Introduction and Release Information

The Windows NT Assembler for Alpha systems converts assembly language statements into Alpha machine code. In most assembly languages, each instruction corresponds to a single machine instruction. Some instructions in this assembly language can, however, generate several machine instructions. This feature results in assembly programs that can run without modification on future machines that might have different machine instructions.

The assembler is intended primarily for producing object modules from the assembly instructions generated by high-level language compilers such as Microsoft's Visual C++®, Alpha Edition. Because of its limited purpose, the assembler lacks many functions normally present in full-featured products.

Important! Please read the Release Notes topic for the most up-to-date information about the Alpha Assembler.


Release Notes for Version 3.04.00 of the Alpha Assembler

The Release Notes section of the Alpha Assembler documentation contains the most up-to-date information about the assembler's features and use.

1.0 The Microsoft C++ compiler program CL.EXE must be installed in order for the Alpha assembler preprocessor to run correctly. Preprocessing can be optionally bypassed by using the /nopp command-line option.

2.0 Command syntax

ASAXP [options] <filename>

where <filename> is the name of the assembly source file. The ASAXP assembler assumes that a source filename extension of .I means that the source has already been preprocessed. The options are listed below.

3.0 Basic command-line options:

  • /? — Display list of supported options.

  • /help — Display list of supported options.

  • /arch<symbol> — Where <symbol> can be defined as follows:

    EV4 — Generate instructions for the EV4 architecture.

    EV5 — Generate instructions for the EV4 architecture.

    EV56 — Generate instructions for the EV56 architecture.

    EV6 — Generate instructions for the EV56 architecture (EV6 in future).

    HOST — Generate instructions for the machine on which the assembler is executing.

    GENERIC — Generate instructions that most current Alpha chips use (currently EV5).

    Note: Whitespace can optionally precede the case-insensitive <symbol>.

  • /D<symbol> — Tells the C preprocessor the definition of <symbol>.

  • /D<symbol>=<string>

  • /E — Writes the preprocessor output to standard output (same as C compiler's /E option).

  • /I<dir> — Tells the preprocessor to search <dir> for INCLUDE files. Whitespace can optionally precede <dir>.

  • /U<symbol> — Tells the C preprocessor to undefine <symbol>.

  • /Gy — Procedure Linking. When used, each procedure is placed in its own section.

  • /Fo <output_filename> — Specifies an output filename other than the default. (The default is the basename of the source file with the .OBJ extension.)

  • /O0 — Turn off code-scheduling optimization.

  • /O1 — Turn on code-scheduling optimization (default).
    • /noloc — Ignore the .loc and .file directives.
  • /nologo — Suppress the logo.

  • /nopp — Do not invoke the C preprocessor.

  • /nowrn — Do not warn if the .end directive does not refer to the current procedure name.

  • /wnt3.1 — Generate object files compatible with the wnt 3.1 linker.

  • /QAltls — Set flag for a large thread local storage (tls) section.

  • /QApdst — Set EXCEPTION_MODE_SILENT (default).

  • /QApdsg — Set EXCEPTION_MODE_SIGNAL.

  • /QApdsa — Set EXCEPTION_MODE_SIGNAL_ALL.

  • /QApdie — Set EXCEPTION_MODE_IEEE.

  • /QApdca — Set EXCEPTION_MODE_CALLER.

  • /QAarchEV4 — Generate instructions for the EV4 architecture (default).

  • /QAarchEV5 — Generate instructions for the EV4 architecture.

  • /QAarchEV56 — Generate instructions for the EV56 architecture.

  • /QAarchEV6 — Generate instructions for the EV56 architecture (EV6 in future).

  • /QAtuneEV4 — Schedule instructions for the EV4 architecture.

  • /QAtuneEV5 — Schedule instructions for the EV5 architecture (default).

  • /QAtuneEV56 — Schedule instructions for the EV5 architecture.

  • /QAtuneEV6 — Schedule instructions for the EV4 architecture (EV6 in future).

  • /QA21064 — Generate and schedule instructions for the EV4 architecture.

  • /QA21066 — Same as /QA21064.

  • /QA21064A — Same as /QA21064.

  • /QA21066A — Same as /QA21064.

  • /QA21164 — Generate instructions for the EV4 architecture and schedule for the EV5 architecture (default).

  • /QA21164A — Generate instructions for the EV56 architecture and schedule for the EV5 architecture.

  • /QA21264 — Generate instructions for the EV56 architecture and schedule for the EV5 architecture (EV6 in future).

  • /tune<symbol> — Where <symbol> can be defined as follows:

    EV4 — Schedule instructions for the EV4 architecture.

    EV5 — Schedule instructions for the EV5 architecture.(default).

    EV56 — Schedule instructions for the EV5 architecture.

    EV6 — Schedule instructions for the EV5 architecture (EV6 in future).

    HOST — Schedule instructions appropriate for the machine on which the assembler is executing.

    GENERIC — Schedule instructions that most current Alpha chips use (currently EV5).

    Note: Whitespace can optionally precede the case-insensitive <symbol>.

  • /V — Display assembler version.

  • /v — Verbose. Displays command line to preprocessor and assembly options.

  • /Zd — Limited debugging. Inserts line numbers into symbol table.

  • /Zi — CodeView™ symbolic information is emitted.

4.0 Advanced command-line options:

  • /symbols_aligned_0mod4 — Default. Assume symbols are longword aligned.

  • /symbols_not_aligned — Do not make assumptions about symbols.

  • /stack_aligned_0mod8 — Default. Assume stack is aligned on quadword boundary.

  • /stack_not_aligned — Do not make any assumptions about stack alignment.

  • /thread_pointer_aligned_0mod8 — Default. Applies to TLS section. Assume that the thread pointer is quadword aligned.

  • /thread_pointer_not_aligned — Do not make any assumptions about the thread pointer.

  • /resumption_safe — This option tightens up the scheduling for floating point instructions. This is primarily intended in cases where the programmer wants to catch floating point exceptions.

  • /diag_pipe — Print out the scheduling pipeline (only when /O1 is set).

  • /1, /2, /3, /4 - Allow debugging output after assembler phase. These options are used with other debug options. Note that /4 provides output before and after scheduling. /1 - Parse, /2 - Layout, /3 - Encoding, /4 - Encoding and Scheduling.

  • /dump_ir — Display internal instruction table. Must have one or more of the phases set.

  • /dump_sym — Display the internal symbol table. Must have one or more of the phases set. Also displays the coff symbol table when /3 or /4 is set.

  • /dump_inst — Display the internal instruction encoding table.

  • /dbg_out[&]<file> — Redirect debug output to <file name>. If & precedes name, then append to file.

  • /err_out[&]<file> — Redirect error output to <file name>. If & precedes name, then append to file.

5.0 Options provided for compatibility with the ACC and DIGITAL™ UNIX® assembler:

  • /eflag number — Set exception mode to specified number.

  • /g, /g2, /g3 — Same as /Zi.

  • /g1 —Same as /Zd.

  • /g0 — No debug (default).

  • /G <num> — Ignored.

  • /o <filename> — Same as /Fo.

  • /std, /std0, /std1 — Ignored.

  • /t <filename> — Ignored.

6.0 Options accepted by the assembler, but silently ignored:

  • /a /b /c /coff /d /l /M /n /p /w /X /z

7.0 Differences from the DIGITAL UNIX assembler, as0/as1 (a.k.a. acc)

Directives

  • The following directives are silently ignored:

    .set volatile/novolatile,

    .bgnb, .gjsrlive, .lab, .livereg, .option, .vreg, .weakext, .ugen, .alias, .noalias

  • The following directives generate warnings when encountered:

    .const, .gjsrsaved, .gprel32, .gretlive, .save_ra

  • .aent Directive

    The as0/as1 assembler would insert a nop instruction — for example, bis $31, $31, $31, when an .aent directive is specified immediately after an .ent directive.

    ASAXP does not insert an additional instruction.

    Updated for version 3.02.0. The .aent directive is fully supported, and will cause procedure descriptors to be inserted into the .pdata section.

  • .edata Directive

    .edata <flag> <exception_data> <lang_handler>

    If flag is 0, the current section changes to .xdata.

    If flag is 1, the exception data and language handler are inserted into the procedure descriptor for the current procedure. If the .edata directive precedes the .ent directive, the information applies to the next .ent directive.

  • .eflag Directive

    .eflag number

    This sets the exception mode bits in the procedure descriptor for the current procedure. This overrides the default set by the /QApd xx command line options. ASAXP treats the number as an expression.

  • .end Directive

    The as0/as1 compiler would ignore the optional symbol following the .end directive.

    ASAXP checks that an .ent directive is active for any symbol argument to the .end directive. In addition, ASAXP verifies that the procedure is terminated within the proper section.

    ASAXP generates a .end directive when encountering a .ent directive when a procedure is active, or when encountering an end of file when a procedure is active. In both cases a warning is issued.

7.1. Unsupported instructions

The ldgp instruction is silently ignored by ASAXP.

7.2. Code generated

The code generated by ASAXP is meant to be functionally equivalent to as0/as1; however, it is not identical.

7.3. Optimizations

ASAXP makes no attempt to optimize code. The code must be optimized "by hand."

The as0/as1 assembler attempts to keep track of register contents in the emitted code. For instance:

ldiq $3, 0x7fff0001
ldiq $4, 0x7fff0002

is emitted as three instructions by as0/as1 because it realizes the second constant can be built from the first. ASAXP does not do this and will generate four instructions.

The as0/as1 assembler has a similar ability to do this with relocatable expressions, an ability that ASAXP does not have.

The as0/as1 assembler uses tricky ways to load constants that are larger than 2**32. ASAXP also tries to reduce constants. Those constants that are not reduced are placed in a constant pool.

7.4 Code scheduling (reordering)

ASAXP uses a post-generation code scheduler to reorder instructions based on the characteristics of the individual instructions in the architecture. This reordering generally results in faster performance. It does, however, affect the line number information used by the debugger. The reordering algorithms used are consistent with as0/as1.

7.5 Corrected instruction encodings

The as0/as1 assembler does not encode the excb, mb, rpcc, trapb, and wmb instructions correctly. ASAXP has the correct encodings.

7.6 jsr Instructions

The as0/as1 assembler transforms jsrd" instructions with symbolic operands to bsr instructions.

ASAXP generates the long form of the jsr (ldah-lda-jsr sequence using register $at) for such cases. If a bsr instruction is desired, then the code should be modified to use bsr with a symbolic operand.

7.7 Preprocessor

ASAXP uses the CL command for preprocessing the source files. One limitation from this is that it is not legal to use the pound (#) character to begin an end-of-line comment in #include files.

ASAXP does work to make it legal to use the pound(#) character to begin an end-of-line comment in the main source file (the file specified on the command line).

The C++ style comment (//) still works in header files.

7.8 Libc.lib

References to the divide and remainder instructions actually get transferred to calls to special run-time library routines.

These routines can be found in the system library libc.lib.

7.9 Other

The as0/as1 assembler emits local BRADDR relocation records for unconditional branches to local labels. Since branches are pc-relative and the distance to the target is known if the symbol is local, ASAXP fills in the correct branch displacement itself. Relocations are issued for non-local branches as well as branches between sections.

8.0 Features added for version 2.0 to support Windows NT 3.5

8.1. The maximum value for the .align directive is 6, not 4.

Section alignments are adjusted based upon the strictest alignment specified by a .align directive within that section. Please note that the .align directive specifies the low-order bits of the PC to be cleared, not the boundary. To align on a quadword (8 byte) boundary, use .align 3, not .align 8.

8.2. Command-line options have been updated:

/Zi — Same as /g or /g2. Emit CodeView™ debugging information.

/Zd — Same as /g1. Emit COFF line numbers.

/O0 — Turn off code scheduling optimization.

/O1 — Turn on code scheduling optimization (default).

/nologo — Suppress the logo.

/wnt3.1 — Generate object files compatible with the WNT 3.1 linker.

The following command-line options set the default exception handling run time procedure descriptor flags. Please refer to Windows NT for Alpha Calling Standard.

/QApdst — Set EXCEPTION_MODE_SILENT (default).

/QApdsg — Set EXCEPTION_MODE_SIGNAL.

/QApdsa — Set EXCEPTION_MODE_SIGNAL_ALL.

/QApdie — Set EXCEPTION_MODE_IEEE.

/QApdca — Set EXCEPTION_MODE_CALLER.

/eflag number — Set the default exception handling.

/symbols_aligned_0mod4 — Symbols are longword granular (default).

/symbols_not_aligned — No attempt is made to align symbols.

/stack_aligned_0mod8 — Stack is aligned on quadword boundary.

/stack_not_aligned — No attempt is made to align the stack.

8.3. Store byte (stb) and store word (stw) pseudo instructions

The store byte (stb) and store word (stw) pseudo instructions use one additional register, $t11. The assembler now uses the additional registers $at, $t9, $t10, and $t11. The stb and stw instructions are implemented as hardware instructions by the 21164-333 and newer processors. (See section 6.4, below.)

8.4. The nomove and noreorder assembler options

The nomove and noreorder assembler options behave identically as documented under the .set nomove directive.

8.5. Errors and warnings

Errors and warnings are now issued to stdout so they can be optionally redirected.

8.6. Internally generated symbols

Internally generated symbols are now emitted to the COFF symbol table. The generated names have the form $$nnn. Since $$nnn names are also generated by the acc compiler, the ASAXP-generated names are guaranteed to be unique.

8.7 Identifier names can now contain the @ and ? characters.

8.8 The load and store sequences are now longword granular.

8.9 Added a new directive, .tls$, for thread local storage.

8.10 The .extern directive now contains a modifier, .extern (thread) <symbol>

9.0 Features added for version 2.02.

9.1 Procedure linking (/Gy).

The /Gy command-line option causes every procedure to be placed into a section by itself. This is compatible with VC++ function linking.

9.2 Syntax for section directives

The syntax for the section directives .text, .data, .rdata, .tls$, and .sdata has been extended. The new syntax is:

.text [identifier]
.data [identifier]
.rdata [identifier]
.tls$ [identifier]
.sdata [identifier]

The identifier parameter is optional. If specified, that identifier is used to name the section. If identifier is not specified, the section name is generated by asaxp as standard section names. There is no limit to the length of a section name. The same rules that apply to other identifiers also apply to section names. Section names are maintained in a separate name space from other symbols used in the assembler.

There is a special case of the .text directive. The assembler allows a non-text directive to occur within the scope of a procedure. The use of the .text directive following the non-text instructions causes the assembler to reset its context to the procedure. The Alpha Asssember does produce a warning in this case. This feature has been retained in asaxp to support code generated by the acc compiler. For example:

.text dohello # Assign the following code to the dohello section
.ent dohello
dohello:
lda    $sp, -16($sp)
stq    $26, 0($sp)
.prologue
.rdata hello_world    # Assign the following code to the hello_world
# section. Note that asaxp does produce a warning.
hello:
.asciiz    "Hello world\n"
.text # Restore context to the dohello section
lda    $16, hello
bsr    $26, printf
ldq    $26, 0($sp)
lda    $sp, 16($sp)
ret    $31, ($26), 1
.end

9.3 Interaction between procedure linking and using named sections.

With /Gy in effect, each procedure is placed in a separate section. That section is named .text. There may be multiple .text sections. If the programmer elects to place a procedure into a named section other than .text, that is permissible. There is one caveat: The named section specified by the programmer must be empty. If it is not empty, the procedure linking code will cause the following procedure to be placed into a new .text section.

9.4 Additional error checking on sections.

The assembler does not allow a procedure to be declared in other than a .text section. Instructions occurring in non-text sections cause the assembler to flag an error.

9.5 Symbols defined by a symbolic equate can now be exported:

.global foo
foo = <some constant>

9.6 Subtraction of two identifiers

The subtraction of two identifiers is now permitted as part of a constant expression. An optional expression can follow the symbolic difference.

The expression is limited to addition, subtraction, multiplication, and division binary operators. The normal expression evaluation rules have been altered a bit such that the symbolic difference is assumed to be contained within parentheses. The expression following the binary operator can be any legal constant expression.

foo:
.quad bar - foo * 2 # The result here is 16.
bar:

10.0 Features added for version 3.01.

10.1 Support for 21164 architecture

Support for the 21164 architecture family, including support for the new word and byte instructions, architecture mask, and implementation version.

Added command-line options and directives to allow selection of new instructions as they are introduced. The default architecture is currently EV4 with EV5 scheduling.

The term <arch argument> is used to specify the architecture or tuning features (uppercase or lowercase):

EV4 — Available in all chips.

EV5 — For /arch, same as EV4. For /tune, selects scheduling for the 21164 chip architecture.

EV56 — For /arch, emit byte instructions. For /tune use 21164 scheduling.

EV6 — Same as EV56. Will reflect the 21264 chip when available.

HOST — Generate instructions or tune as appropriate for the system on which the code is assembled.

GENERIC — Generate instructions or schedule based on the most prevalent Alpha architecture. At present, this is EV5, but will change in the future.

10.2 New command-line switches for architecture selection

Added command-line options for new Alpha chip architectures. These switches are compatible with VC++ 4.0 and DIGITAL UNIX. The QA21 family set both the architecture and tuning parameters. The /arch, /tune, /QAarch, and /QAtune options work independently of each other.

/QA21064 — Generate and schedule instructions for the EV4 architecture.

/QA21066 — Same as /QA21064.

/QA21064A — Same as /QA21064.

/QA21066A — Same as /QA21064.

/QA21164 — Generate instructions for the EV4 architecture and schedule for the EV5 architecture (default).

/QA21164A — Generate instructions for the EV56 architecture and schedule for the EV5 architecture.

/QA21264 — Generate instructions for the EV56 architecture and schedule for the EV5 architecture (EV6 in future).

/QAarch<arch argument> — Generate instructions based on <arch argument>.

/arch <arch argument> — Generate instructions based on <arch argument>.

/QAtune<arch argument> — Schedule based on <arch argument>.

/tune <arch argument> — Schedule based on <arch argument>.

Some additional options have been added to be silently ignored for compatibility with Microsoft's masm assembler.

10.3 Two new arch directives.

These directives override the command-line options.

.arch <arch argument> — Generate instructions based on <arch argument>.

.tune <arch argument> — Schedule based on <arch argument>.

10.4 Macro substitution in the .repeat/.endr block.

The %r token may be used within an identifier. This expands to the repeat iteration number, starting at 0. For example:

.repeat 3
.globl aglob%r
.endr
This expands to:
.globl aglob0
.globl aglob1
.globl aglob2

10.5 Added ldbu, ldwu, stb, and stw instructions for EV56.

These instructions are implemented as pseudo instructions for EV4 and prior releases of the assembler.

10.6 Added the sextb and sextw instructions for EV56.

These instructions sign extend byte and word respectively. These are new instructions as of ASAXP release 3.01.0. These instructions have the same syntax as the sextl instruction. They are implemented as pseudo instructions for EV4 and EV5. Note that the immediate value versions of these instructions are implemented as pseudo instructions, with the sign extension being performed at assembly time.

10.7 Added encodings for the amask and implver instructions.

These instructions test the architecture and implementation variants of the machine. These instructions are supported on all architectures.

10.8 Architecture Mask Syntax

amask $s_reg, $d_reg
amask $d_reg/$s_reg
amask val_immed, $d_reg

The source register or immediate value represents a mask of architectural extensions requested. Bits corresponding to architectural extensions that are present are cleared; reserved bits and bits corresponding to absent extensions are copied unchanged. The result is placed into the destination register. If the result is zero, all requested features are present. Software may specify a source value of all 1's to determine the complete set of architectural extensions implemented by a processor.

Bit | Feature
0 | Byte/Word instructions are present
1..63 | Reserved.

10.9 Implementation Version Syntax:

implver $d_reg

A small integer is placed into the destination register. The integer specifies the major implementation version of the processor on which it is executed. This information can be used to make code-scheduling or tuning decisions, or it can be used to branch to different pieces of code optimized for different implementations.

Value | Implementations
0 | For EV4, EV45, LCA and LCA 45 chips (21064, 21064A, 21066, 21068, and 21066A)
1 | For EV-5 and EV56 chips (21164, 21164A)
2 | For EV-6 and derivative chips (21264, etc).

10.10 Added EV5 code scheduling.

Code scheduling may be altered by setting the command-line option (as noted in section 6.1) or by using the .tune directive (as noted in section 6.2). Code scheduling is performed on a basic block. In asaxp, an extended basic block is a block of code with a single entry point and possibly multiple exit points. In addition, the .prologue directive starts a new basic block. The .tune directive may start a basic block if the tuning context is changed. Conditional branch instructions are included within an extended basic block. This enhances the scheduling in cases where the branch is not taken.

Example using a single source code block for run-time architecture determination:

.text
.tune ev5 # Select 21164 tuning. Will run ok for 21064.
.arch ev4 # Default EV4 architecture
# Prototype:char *cpystr(char *, const char *);
.globl cpystr
.ent cpystr
cpystr:
mov $16, $0 # Save return value
amask 1, $1 # Test if hardware ldbu/stb is present
beq $1, while1 # If bit 0 == 0, go to second sequence.

# Generate 2 sequences of instructions. The first instance
# generates code for the 21064 and the early 21164 chips.
# The second sequence will cause the ldbu/stb hardware
# instructions to be generated. These are supported by the
# 21164-366 and later versions of the 21164 chips.
# Note that .arch EV56 directive at the end of the sequence
# will cause the assembler to switch into EV56 mode.

 .repeat 2
while%r: # This is while0 for first instance,
 # while1 for second
 ldbu $1, ($17) # Get source byte
 stb $1, ($16) # Store to destination
 beq $1, done # If at EOS, return.
 addq $16, 1, $16 # Next destination
 addq $17, 1, $17 # Next source
 br while%r
 .arch ev56 # Change architecture at end
 # of repetition
 .endr
done:
 ret # dedemau
 .end cpystr

10.11 Relocation operands

Relocation operands are generally useful in three situations:

  • As support for independent expression of the high and low addresses.

  • In application programs in which the programmer needs precise control over scheduling

  • In source code written for compiler development

    Some macro instructions (for example, lda) require special coordination between the machine-code instructions and the relocation sequences given to the linker. By using the macro instructions, the assembler programmer relies on the assembler to generate the appropriate relocation sequences.

    In some instances, the use of macro instructions may be undesirable. For example, a compiler that supports the generation of assembly language files may not want to defer instruction scheduling to the assembler. Such a compiler will want to schedule some or all of the machine-code instructions. To do this, the compiler must have a mechanism for emitting an object file's relocation sequences without using macro instructions. The mechanism for establishing these sequences is the relocation operand.

    A relocation operand is placed after the normal operand on an assembly language statement. The syntax of the relocation_operand is as follows:

    !relocation_type! sequence_number or
! sequence_number
relocation_type

    Any one of the following relocation types can be specified:

  • braddr — Branch address.

  • hint — Jump hint.

  • poffset — Procedure offset.

  • refhi — High reference. Associated with an ldah instruction, this is normally accompanied by a Pair relocation.

  • sechi — Similar to refhi. This is for use by TLS.

  • reflo — This is associated with a load, store, or lda instruction. The associated instruction may be the target of a pair relocation.

  • seclo — Similar to reflo. This is for use by TLS.

  • reflong — Longword relative reference. This is used when the address of a symbol is stored by a .long directive.

  • refquad — Quadword relative reference. This is used when the address of a symbol is stored by a .quad directive.

  • snum — Section number.

  • soffset — Section offset.

    The relocation types must be enclosed within a pair of exclamation points (!) and are not case sensitive. Only refhi, sechi, reflo, and seclo are useful in ASAXP.

    The sequence number is a positive integer constant with a value range of 1 to 2147483647. The sequence number may be specified in decimal, hex, or octal notations.

    The following examples contain relocation operands in the source code:

    # Equivalent C statement:
# extern __int64 sym1, sym2;
# sym1 += sym2;

    Assembly statements containing macro instructions:

     ldq $1, sym1
 ldq $2, sym2
 addq $1, $2, $3
 stq $3, sym1

    Assembly statements containing machine-code instructions requiring relocation operands. In asaxp, an ldah instruction using a symbol without a relocation operand will produce a syntax error. By using the relocation operands, an ldah instruction is eliminated.

    ldah $4, sym1!refhi!1    # Load high value for sym1.
ldah $5, sym2!refhi!2    # Load high value for sym2.
ldq $1, sym1($4)!reflo!1 # Load sym1. Paired to ldah.
ldq $2, sym2($5)!reflo!2 # Load sym2. Paired to ldah.
addq $1, $2, $3
stq $3, sym1($4)!reflo!1 # Store value in sym1 unpaired.

10.12 Support for large tls section.

The /QAltls command-line option turns on large thread local storage for the entire module. Use the relocation operand to control references at an instruction level.

11.0 Features added for release 3.02.0.

Support for EV6 ECO 84, 87, 88, 90, 96. These new instructions require either the .arch ev6 directive or /arch ev6 command-line option. These instructions are generated as primitive instructions for all architectures. However, when these are unimplemented, the hardware will generate an OPDEC trap. Added support for .split directive.

11.1 ECO 84 - SQRT instructions.

SQRTx Fb.rx, Fc.wx

VAX Modes:

SQRTF - F_floating

SQRTG - G_floating

Includes qualifiers s, c, u (e.g., sqrtgsuc).

IEEE Modes:

SQRTS - S_floating

SQRTT - T_floating

Includes qualifiers d, m, c, s, u, i (e.g., sqrtssuic).

11.2 CTPOP/CTLZ/CTTZ

CTPOP Rb.rq, Rc.wq

CTLZ Rb.rq, Rc.wq

CTTZ Rb.rq, Rc.wq

11.3 Integer/Floating Register moves.

FTOIx Fa.rq, Rc.wq

FTOIS - s_floating to longword.

FTOIT - t_floating to quadword.

ITOFx Ra.rq, Fc.wq

ITOFS - Longword to s_floating

ITOFF = Longword to f_floating

ITOFT - Quadword to t_floating

11.4 Instructions for Graphics and Video Algorithms

PERR Ra.rq, Rb.rq, Rc.wq - Pixel Error
MINxxx Ra.rq, Rb.rq, Rc.wq
MAXxxx Ra.rq, Rb.rq, Rc.wq
MAXSB8 - Vector Signed byte Maximum
MAXSW4 - Vector Signed word Maximum
MAXUB8 - Vector Unsigned byte Maximum
MAXUW4 - Vector Unsigned word Maximum
MINSB8 - Vector Signed byte Minimum
MINSW4 - Vector Signed word Minimum
MINUB8 - Vector Unsigned byte Minimum
MINUW4 - Vector Unsigned word Minimum
UNPKBx Rb.rq, Rc.wq
UNPKBL Unpack Bytes to Longwords
UNPKBW Unpack Bytes to Words
PKxB Rb.rq, Rc.wq
PKLB Pack Bytes to Longwords
PKWB Pack Bytes to Words

11.5 Data Cache Control Instructions

WH64 (Rb.ab) - Write Hint - 64 bytes
ECB (Rb.ab) - Evict Cache Block

11.6 Added support for NTOM and other profiling tools.

This includes the addition of the .split directive. A related change is that data directives (e.g., .long) that are placed within a procedure cause the assembler to generate an additional procedure descriptor such that tools like NTOM may move code segments efficiently.

.split proc_name

The proc_name refers to the procedure name of the associated mainline procedure. The proc_name must have been the subject of a previous .ent directive. The .split directive differs from the .aent directive in that it is part of the referenced procedure, but may not be adjacent to that procedure.

12.0 Features added for 3.03.2

12.1 Support for GEM-generated .s files.

12.2 Added .tlscomm directive.

.tlscomm name, expression[, section identifier]

The .tlscomm directive causes name (unless defined elsewhere) to become a global common symbol at the head of a block of at least expression bytes of storage within the .tls$ section. The linker overlays like-named common blocks, using the expression value of the largest block as the byte size of the overlay. If section identifier is selected, it will be appended to .tls$.

12.3 Added the .comdat directive

.comdat symbol [ comdat type [ section identifier ]]

The .comdat directive declares the referenced symbol to be a comdat symbol. If specified, the comdat type is one of (case insensitive):

"IMAGE_COMDAT_SELECT_NODUPLICATES"

"IMAGE_COMDAT_SELECT_ANY"

"IMAGE_COMDAT_SELECT_SAME_SIZE"

"IMAGE_COMDAT_SELECT_EXACT_MATCH"

"IMAGE_COMDAT_SELECT_ASSOCIATIVE"

"IMAGE_COMDAT_SELECT_LARGEST"

"IMAGE_COMDAT_SELECT_NEWEST"

These correspond to the definitions of the same names in winnt.h.

The "IMAGE_COMDAT_SELECT_" may be omitted as well as "_SIZE" or "_MATCH".

If comdat type is not specified, the comdat type defaults to IMAGE_COMDAT_SELECT_EXACT_MATCH. If the comdat type is IMAGE_COMDAT_SELECT_ASSOCIATIVE, then the section identifier is required, and it must be the name of a section defined within the compilation unit.

12.4 Added the .drectve directive.

.drectve string [, string]...

The .drectve directive places linker directives in the object file into the .drectve section. This directive may appear anywhere in the source file, and does not change the current section context. The string must be enclosed in quotation marks ("). Each string is padded by a single space as required by the linker.

.drectve "-defaultlib:libc", "-defaultlib:oldnames"

12.5 Added the .section directive

.section section-name[,Coff section name ] [section-attribute[, section-attribute]...

Where section-attribute is one of the IMAGE_SCN_ manifest constants that are defined in winnt.h. The full attribute name (e.g., IMAGE_SCN_xxx) or the suffix may be used as shorthand.

For alignment purposes, the assembler will assume that CNT_CODE or MEM_EXECUTE characteristics are text type sections, and will generate nops to fill gaps. All other sections are treated as data, and the assembler will fill in with binary zeros. The assembler will use whatever values are selected for the object file section header, and makes no attempt to warn in the event of a conflict. Section attributes are read together bitwise.

It is important that thread-local-storage data sections contain the section name beginning with .tls. This affects relocations. However, relocation operands can supply the correct relocations.

The COFF section name is a quoted string containing the name that will be placed into the symbol table for this section. The assembler does not look at this name. If not supplied, the section name will be the asaxp section name.

If the section directive is used without characteristics, a lookup for that name is performed, and the first section in the section table matching that name is chosen. If attributes are supplied, the lookup will match by both name and attributes. If the assembler is unable to find an appropriate match, a new section is created. Also note that there are standard section names. The assembler creates empty sections with names of .text, .rdata, .xdata, .pdata, .data, .sdata, .tls$, .debug$, .debug$, .drectv, and .bss.

.section .text
# lookup a section named ".text", and set context to that section.
.section gallagher
# Lookup a section named gallagher. If found, the context is changed
# to the gallagher section. If not found, an error is generated concerning
# unknown attributes
.section .text "CNT_CODE", "MEM_EXECUTE", "MEM_WRITE"
# The assembler will seach for a section containing these attributes with
# a name .text and create one if one is not found. The assembler will
# not make any judgements even though the attributes conflict.
Attribute name:
IMAGE_SCN_CNT_CODE
IMAGE_SCN_CNT_INITIALIZED_DATA
IMAGE_SCN_CNT_UNINITIALIZED_DATA
IMAGE_SCN_LNK_OTHER
IMAGE_SCN_LNK_INFO
IMAGE_SCN_LNK_REMOVE
IMAGE_SCN_LNK_COMDAT
IMAGE_SCN_ALIGN_1BYTES
IMAGE_SCN_ALIGN_2BYTES
IMAGE_SCN_ALIGN_4BYTES
IMAGE_SCN_ALIGN_8BYTES
IMAGE_SCN_ALIGN_16BYTES
IMAGE_SCN_ALIGN_32BYTES
IMAGE_SCN_ALIGN_64BYTES
IMAGE_SCN_ALIGN_1KBYTES
IMAGE_SCN_MEM_DISCARDABLE
IMAGE_SCN_MEM_NOT_CACHED
IMAGE_SCN_MEM_NOT_PAGED
IMAGE_SCN_MEM_SHARED
IMAGE_SCN_MEM_EXECUTE
IMAGE_SCN_MEM_READ
IMAGE_SCN_MEM_WRITE

13.0 Features added for 3.04.00

13.1 Support for /nosplit and /noaent command-line options.

The /nosplit option prevents the assembler from automatically generating split procedures.

The /noaent option disallows the specification of alternate entry points.

13.2 Added support for .set[no]aent and .set[no]split directives.

These directives instruct the assembler to enable or disable specific options. The assembler uses aent and split as default options.

  • The aent option allows the specification of alternate entry points.

  • The noaent option disallows the specification of alternate entry points.

  • The split option allows the assembler to automatically generate split procedures.

  • The nosplit option prevents the assembler from automatically generating split procedures.

13.3 Support /Ap64 command-line option.

This option directs the assembler to generate code using a 64-bit addressing model.

13.4 Support /Gt n command line option and GP-relative addressing for .sdata items.

13.5 Added optional "expected size" argument to .extern directive.

When /Gt n is specified on the command line, data items specified with a size less than or equal to n will be addressed with GP-relative addressing (rather than the ldah/lda pairs). Assumes that the defining instance of such an external is declared in the .sdata section in another object file.

An optional "expected size" argument may now be specified with a .extern that allows correct placement of the extern in .sdata by the assembler.

13.6 Changed allocation of .bss and .sbss sections.

The allocation of symbols within the .bss and .sbss sections has been changed so that it corresponds to the order in which .lcomm directives appear in the assembler source.

13.7 Changed naming convention used for internally generated labels.

The naming convention used for internally generated labels has been changed from ~ngenlab to ~Ln.

13.8 Added support for extension relocations.

The previous limit on the number of relocations that could be applied to an individual section (65535) has been removed due to the implementation of extension relocations.


Copyright Notice and Disclaimers

Notice

The information in this guide is subject to change without notice.

COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL ERRORS OR OMISSIONS CONTAINED HEREIN; NOR FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THE MATERIAL.

This guide contains information protected by copyright. No part of this guide may be photocopied or reproduced in any form without prior written consent from Compaq Computer Corporation.

© 1998 Compaq Computer Corporation.

All Rights Reserved.

Portions of this information are © 1990 MIPS Computer Systems, Inc.

COMPAQ and the Compaq logo
Registered in the United States Patent and Trademark Office.

AlphaServer,AlphaStation, DIGITAL, and the DIGITAL logo are trademarks of Compaq Computer Corporation.

CodeView, Visual C++, Windows, and Windows NT are registered trademarks of Microsoft Corporation.

The software described in this guide is furnished under a license agreement or nondisclosure agreement, the software may be used or copied only in accordance with the terms of the agreement.

Product names mentioned herein may be trademarks and/or registered trademarks of their respective companies.


Intended Users

The Windows NT Assembler for Alpha systems is provided for experienced assembly language programmers who need to:

  • Maximize the efficiency of a routine, for example, in a low-level I/O driver, which might not be possible in another high-level language such as C, Fortran-77, or Pascal.

  • Access machine functions unavailable from high-level languages or satisfy special constraints such as restricted register usage.


Associated Documents

Refer to the following publication for further information about the Alpha architecture:

Alpha Architecture Reference Manual, 3rd Edition
By Digital Press
Published for Digital Press by Butterworth-Heinemann
© 1998

You can obtain this publication by calling Butterworth-Heinemann at 781-904-2500 and ordering part number EY-W938E-DP, or by going to your favorite technical bookstore and ordering ISBN number 1-55558-202-8.

This assembler documentation also refers to the following document, which is included with Microsoft Visual C++ 6.0 for Alpha Systems:

Windows NT for Alpha Systems Calling Standard.


Typographic Conventions

This assembler Help file uses the following typographic conventions:

Convention | Description
literals | When used alone, bold text indicates a heading. In the context of a command line, bold text indicates text that should be typed exactly as shown.
variables | Italic text indicates text you must type, substituting actual values for the placeholder names supplied.
Monospace | Monospaced text indicates example code.
CAPS | Capital letters indicate a drive or path.
$ | The dollar sign ($) is the first character in a register name.
[[text in double square brackets]] | Text in double square brackets is optional.
text in curly braces with a vertical bar e.g., {a|A} | Text in curly braces separated by a vertical bar is required. You must choose a value from one or the other side of the vertical bar.

As applicable, the following types of information are provided for each instruction or assembly directive listed:

Section | Description
Syntax | This section shows the mnemonic and operands for each instruction or assembly directive. If an instruction accepts more than one string of operands, the Syntax section contains a separate line for each operand string. For example: divf $s_reg1, $s_reg2, $d_reg divf $d_reg/$s_reg1, $s_reg2
Description | This section describes the function of the instruction or assembly directive, what it does with the given operands, and any side effects. The instruction descriptions also include one of the following hotspots, whichever is appropriate, to provide quick access to operand descriptions:
 | Main Instruction Operand Descriptions
 | Floating-Point Instruction Operand Descriptions
Qualifiers | This section appears only in floating-point instruction descriptions. Many floating-point instructions accept one or more appended letters that specify particular rounding and trapping modes. See Divide F_floating (divf) for an example of a Qualifiers section. See Also Floating-Point Instruction Qualifiers for descriptions of the rounding and trapping mode qualifiers.


Command-Line Syntax

To assemble your programs, use the ASAXP command.

Note The Microsoft C++ compiler program CL.EXE must be installed for the Alpha assembler preprocessor to work.

The Alpha assembler command line uses the following syntax:

ASAXP options variables \\path\filename

where filename is the name of the assembly source file. The command assumes that a .I filename extension means that the source has already been preprocessed.


Command Options

The Alpha assembler (ASAXP) command options are listed in the following table. References provide more information about some of the options.

Option | Description | Footnote
/? /help | Display help text. |
/Dsymbol | Define constants and macros. | (1)
/Dsymbol=string |  |
/E | Writes preprocessor output to standard output. Works the same as the compiler’s /E option. |
/eflag flags | Encode the exception-related flags to be stored in the PDSC_RPD_FLAGS field of the procedures run-time procedure descriptor. This is equivalent to the .eflag directive_except that it is for the entire module. | (2)
/Fo filename /o filename | Specify an output filename other than the default. The default is the base name of the source file with the extension .OBJ. |
/Gy | Enables procedure linking, which places each procedure in its own section. |
/I | Specify path for include files. | (1)
/L DIR | Tells the preprocessor to search the directory indicated for include files. |
/noloc | Ignore the .loc and .file directives. |
/nologo | Suppress the display of the sign-on banner. |
/nopp | Do not invoke the C language preprocessor on the input file. |
/nowrn | Do not warn if the if the .end directive does not refer to the current procedure name. |
/O0 | Turn off code scheduling optimization. |
/O1 | Turn on code scheduling optimization (default). |
/QA21064, /QA21064A, /QA21066A | Generate and schedule instructions for the EV4 processor. |
/QA21164 | Generate instructions for the EV4 and schedule instructions for the EV5. |
/QA21164A | Generate instructions for the EV56 and schedule instructions for the EV5. |
/QA21264 | Generate instructions for the EV56 and schedule instructions for the EV5 (EV6 in the future). |
/QAarch [[EV4|EV5|EV56|EV6|HOST|GENERIC]] | Generate instructions for the indicated processor. EV4 is the default. |
/QAltls | Set flag for a large thread local storage section. |
/Qapdca | Set the exception-related flags to EXCEPTION_MODE_CALLER. This should be used if the user is writing an RTL that should behave according to the user’s exception mode. | (2)
/Qapdie | Set the exception-related flags to EXCEPTION_MODE_IEEE . This should be used if the user desires IEEE behavior when making RTL calls from the assembler. | (2)
/QApdsa | Set the exception-related flags to EXCEPTION_MODE_SIGNAL_ALL. | (2)
/QApdsg | Set the exception-related flags to EXCEPTION_MODE_SIGNAL. | (2)
/QApdst | Set the exception-related flags to EXCEPTION_MODE_SILENT (default). | (2)
/QAtune [[EV4|EV5|EV56|EV6|HOST|GENERIC]] | Schedules instructions for the indicated processor. EV5 is the default. |
/resumption_safe | Prevent the scheduler from moving floating-point operating instructions. This should be used when using IEEE mode instructions with exception handling. |
/stack_aligned _0mod8 | Align stack on a quadword boundary (default). |
/stack_not_aligned | No attempt is made to align stack. |
/symbols_aligned _0mod4 | Symbols are longword granular (default). |
/symbols_not _aligned | No attempt is made to align symbols. |
/Usymbol | Undefine constants and macros. | (1)
/Zd | Emit line numbers and public symbols for debugging. |
/Zi | Emit CodeView® symbolic information for WINDBG. |
1)For more information, see the descriptions of the /D and /I options for the CL command in the section Using CL in the Microsoft Win32 SDK Tools User's Guide. (2)For more information, refer to the Windows NT for Alpha Calling Standard..


Preprocessing

The Microsoft C++ compiler (CL) is used to preprocess assembly sources. This compiler's preprocessor expands macros into source that is lexically compatible with the Alpha assembler. You can also use preprocessor directives for conditional assembly and for including other files.

Note File names with the extension .I are assumed to have been preprocessed.

For information on using the preprocessor, see the Microsoft C/C++ Language Help.


Alpha Registers

Alpha systems have the following types of registers:

  • Integer registers

  • Floating-point registers

You must use integer and floating-point registers appropriately according to the type of register expected in the assembly instructions. If you confuse the two, the assembler issues an error message.

The assembler reserves all register names. All register names start with a dollar sign ($), and all alphabetic characters in register names are lowercase.


Integer Registers

Alpha systems have 32 integer registers. Each register is 64 bits wide. In other system architectures, integer registers are sometimes referred to as general registers.

The integer registers have the names $0 to $31.

Note You must include the leading dollar sign ($) whenever you specify a register.

Integer register $31 always contains the value 0. All other integer registers can be used interchangeably, except for integer register $30, which is assumed to be the stack pointer (certain PALcode assumes that $30 is the stack pointer).

The following table describes the Alpha integer registers:

Register name | Alternate name | Use
$0 | $v0 | Used for expression evaluations and to hold the integer function results. Not preserved across procedure calls.
$1-$8 | $t0-$t7 | Temporary registers used for expression evaluations. Not preserved across procedure calls.
$9-$14 | $s0-$s5 | Saved registers. Preserved across procedure calls.
$15 | $s6 or $fp | Contains the frame pointer (if needed); otherwise, a saved register.
$16-$21 | $a0-$a5 | Used to pass the first six integer type actual arguments. Not preserved across procedure calls.
$22-$25 | $t8-$t11 | Temporary registers used for expression evaluations. Not preserved across procedure calls.
$26 | $ra | Contains the return address. Preserved across procedure calls.
$27 | $pv or $t12 | Contains the procedure value and used for expression evaluation. Not preserved across procedure calls.
$28 or $at | $at | Reserved for the assembler. Not preserved across procedure calls.
$29 or $gp | $gp | Contains the global pointer for compiler-generated code. Not preserved across procedure calls. Note Register $gp should not be altered. For more information, refer to the Windows NT for Alpha Calling Standard.
$30 or $sp | $sp | Contains the stack pointer. Preserved across procedure calls.
$31 | $zero | Always has the value 0.


Floating-Point Registers

Alpha systems have 32 floating-point registers. Each register is 64 bits wide. Each register can hold one 32-bit single-precision value or one 64-bit double-precision value.

The floating-point registers have the names $f0 to $f31.

Note You must include the leading dollar sign ($) whenever you specify a register.

Floating-point register $f31 always contains the value 0.0. All other floating-point registers can be used interchangeably.

The Alpha floating-point register assignments are as follows:

Register Name | Use
$f0 | Used to hold floating-point type function results. In a standard call that returns a complex floating-point result, this register is used to return the real part of the result.
$f1 | Used to hold floating-point type function results. In a standard call that returns a complex floating-point result, this register is used to return the imaginary part of the result.
$f2-$f9 | Saved registers. Preserved across procedure calls.
$f10-$f15 | Temporary registers used for expression evaluation. Not preserved across procedure calls.
$f16-$f21 | Used to pass the first six single- or double-precision actual arguments. Not preserved across procedure calls.
$f22-$f30 | Temporary registers used for expression evaluations. Not preserved across procedure calls.
$f31 | Always has the value 0.0.


Byte Addressing

This topic describes the byte-addressing schemes for load and store instructions used in aligned data operations and unaligned data operations.

See Also

Atomic Updates


Atomic Updates (lock flags)

Alpha includes two per-processor registers associated with the load locked and store conditional instructions noted below. These instructions together provide for the atomic update of an aligned quadword or aligned longword. Refer to the Alpha Architecture Reference Manual Associated_Documents for further information.

The code sequence below illustrates atomic updates. This load-locked/store-conditional paradigm may be used whenever an atomic update of a shared aligned quadword is desired, including getting the effect of atomic bytes writes.

try_again:
   ldq_l R1, a_quadword //Load and set flag
   stq_c R1, a_quadword //<modify register R1>
   beq R1, no_store
      :
      :
no_store:
   br try_again    //code to check for excessive iterations


Aligned Data Operations

All Alpha systems use the following byte-addressing scheme for aligned data:

  • Access to words requires alignment on byte boundaries that are evenly divisible by 2.

  • Access to longwords requires alignment on byte boundaries that are evenly divisible by 4.

  • Access to quadwords requires alignment on byte boundaries that are evenly divisible by 8.

Any attempt to address a data item that does not have the proper alignment may cause an alignment exception.

Aligned data operations include:

Load Quadword (ldq)

Store Quadword (stq)

Load Sign Extended Longword (ldl)

Store Longword (stl)

Load Word (ldw)

Store Word (stw)


Unaligned Data Operations

The Alpha assembler's unaligned load and store instructions operate on arbitrary byte boundaries. They all generate multiple machine-code instructions. They do not raise alignment exceptions.

Unaligned data operations include:

Unaligned Load Quadword (uldq)

Unaligned Store Quadword (ustq)

Unaligned Load Longword (uldl)

Unaligned Store Longword (ustl)

Unaligned Load Word (uldw)

Unaligned Store Word (ustw)

Unaligned Load Word Unsigned (uldwu)

Load Byte (ldb)

Store Byte (stb)

Load Byte Unsigned (ldbu)

Store Quadword Conditional (stq_c)

Store Longword Conditional (stl_c)

Load Sign Extended Longword Locked (ldl_l)

Load Quadword Locked (ldq_l)


Lexical Conventions

This topic describes the lexical conventions used throughout the Alpha Assembler.


Blank and Tab Characters

You can use blank and tab characters anywhere between operators, identifiers, and constants. Adjacent identifiers or constants that are not otherwise separated must be separated by a blank or tab.

These characters can also be used within character constants; however, they are not allowed within operators and identifiers.


Comments

The number sign character ( # ) introduces a line comment. Comments that start with a number sign extend through the end of the line on which they appear. You can also use C and C++ language notation ( /*...*/ or // ) to delimit comments.

Note Do not start a comment with a number sign in column one. Comments beginning with the number sign character ( # ) are not allowed in header files.


Identifiers

An identifier consists of a case-sensitive sequence of alphanumeric characters (A-Z, a-z, 0-9), and the following special characters:

. (period)

_ (underscore)

$ (dollar sign)

@ (at sign)

? (question mark)

Identifiers can be up to 31 characters long, and the first character cannot be numeric (0-9).

If an identifier is not defined to the assembler (only referenced), the assembler assumes that the identifier is an external symbol. The assembler then treats the identifier like a name specified by an .extern directive.

If the identifier is defined to the assembler and the identifier has not been specified as global, the assembler assumes that the identifier is a local symbol.


Backslash Conventions

The C backslash conventions and their meanings are as follows:

Convention | Meaning
\a | Alert (0x07)
\b | Backspace (0x08)
\f | Form feed (0x0c)
\n | Newline (0x0a)
\r | Carriage return (0x0d)
\t | Horizontal tab (0x09)
\v | Vertical feed (0x0b)
\\ | Backslash (0x5c)
\" | Quotation mark (0x22)
\' | Single quote (0x27)
\nnn | Character whose octal value is nnn (where n is 0-7)
\X nn | Character whose hexadecimal value is nn (where n is 0-9, a-f, or A-F)


Scalar Constants

The assembler interprets all scalar constants as twos complement numbers. Scalar constants can be any of the digits 0123456789abcdefABCDEF.

Scalar constants can be one of the following constants:

  • Decimal constants. These consist of a sequence of decimal digits (0-9) without a leading zero.

  • Hexadecimal constants. These consist of the characters 0x (or 0X) followed by a sequence of hexadecimal digits.

  • Octal constants. These consist of a leading zero followed by a sequence of octal digits (0-7).


Floating-Point Constants

Floating-point constants can appear only in floating-point directives and in the floating-point load immediate instructions. Floating-point constants have the following format:

[[+|-]] d1 [[d2]] {e|E} [[+|-]] d3

Constant | Description
d1 | Required. Written as a decimal integer and denotes the integral part of the floating-point value.
d2 | Optional. Written as a decimal integer and denotes the fractional part of the floating-point value.
d3 | Required. Written as a decimal integer and denotes a power of 10.

Note The plus (+) and minus (-) symbols are optional. For example, the number .02173 can be represented as 21.73E-3

The floating-point directives (such as .float and .double) may optionally use hexadecimal floating-point constants instead of decimal constants. A hexadecimal floating-point constant consists of the following elements:

[[+|-]] 0x [[1|0]] hex-digits h0x hex-digits

The assembler places the first set of hexadecimal digits (excluding the 0 or 1 preceding the decimal point) in the mantissa field of the floating-point format without attempting to normalize it. It stores the second set of hexadecimal digits in the exponent field without biasing them. If the mantissa appears to be denormalized, it checks to determine whether the exponent is appropriate. Hexadecimal floating-point constants are useful for generating IEEE special symbols and for writing hardware diagnostics.

For example, both of the following directives generate the single-precision number 1.0:

.float 1.0e+0
.float 0x1.0h0x7f

The assembler uses normal (nearest) rounding mode to convert floating-point constants.


String Constants

All characters except the newline character (\n) are allowed in string constants. String constants begin and end with double quotation marks (").

The assembler observes most of the backslash conventions used by the C language. See Backslash Conventions for a list of the conventions and their meanings.

Deviations from C conventions are as follows:

  • The assembler does not recognize the question mark (?).

  • The assembler does not recognize the prefix "L" (wide character constant).

  • The assembler limits hexadecimal character constants to two characters.

  • The assembler allows the leading "x" character in hexadecimal constants to be either uppercase or lowercase; that is, both \xnn and \Xnn are allowed.

For octal notation, the backslash conventions require three characters when the next character could be confused with the octal number.

For hexadecimal notation, the backslash conventions require two characters when the next character could be confused with the hexadecimal number (that is, use a 0 for the first character of a single-character hexadecimal number).


Multiple Lines per Physical Line

You can include multiple statements on the same line by separating the statements with semicolons (;).

The assembler does not recognize semicolons as separators when they follow comment symbols #, //, or /*.


Statements

Each statement consists of an optional label, an operation code, and one or more operands.


Label Definitions

A label definition consists of an identifier followed by a colon (:). Label definitions assign the current value and type of the location counter to the name. An error results when the name is already defined.

Label definitions always end with a colon. You can put a label definition on a line by itself.

A generated label is a single numeric value (1-255). To reference a generated label, put an f (forward) or a b (backward) immediately after the digit. The reference tells the assembler to look for the nearest generated label that corresponds to the specified number in the lexically forward or backward direction.


Null Statements

A null statement is an empty statement that the assembler ignores. Null statements can have label definitions. For example, the following line has three null statements in it:

label: ; ;


Keyword Statements

A keyword statement begins with a predefined keyword. The syntax for the rest of the statement depends on the keyword. Keywords are either assembler instructions (mnemonics) or directives.


Expressions

An expression is a sequence of symbols that represents a value. Each expression and its result have data types. The assembler does arithmetic in twos complement integers with 64 bits of precision. Expressions follow precedence rules and consist of the following elements:

  • Operators

  • Identifiers

  • 06Constants

You can also use a single character string in place of an integer within an expression. For example, the following two pairs of statements are equivalent:

.byte "a" ; .word "a"+0x19
.byte 0x61 ; .word 0x7a


Expression Operators

The assembler supports the following expression operators:

Operator | Meaning
+ | Addition
- | Subtraction
* | Multiplication
/ | Division
% | Remainder
<< | Shift left
>> | Shift right (sign is not extended)
^ | Bitwise EXCLUSIVE OR
& | Bitwise AND
I | Bitwise OR
- | Minus (unary)
+ | Identity (unary)
~ | Complement


Expression Operator Precedence Rules

The assembler supports the following expression operator precedence rules:

Precedence | Operators
Least binding, lowest precedence | Binary +, -
. | Binary *, /, %, <<, >>, ^, &, |
Most binding, highest precedence | Unary -, +, ~

Note The assembler's precedence scheme differs from that of the C language.


Address Formats

An expression is a sequence of symbols that represents a value. Each expression and its result have data types. The assembler does arithmetic in twos complement integers with 64 bits of precision. Expressions follow precedence rules and consist of the following elements:


base-register

Specifies an indexed address, which assumes a zero offset. The base register's contents specify the address.


expression

Specifies an absolute address.


expression (base-register)

Specifies a based address. To get the address, the value of the expression is added to the contents of the base register. The assembler generates the most locally efficient code for referencing the value at the specified address.


Relocation Operands

Relocation operands are generally useful in three situations:

  • As support for independent expression of the high and low addresses

  • In application programs in which the programmer needs precise control over scheduling

  • In source code written for compiler development

Some macro instructions (for example, lda) require special coordination between the machine-code instructions and the relocation sequences given to the linker. By using the macro instructions, the assembler programmer relies on the assembler to generate the appropriate relocation sequences.

In some instances, the use of macro instructions may be undesirable. For example, a compiler that supports the generation of assembly language files may not want to defer instruction scheduling to the assembler. Such a compiler will want to schedule some or all of the machine-code instructions. To do this, the compiler must have a mechanism for emitting an object file's relocation sequences without using macro instructions. The mechanism for establishing these sequences is the relocation operand. A relocation operand is placed after the normal operand on an assembly language statement, as illustrated below:

opcode operand relocation_operand

The syntax of the relocation_operand is as follows:

![[relocation_type!]] sequence_number

Relocation type

The following table lists relocation_type values:

Relocation type | Windows NT description
braddr | Branch address.
hint | Jump hint.
poffset | Procedure offset.
refhi | High reference. Associated with an ldah instruction, this is normally accompanied by a pair relocation.
Sechi | Similar to refhi. This is for use by TLS.
Reflo | This is associated with a load, store, or lda instruction. The associated instruction may be the target of a pair relocation.
Seclo | Similar to reflo. This is for use by TLS.
Reflong | Longword relative reference. This is used when the address of a symbol is stored by a .long directive.
Refquad | Quadword relative reference. This is used when the address of a symbol is stored by a .quad directive.
Snum | Section number.
soffset | Section offset.

The relocation types must be enclosed within a pair of exclamation points (!) and are not case sensitive. Only refhi, sechi, reflo, and seclo are useful in the Alpha assembler.

Sequence number

The sequence_number value is a positive integer constant with a value range of 1 to 2147483647. The sequence number may be specified in decimal, hex, or octal notations.

The following examples contain relocation operands in the source code:

 # Equivalent C statement:
 # extern __int64 sym1, sym2;
 # sym1 += sym2;

Assembly statements containing macro instructions:

 ldq $1, sym1
 ldq $2, sym2
 addq $1, $2, $3
 stq $3, sym1

Assembly statements containing machine-code instructions requiring relocation operands:

In the Alpha assembler, an ldah instruction using a symbol without a relocation operand will produce a syntax error. By using the relocation operands, an ldah instruction is eliminated.

 ldah $4, sym1!refhi!1      # Load high value for sym1.
 ldah $5, sym2!refhi!2      # Load high value for sym2.
 ldq $1, sym1($4)!reflo!1   # Load sym1. Paired to ldah.
 ldq $2, sym2($5)!reflo!2   # Load sym2. Paired to ldah.
 addq $1, $2, $3
 stq $3, sym1($4)!reflo!1   # Store value in sym1 unpaired.


relocatable-symbol

Specifies a relocatable address. The assembler generates the necessary instructions to address the item and generates relocation information for the linker.


relocatable-symbol+/-expression

Specifies a relocatable address. To get the address, the value of the expression, which has an absolute value, is added to or subtracted from the relocatable symbol. The assembler generates the necessary instructions to address the item and generates relocation information for the linker. If the symbol name does not appear as a label anywhere in the assembly, the assembler assumes that the symbol is external.


relocatable-symbol (index-register)

Specifies an indexed relocatable address. To get the address, the index register is added to the relocatable symbol's address. The assembler generates the necessary instructions to address the item and generates relocation information for the linker. If the symbol name does not appear as a label anywhere in the assembly, the assembler assumes that the symbol is external.


relocatable-symbol+/-expression (index-register)

Specifies an indexed relocatable address. To get the address, the assembler adds or subtracts the relocatable symbol, the expression, and the contents of the index register. The assembler generates the necessary instructions to address the item and generates relocation information for the linker. If the symbol name does not appear as a label anywhere in the assembly, the assembler assumes that the symbol is external.


relocatable symbol (+/-/* constant)

The subtraction of two identifiers is now permitted as part of a constant expression. An optional expression can follow the symbolic difference. The expression is limited to addition, subtraction, multiplication, and division binary operators. The normal expression evaluation rules have been altered a bit such that the symbolic difference is assumed to be contained within parentheses. The expression following the binary operator can be any legal constant expression.

foo:
 .quad bar - foo * 2 # The result here is 16.
 bar:


Main Instruction Set

The main instruction set consists of the following categories of instructions:

  • Load

  • Store

  • Arithmetic

  • Logical and Shift

  • Relational

  • Move

  • Control

  • Byte manipulation

  • Extract

  • Insert

  • Mask

  • Zero-byte

  • Special purpose


Main Instruction Operand Descriptions

A main instruction accepts one or more of the following operands:

Operand | Description
address | A symbolic expression whose effective value is used as an address.
$d_reg | Destination register. An integer register that receives a value as a result in an operation.
$d_reg/$s_reg | One integer register that is used as both a destination register and a source register.
label | A label that identifies a location in a program.
offset | An immediate value that is added to the contents of a base register to calculate an effective address.
palcode | A value that determines the operation performed by a PAL instruction.
$s_reg, $s_reg1, $s_reg2 | Registers whose contents are to be used in an operation.
val_expr | An expression whose value is used as an absolute value.
val_immed | An immediate value that is to be used in an operation.
jhin | An address operand that provides a hint of where a jmp or jsr instruction will transfer control.
rhin | An immediate operand that provides software with a hint about how a ret or jsr coroutine instruction is used.


Load Instructions

These general-purpose load instructions are used to load immediate values.

Load instructions can generate many code sequences for which the linker must fix the address by resolving external data items.


Load Address (lda)

Syntax

lda $d_reg, address

Description

Load Address loads the destination register with the effective address of the specified data item.


Load Address High (ldah)

Syntax

ldah $d_reg, offset (b_reg)

Description

Load Address High loads the destination register with the effective address of the specified data item. In computing the effective address, the signed constant offset is multiplied by 65536 before adding to the base register. The signed offset must be in the range –32768 to 32767.


Load Byte (ldb)

Syntax

ldb $d_reg, address

Description

Load Byte loads the least significant byte of the destination register with the contents of the byte specified by the effective address. Because the loaded byte is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

Note The assembler destroys the contents of temporary registers $at and $t9 for this instruction.


Load Byte Unsigned (ldbu)

Syntax

ldbu $d_reg, address

Description

Load Byte Unsigned loads the least significant byte of the destination register with the contents of the byte specified by the effective address. Because the loaded byte is an unsigned value, the other bytes of the destination register are cleared to zeros.

Note The assembler destroys the contents of temporary registers $at and $t9 for this instruction unless the .arch directive or the /arch command-line option causes the assembler to generate a single machine instruction in response to the ldbu command.


Load Word (ldw)

Syntax

ldw $d_reg, address

Description

Load Word loads the two least significant bytes of the destination register with the contents of the word specified by the effective address. Because the loaded word is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

If the effective address is not evenly divisible by 2, a data alignment exception may be signaled.

Note The assembler destroys the contents of temporary registers $at and $t9 for this instruction.


Load Word Unsigned (ldwu)

Syntax

ldwu $d_reg, address

Description

Load Word Unsigned loads the two least significant bytes of the destination register with the contents of the word specified by the effective address. Because the loaded word is an unsigned value, the other bytes of the destination register are cleared to zeros.

If the effective address is not evenly divisible by 2, a data alignment exception may be signaled.

Note The assembler destroys the contents of temporary registers $at and $t9 for this instruction unless the .arch directive or the /arch command-line option causes the assembler to generate a single machine instruction in response to the ldwu command.


Load Sign Extended Longword (ldl)

Syntax

ldl $d_reg, address

Description

Load Sign Extended Longword loads the four least significant bytes of the destination register with the contents of the longword specified by the effective address. Because the loaded longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.


Load Sign Extended Longword Locked (ldl_l)

Syntax

ldl_l $d_reg, address

Description

Load Sign Extended Longword Locked loads the four least significant bytes of the destination register with the contents of the longword specified by the effective address. Because the loaded longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.

If an ldl_l instruction executes without faulting, the processor records the target physical address in a per-processor locked-physical-address register and sets the per-processor lock flag.

If the per-processor lock flag is still set when a Store Longword Conditional (stl_c) instruction is executed, the store occurs; otherwise, it does not occur.

See Also

Atomic Updates


Load Quadword (ldq)

Syntax

ldq $d_reg, address

Description

Load Quadword loads the destination register with the contents of the quadword specified by the effective address. All bytes of the register are replaced with the contents of the loaded quadword.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.


Load Quadword Locked (ldq_l)

Syntax

ldq_l $d_reg, address

Description

Load Quadword Locked loads the destination register with the contents of the quadword specified by the effective address. All bytes of the register are replaced with the contents of the loaded quadword.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.

If an ldq_l instruction executes without faulting, the processor records the target physical address in a per-processor locked-physical-address register and sets the per-processor lock flag. If the per-processor lock flag is still set when a Store Quadword Conditional (stq_c) instruction is executed, the store occurs; otherwise, it does not occur.

See Also

Atomic Updates


Load Quadword Unaligned (ldq_u)

Syntax

ldq_u $d_reg, address

Description

Load Quadword Unaligned loads the destination register with the contents of the quadword specified by the effective address with the three low-order bits cleared. The address does not have to be aligned on an 8-byte boundary, it can be any byte address.


Unaligned Load Word (uldw)

Syntax

uldw $d_reg, address

Description

Unaligned Load Word loads the two least significant bytes of the destination register with the word at the specified address. The address does not have to be aligned on a 2-byte boundary, it can be any byte address. Because the loaded word is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

Note The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Unaligned Load Word Unsigned (uldwu)

Syntax

uldwu $d_reg, address

Description

Unaligned Load Word Unsigned loads the two least significant bytes of the destination register with the word at the specified address. The address does not have to be aligned on a 2-byte boundary, it can be any byte address. Because the loaded word is an unsigned value, the other bytes of the destination register are cleared to zeros.

Note The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Unaligned Load Longword (uldl)

Syntax

uldl $d_reg, address

Description

Unaligned Load Longword loads the four least significant bytes of the destination register with the contents of the longword specified by the effective address. The address does not have to be aligned on a 4-byte boundary; it can be any address. Because the loaded longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

Note The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Unaligned Load Quadword (uldq)

Syntax

uldq $d_reg, address

Description

Unaligned Load Quadword loads the destination register with the quadword at the specified address. The address does not have to be aligned on an 8-byte boundary; it can be any byte address in memory.

Note The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Load Immediate Longword

Load Immediate Longword (ldil)

Syntax

ldil $d_reg, val_expr

Description

Load Immediate Longword loads the destination register with the value of an expression that can be computed at assembly time. The value is converted to canonical longword form before being stored in the destination register; bit 31 is replicated in bits 32 though 63 of the destination register.


Load Immediate Quadword (ldiq)

Syntax

ldiq $d_reg, val_expr

Description

Load Immediate Quadword loads the destination register with the value of an expression that can be computed at assembly time.


Store Instructions

This topic describes the general-purpose store instructions supported by the assembler. Store instructions move data between memory and general registers.


Store Byte (stb)

Syntax

stb $s_reg, address

Description

Store Byte stores the least significant byte of the source register in the memory location specified by the effective address.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, and $t11 for this instruction unless the .arch directive or the /arch command-line option causes the assembler to generate a single machine instruction in response to the stb command.


Store Word (stw)

Syntax

stw $s_reg, address

Description

Store Word stores the two least significant bytes of the source register in the memory location specified by the effective address.

If the effective address is not evenly divisible by 2, a data alignment exception may be signaled.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, and $t11 for this instruction unless the .arch directive or the /arch command-line option causes the assembler to generate a single machine instruction in response to the stw command.


Store Longword (stl)

Syntax

stl $s_reg, address

Description

Store Longword stores the four least significant bytes of the source register in the memory location specified by the effective address.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.


Store Longword Conditional (stl_c)

Syntax

stl_c $s_reg, address

Description

Store Longword Conditional stores the four least significant bytes of the source register in the memory location specified by the effective address, if the lock flag is set. The lock flag is returned in the source register and is then set to zero.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.

See Also

Load Sign Extended Longword Locked (ldl_l)

Atomic Updates


Store Quadword (stq)

Syntax

stq $s_reg, address

Description

Store Quadword stores the contents of the source register in the memory location specified by the effective address.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.


Store Quadword Conditional (stq_c)

Syntax

stq_c $s_reg, address

Description

Store Quadword Conditional stores the contents of the source register in the memory location specified by the effective address, if the lock flag is set. The lock flag is returned in the source register and is then set to zero.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.

See Also

Load Quadword Locked (ldq_l)

Atomic Updates


Store Quadword Unaligned (stq_u)

Syntax

stq_u $s_reg, address

Description

Store Quadword Unaligned stores the contents of the source register in the memory location specified by the effective address with the three low-order bits cleared.


Unaligned Store Word (ustw)

Syntax

ustw $s_reg, address

Description

Unaligned Store Word stores the two least significant bytes of the source register in the memory location specified by the effective address. The address does not have to be aligned on a 2-byte boundary, it can be any byte address.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Unaligned Store Longword (ustl)

Syntax

ustl $s_reg, address

Description

Unaligned Store Longword stores the four least significant bytes of the source register in the memory location specified by the effective address. The address does not have to be aligned on a 4-byte boundary, it can be any byte address.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Unaligned Store Quadword (ustq)

Syntax

ustq $s_reg, address

Description

Unaligned Store Quadword stores the contents of the source register in a memory location specified by the effective address. The address does not have to be aligned on an 8-byte boundary, it can be any byte address.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Arithmetic Instructions

Arithmetic Instructions perform arithmetic operations on values in registers. (Floating-point arithmetic instructions are described elsewhere)


Clear Instruction (clr)

Syntax

clr $d_reg

Description

Clear sets the contents of the destination register to zero.


Sign Extension Instruction (sextl)

Syntax

sextl $s_reg, $d_reg

sextl $d_reg/$s_reg

sextl val_immed, $d_reg

Description

Sign-Extension Longword moves the four least significant bytes of the source register into the four least significant bytes of the destination register. Because the moved longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.


Absolute Value Longword (absl)

Syntax

absl $s_reg, $d_reg

absl $d_reg/$s_reg

absl val_immed, $d_reg

Description

Absolute Value Longword computes the absolute value of the contents of the source register and puts the result in the destination register. If the value in the source register is –2147483648, an overflow exception is signaled.


Absolute Value Quadword (absq)

Syntax

absq $s_reg, $d_reg

absq $d_reg/$s_reg

absq val_immed, $d_reg

Description

Absolute Value Quadword computes the absolute value of the contents of the source register and puts the result in the destination register. If the value in the source register is –9223372036854775808, an overflow exception is signaled.


Negate Longword without Overflow (negl)

Syntax

negl $s_reg, $d_reg

negl $d_reg/$s_reg

negl val_immed, $d_reg

Description

Negate Longword (without overflow) negates the integer contents of the four least significant bytes in the source register and puts the result in the destination register. An overflow occurs if the value in the source register is –2147483648, but the overflow exception is not signaled.


Negate Longword with Overflow (neglv)

Syntax

neglv $s_reg, $d_reg

neglv $d_reg/$s_reg

neglv val_immed, $d_reg

Description

Negate Longword (with overflow) negates the integer contents of the four least significant bytes in the source register and puts the result in the destination register. If the value in the source register is –2147483648, an integer overflow exception is signaled.


Negate Quadword without Overflow (negq)

Syntax

negq $s_reg, $d_reg

negq $d_reg/$s_reg

negq val_immed, $d_reg

Description

Negate Quadword (without overflow) negates the integer contents of the source register and puts the result in the destination register. An overflow occurs if the value in the source register is –9223372036854775808, but the overflow exception is not signaled.


Negate Quadword with Overflow (negqv)

Syntax

negqv $s_reg, $d_reg

negqv $d_reg/$s_reg

negqv val_immed, $d_reg

Description

Negate Quadword (with overflow) negates the integer contents of the source register and puts the result in the destination register. If the value in the source register is –9223372036854775808, an integer overflow exception is signaled.


Add Longword without Overflow (addl)

Syntax

addl $s_reg1, $s_reg2, $d_reg

addl $d_reg/$s_reg1, $s_reg2

addl $s_reg1, val_immed, $d_reg

addl $d_reg/$s_reg1, val_immed

Description

Add Longword (without overflow) computes the sum of two signed 32-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. Overflow exceptions never occur.


Add Longword with Overflow (addlv)

Syntax

addlv $s_reg1, $s_reg2, $d_reg

addlv $d_reg/$s_reg1, $s_reg2

addlv $s_reg1, val_immed, $d_reg

addlv $d_reg/$s_reg1, val_immed

Description

Add Longword (with overflow) computes the sum of two signed 32-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. If the result cannot be represented as a signed 32-bit number, an integer overflow exception is signaled.


Add Quadword without Overflow (addq)

Syntax

addq $s_reg1, $s_reg2, $d_reg

addq $d_reg/$s_reg1, $s_reg2

addq $s_reg1, val_immed, $d_reg

addq $d_reg/$s_reg1, val_immed

Description

Add Quadword (without overflow) computes the sum of two signed 64-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. Overflow exceptions never occur.


Add Quadword with Overflow (addqv)

Syntax

addqv $s_reg1, $s_reg2, $d_reg

addqv $d_reg/$s_reg1, $s_reg2

addqv $s_reg1, val_immed, $d_reg

addqv $d_reg/$s_reg1, val_immed

Description

Add Quadword (with overflow) computes the sum of two signed 64-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. If the result cannot be represented as a signed 64-bit number, an integer overflow exception is signaled.


Scaled Longword Add by 4 (s4addl)

Syntax

s4addl $s_reg1, $s_reg2, $d_reg

s4addl $d_reg/$s_reg1, $s_reg2

s4addl $s_reg1, val_immed, $d_reg

s4addl $d_reg/$s_reg1, val_immed

Description

Scaled Longword Add by 4 computes the sum of two signed 32-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 4 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Add by 4 (s4addq)

Syntax

s4addq $s_reg1, $s_reg2, $d_reg

s4addq $d_reg/$s_reg1, $s_reg2

s4addq $s_reg1, val_immed, $d_reg

s4addq $d_reg/$s_reg1, val_immed

Description

Scaled Quadword Add by 4 computes the sum of two signed 64-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 4 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Longword Add by 8 (s8addl)

Syntax

s8addl $s_reg1, $s_reg2, $d_reg

s8addl $d_reg/$s_reg1, $s_reg2

s8addl $s_reg1, val_immed, $d_reg

s8addl $d_reg/$s_reg1, val_immed

Description

Scaled Longword Add by 8 computes the sum of two signed 32-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 8 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Add by 8 (s8addq)

Syntax

s8addq $s_reg1, $s_reg2, $d_reg

s8addq $d_reg/$s_reg1, $s_reg2

s8addq $s_reg1, val_immed, $d_reg

s8addq $d_reg/$s_reg1, val_immed

Description

Scaled Quadword Add by 8 computes the sum of two signed 64-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 8 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Multiply Longword without Overflow (mull)

Syntax

mull $s_reg1, $s_reg2, $d_reg

mull $d_reg/$s_reg1, $s_reg2

mull $s_reg1, val_immed, $d_reg

mull $d_reg/$s_reg1, val_immed

Description

Multiply Longword (without overflow) computes the product of two signed 32-bit values. This instruction puts the 32-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. Overflows are not reported.


Multiply Longword with Overflow (mullv)

Syntax

mullv $s_reg1, $s_reg2, $d_reg

mullv $d_reg/$s_reg1, $s_reg2

mullv $s_reg1, val_immed, $d_reg

mullv $d_reg/$s_reg1, val_immed

Description

Multiply Longword (with overflow) computes the product of two signed 32-bit values. This instruction puts the 32-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. If an overflow occurs, an integer overflow exception is signaled.


Multiply Quadword without Overflow (mulq)

Syntax

mulq $s_reg1, $s_reg2, $d_reg

mulq $d_reg/$s_reg1, $s_reg2

mulq $s_reg1, val_immed, $d_reg

mulq $d_reg/$s_reg1, val_immed

Description

Multiply Quadword (without overflow) computes the product of two signed 64-bit values. This instruction puts the 64-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. Overflow is not reported.


Multiply Quadword with Overflow (mulqv)

Syntax

mulqv $s_reg1, $s_reg2, $d_reg

mulqv $d_reg/$s_reg1, $s_reg2,

mulqv $s_reg1, val_immed, $d_reg

mulqv $d_reg/$s_reg1, val_immed

Description

Multiply Quadword (with overflow) computes the product of two signed 64-bit values. This instruction puts the 64-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. If an overflow occurs, an integer overflow exception is signaled.


Unsigned Quadword Multiply High Instruction

Unsigned Quadword Multiply High Instruction (umulh)

Syntax

umulh $s_reg1, $s_reg2, $d_reg

umulh $d_reg/$s_reg1, $s_reg2

umulh $s_reg1, val_immed, $d_reg

umulh $d_reg/$s_reg1, val_immed

Description

Unsigned Quadword Multiply High computes the product of two unsigned 64-bit values. This instruction multiplies the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the high-order 64 bits of the 128-bit product in the destination register.


Subtract Longword without Overflow (subl)

Syntax

subl $s_reg1, $s_reg2, $d_reg

subl $d_reg/$s_reg1, $s_reg2

subl $s_reg1, val_immed, $d_reg

subl $d_reg/$s_reg1, val_immed

Description

Subtract Longword (without overflow) computes the difference of two signed 32-bit values. This instruction subtracts either the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. Overflow exceptions never happen.


Subtract Longword with Overflow (sublv)

Syntax

sublv $s_reg1, $s_reg2, $d_reg

sublv $d_reg/$s_reg1, $s_reg2

sublv $s_reg1, val_immed, $d_reg

sublv $d_reg/$s_reg1, val_immed

Description

Subtract Longword (with overflow) computes the difference of two signed 32-bit values. This instruction subtracts either the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. If the true result's sign differs from the destination register's sign, an integer overflow exception is signaled.


Subtract Quadword without Overflow (subq)

Syntax

subq $s_reg1, $s_reg2, $d_reg

subq $d_reg/$s_reg1, $s_reg2

subq $s_reg1, val_immed, $d_reg

subq $d_reg/$s_reg1, val_immed

Description

Subtract Quadword (without overflow) computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. Overflow exceptions never occur.


Subtract Quadword with Overflow (subqv)

Syntax

subqv $s_reg1, $s_reg2, $d_reg

subqv $d_reg/$s_reg1, $s_reg2

subqv $s_reg1, val_immed, $d_reg

subqv $d_reg/$s_reg1, val_immed

Description

Subtract Quadword (with overflow) computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. If the true result's sign differs from the destination register's sign, an integer overflow exception is signaled.


Scaled Longword Subtract by 4 (s4subl)

Syntax

s4subl $s_reg1, $s_reg2, $d_reg

s4subl $d_reg/$s_reg1, $s_reg2

s4subl $s_reg1, val_immed, $d_reg

s4subl $d_reg/$s_reg1, val_immed

Description

Scaled Longword Subtract by 4 computes the difference of two signed 32-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 4) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Subtract by 4 (s4subq)

Syntax

s4subq $s_reg1, $s_reg2, $d_reg

s4subq $d_reg/$s_reg1, $s_reg2

s4subq $s_reg1, val_immed, $d_reg

s4subq $d_reg/$s_reg1, val_immed

Description

Scaled Quadword Subtract by 4 computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 4) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Longword Subtract by 8 (s8subl)

Syntax

s8subl $s_reg1, $s_reg2, $d_reg

s8subl $d_reg/$s_reg1, $s_reg2

s8subl $s_reg1, val_immed, $d_reg

s8subl $d_reg/$s_reg1, val_immed

Description

Scaled Longword Subtract by 8 computes the difference of two signed 32-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 8) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Subtract by 8 (s8subq)

Syntax

s8subq $s_reg1, $s_reg2, $d_reg

s8subq $d_reg/$s_reg1, $s_reg2

s8subq$s_reg1, val_immed, $d_reg

s8subq $d_reg/$s_reg1, val_immed

Description

Scaled Quadword Subtract by 8 computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 8) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Divide Longword (divl)

Syntax

divl $s_reg1, $s_reg2, $d_reg

divl $d_reg/$s_reg1, $s_reg2

divl $s_reg1, val_immed, $d_reg

divl $d_reg/$s_reg1, val_immed

Description

Divide Longword computes the quotient of two signed 32-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

Overflow is signaled when dividing –2147483648 by -1. A call_pal PAL_gentrap instruction may be issued for either divide-by-zero or overflow.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Divide Longword Unsigned (divlu)

Syntax

divlu $s_reg1, $s_reg2, $d_reg

divlu $d_reg/$s_reg1, $s_reg2

divlu $s_reg1, val_immed, $d_reg

divlu $d_reg/$s_reg1, val_immed

Description

Divide Longword Unsigned computes the quotient of two unsigned 32-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

If the divisor is zero, an exception is signaled and a call_pal PAL_gentrap instruction may be issued. Overflow exceptions never occur.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Divide Quadword (divq)

Syntax

divq $s_reg1, $s_reg2, $d_reg

divq $d_reg/$s_reg1, $s_reg2

divq $s_reg1, val_immed, $d_reg

divq $d_reg/$s_reg1, val_immed

Description

Divide Quadword computes the quotient of two signed 64-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

Overflow is signaled when dividing –9223372036854775808 by -1. A call_pal PAL_gentrap instruction may be issued for either divide-by-zero or overflow.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Divide Quadword Unsigned (divqu)

Syntax

divqu $s_reg1, $s_reg2, $d_reg

divqu $d_reg/$s_reg1, $s_reg2

divqu $s_reg1, val_immed, $d_reg

divqu $d_reg/$s_reg1, val_immed

Description

Divide Quadword Unsigned computes the quotient of two unsigned 64-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

If the divisor is zero, an exception is signaled and a call_pal PAL_gentrap instruction may be issued. Overflow exceptions never occur.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Longword Remainder (reml)

Syntax

reml $s_reg1, $s_reg2, $d_reg

reml $d_reg/$s_reg1, $s_reg2

reml $s_reg1, val_immed, $d_reg

reml $d_reg/$s_reg1, val_immed

Description

Longword Remainder computes the remainder of the division of two signed 32-bit values. The remainder reml(i, j) is defined as i-(j*divl(i, j)) where j != 0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or by the immediate value and then puts the remainder in the destination register.

The reml instruction rounds toward zero. For example, divl(5,-3)=-1 , and reml(5,-3)=2 .

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Longword Remainder Unsigned (remlu)

Syntax

remlu $s_reg1, $s_reg2, $d_reg

remlu $d_reg/$s_reg1, $s_reg2

remlu $s_reg1, val_immed, $d_reg

remlu $d_reg/$s_reg1, val_immed

Description

Longword Remainder Unsigned computes the remainder of the division of two unsigned 32-bit values. The remainder remlu (i, j) is defined as i-(j*divlu (i, j)) where j !=0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the remainder in the destination register.

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Quadword Remainder (remq)

Syntax

remq $s_reg1, $s_reg2, $d_reg

remq $d_reg/$s_reg1, $s_reg2

remq $s_reg1, val_immed, $d_reg

remq $d_reg/$s_reg1, val_immed

Description

Quadword Remainder computes the remainder of the division of two signed 64-bit values. The remainder remq (i, j) is defined as i-(j*divq(i, j)) where j != 0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the remainder in the destination register.

The remq instruction rounds toward zero. For example, divq (5,-3)=-1, and remq (5,-3)=2.

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Quadword Remainder Unsigned (remqu)

Syntax

remqu $s_reg1, $s_reg2, $d_reg

remqu $d_reg/$s_reg1, $s_reg2

remqu $s_reg1, val_immed, $d_reg

remqu $d_reg/$s_reg1, val_immed

Description

Quadword Remainder Unsigned computes the remainder of the division of two unsigned 64-bit values. The remainder remqu (i, j) is defined as i -(j*divqu (i, j)) where j !=0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the remainder in the destination register.

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Logical and Shift Instructions

Logical and shift instructions perform logical shift operations and shifts on values in registers.


Logical Complement NOT (not)

Syntax

not $s_reg, $d_reg

not $d_reg/$s_reg

not val_immed, $d_reg

not $s_reg1, $s_reg2, $d_reg

not $d_reg/$s_reg1, $s_reg2

not $s_reg1, val_immed, $d_reg

not $d_reg/$s_reg1, val_immed

Description

Logical Complement (NOT) computes the Logical NOT of a value. This instruction complements (bit-wise) the contents of $s_reg1 and puts the result in the destination register.


Logical Product AND (and)

Syntax

and $s_reg, $d_reg

and $d_reg/$s_reg

and val_immed, $d_reg

and $s_reg1, $s_reg2, $d_reg

and $d_reg/$s_reg1, $s_reg2

and $s_reg1, val_immed, $d_reg

and $d_reg/$s_reg1, val_immed

Description

Logical Product (AND) computes the Logical AND of two values. This instruction ANDs (bit-wise) the contents of $s_reg1 with the contents of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Sum OR (bis)

Syntax

bis $s_reg, $d_reg

bis $d_reg/$s_reg

bis val_immed, $d_reg

bis $s_reg1, $s_reg2, $d_reg

bis $d_reg/$s_reg1, $s_reg2

bis $s_reg1, val_immed, $d_reg

bis $d_reg/$s_reg1, val_immed

Description

Logical Sum (OR) computes the Logical OR of two values. This instruction ORs (bit-wise) the contents of $s_reg1 with the contents of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Sum OR (or)

The instruction or is a synonym for bis.


Logical Difference XOR (xor)

Syntax

xor $s_reg, $d_reg

xor $d_reg/$s_reg

xor val_immed, $d_reg

xor $s_reg1, $s_reg2, $d_reg

xor $d_reg/$s_reg1, $s_reg2

xor $s_reg1, val_immed, $d_reg

xor $d_reg/$s_reg1, val_immed

Description

Logical Difference (XOR) computes the XOR of two values. This instruction XORs (bit-wise) the contents of $s_reg1 with the contents of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Product with Complement ANDNOT (bic)

Syntax

bic $s_reg, $d_reg

bic $d_reg/$s_reg

bic val_immed, $d_reg

bic $s_reg1, $s_reg2, $d_reg

bic $d_reg/$s_reg1, $s_reg2

bic $s_reg1, val_immed, $d_reg

bic $d_reg/$s_reg1, val_immed

Description

Logical Product with Complement (ANDNOT) computes the Logical AND of two values. This instruction ANDs (bit-wise) the contents of $s_reg1 with the ones complement of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Product with Complement ANDNOT (andnot)

The instruction andnot is a synonym for bic.


Logical Sum with Complement ORNOT (ornot)

Syntax

ornot $s_reg, $d_reg

ornot $d_reg/$s_reg

ornot val_immed, $d_reg

ornot $s_reg1, $s_reg2, $d_reg

ornot $d_reg/$s_reg1, $s_reg2

ornot $s_reg1, val_immed, $d_reg

ornot $d_reg/$s_reg1, val_immed

Description

Logical Sum with Complement (ORNOT) computes the logical OR of two values. This instruction ORs (bit-wise) the contents of $s_reg1 with the ones complement of $s_reg2 or an immediate value and then puts the result in the destination register.


Logical Equivalence XORNOT (eqv)

Syntax

eqv $s_reg, $d_reg

eqv $d_reg/$s_reg

eqv val_immed, $d_reg

eqv $s_reg1, $s_reg2, $d_reg

eqv $d_reg/$s_reg1, $s_reg2

eqv $s_reg1, val_immed, $d_reg

eqv $d_reg/$s_reg1, val_immed

Description

Logical Equivalence (XORNOT) computes the logical XOR of two values. This instruction XORs (bit-wise) the contents of $s_reg1 with the ones complement of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Equivalence XORNOT (xornot)

The instruction xornot is a synonym for eqv.


Shift Left Logical (sll)

Syntax

sll $s_reg, $d_reg

sll $d_reg/$s_reg

sll val_immed, $d_reg

sll $s_reg1, $s_reg2, $d_reg

sll $d_reg/$s_reg1, $s_reg2

sll $s_reg1, val_immed, $d_reg

sll $d_reg/$s_reg1, val_immed

Description

Shift Left Logical shifts the contents of a register left (toward the sign bit) and inserts zeros in the vacated bit positions. The contents of $s_reg1 specifies the value to shift, and the contents of $s_reg2 or the immediate value specifies the number of bits to shift. If $s_reg2 or the immediate value is greater than 63 or less than zero, $s_reg1 shifts by the result of the following AND operation: $s_reg2 AND 63.


Shift Right Logical (srl)

Syntax

srl $s_reg, $d_reg

srl $d_reg/$s_reg

srl val_immed, $d_reg

srl $s_reg1, $s_reg2, $d_reg

srl $d_reg/$s_reg1, $s_reg2

srl $s_reg1, val_immed, $d_reg

srl $d_reg/$s_reg1, val_immed

Description

Shift Right Logical shifts the contents of a register right (toward the least significant bit) and inserts zeros in the vacated bit positions. The contents of $s_reg1 specifies the value to shift, and the contents of $s_reg2 or the immediate value specifies the number of bits to shift. If $s_reg2 or the immediate value is greater than 63 or less than zero, $s_reg1 shifts by the result of the following AND operation: $s_reg2 AND 63.


Shift Right Arithmetic (sra)

Syntax

sra $s_reg, $d_reg

sra $d_reg/$s_reg

sra val_immed, $d_reg

sra $s_reg1, $s_reg2, $d_reg

sra $d_reg/$s_reg1, $s_reg2

sra $s_reg1, val_immed, $d_reg

sra $d_reg/$s_reg1, val_immed

Description

Shift Right Arithmetic shifts the contents of a register right (toward the least significant bit) and inserts the sign bit in the vacated bit position. The contents of $s_reg1 specifies the value to shift, and the contents of $s_reg2 or the immediate value specifies the number of bits to shift. If $s_reg2 or the immediate value is greater than 63 or less than zero, $s_reg1 shifts by the result of the following AND operation: $s_reg2 AND 63.


Relational Instructions

Relational Instructions compare values in registers.


Compare Signed Quadword Equal (cmpeq)

Syntax

cmpeq $s_reg1, $s_reg2, $d_reg

cmpeq $d_reg/$s_reg1, $s_reg2

cmpeq $s_reg1, val_immed, $d_reg

cmpeq $d_reg/$s_reg1, val_immed

Description

Compare Signed Quadword Equal compares two 64-bit values. If the contents of $s_reg1 equals the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1; otherwise, it sets the destination register to zero.


Compare Signed Quadword Less Than (cmplt)

Syntax

cmplt $s_reg1, $s_reg2, $d_reg

cmplt $d_reg/$s_reg1, $s_reg2

cmplt $s_reg1, val_immed, $d_reg

cmplt $d_reg/$s_reg1, val_immed

Description

Compare Signed Quadword Less Than compares two signed 64-bit values. If the contents of $s_reg1 is less than the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1; otherwise, it sets the destination register to zero.


Compare Signed Quadword Less Than or Equal (cmple)

Syntax

cmple $s_reg1, $s_reg2, $d_reg

cmple $d_reg/$s_reg1, $s_reg2

cmple $s_reg1, val_immed, $d_reg

cmple $d_reg/$s_reg1, val_immed

Description

Compare Signed Quadword Less Than or Equal compares two signed 64-bit values. If the contents of $s_reg1 is less than or equal to the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1. Otherwise, the destination register is set to zero.


Compare Unsigned Quadword Less Than (cmpult)

Syntax

cmpult $s_reg1, $s_reg2, $d_reg

cmpult $d_reg/$s_reg1, $s_reg2

cmpult $s_reg1, val_immed, $d_reg

cmpult $d_reg/$s_reg1, val_immed

Description

Compare Unsigned Quadword Less Than compares two unsigned 64-bit values. If the contents of $s_reg1 is less than the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1. Otherwise, the destination register is set to zero.


Compare Unsigned Quadword Less Than or Equal (cmpule)

Syntax

cmpule $s_reg1, $s_reg2, $d_reg

cmpule $d_reg/$s_reg1, $s_reg2

cmpule $s_reg1, val_immed, $d_reg

cmpule $d_reg/$s_reg1, val_immed

Description

Compare Unsigned Quadword Less Than or Equal compares two unsigned 64-bit values. If the contents of $s_reg1 is less than or equal to the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1. Otherwise, the destination register is set to zero.


Move Instructions

Move instructions move data between registers.


Move (mov)

Syntax

mov $s_reg, $d_reg

mov val_immed, d_reg2

Description

Move moves the contents of the source register or the immediate value to the destination register.


Move if Equal to Zero (cmoveq)

Syntax

cmoveq $s_reg1, $s_reg2, $d_reg

cmoveq $d_reg/$s_reg1, $s_reg2

cmoveq $s_reg1, val_immed, $d_reg

cmoveq $d_reg/$s_reg1, val_immed

Description

Move if Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is equal to zero.


Move if Not Equal to Zero (cmovne)

Syntax

cmovne $s_reg1, $s_reg2, $d_reg

cmovne $d_reg/$s_reg1, $s_reg2

cmovne $s_reg1, val_immed, $d_reg

cmovne $d_reg/$s_reg1, val_immed

Description

Move if Not Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is not equal to zero.


Move if Less Than Zero (cmovlt)

Syntax

cmovlt $s_reg1, $s_reg2, $d_reg

cmovlt $d_reg/$s_reg1, $s_reg2

cmovlt $s_reg1, val_immed, $d_reg

cmovlt $d_reg/$s_reg1, val_immed

Description

Move if Less Than Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is less than zero.


Move if Less Than or Equal to Zero (cmovle)

Syntax

cmovle $s_reg1, $s_reg2, $d_reg

cmovle $d_reg/$s_reg1, $s_reg2

cmovle $s_reg1, val_immed, $d_reg

cmovle $d_reg/$s_reg1, val_immed

Description

Move if Less Than or Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is less than or equal to zero.


Move if Greater Than Zero (cmovgt)

Syntax

cmovgt $s_reg1, $s_reg2, $d_reg

cmovgt $d_reg/$s_reg1, $s_reg2

cmovgt $s_reg1, val_immed, $d_reg

cmovgt $d_reg/$s_reg1, val_immed

Description

Move if Greater Than Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is greater than zero.


Move if Greater Than or Equal to Zero (cmovge)

Syntax

cmovge $s_reg1, $s_reg2, $d_reg

cmovge $d_reg/$s_reg1, $s_reg2

cmovge $s_reg1, val_immed, $d_reg

cmovge $d_reg/$s_reg1, val_immed

Description

Move if Greater Than or Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is greater than or equal to zero.


Move if Low Bit Clear (cmovlbc)

Syntax

cmovlbc $s_reg1, $s_reg2, $d_reg

cmovlbc $d_reg/$s_reg1, $s_reg2

cmovlbc $s_reg1, val_immed, $d_reg

cmovlbc $d_reg/$s_reg1, val_immed

Description

Move if Low Bit Clear moves the contents of $s_reg2 or the immediate value to the destination register if the low-order bit of $s_reg1 is equal to zero.


Move if Low Bit Set (cmovlbs)

Syntax

cmovlbs $s_reg1, $s_reg2, $d_reg

cmovlbs $d_reg/$s_reg1, $s_reg2

cmovlbs $s_reg1, val_immed, $d_reg

cmovlbs $d_reg/$s_reg1, val_immed

Description

Move if Low Bit Set moves the contents of $s_reg2 or the immediate value to the destination register if the low-order bit of $s_reg1 is not equal to zero.


Control Instructions

Control instructions change the control flow of an assembly language program. They affect the sequence in which instructions are executed by transferring control from one location to another.


Branch if Equal to Zero (beq)

Syntax

beq $s_reg, label

Description

Branch if Equal to Zero branches to the specified label if the contents of the source register is equal to zero.


Branch if Not Equal to Zero (bne)

Syntax

bne $s_reg, label

Description

Branch if Not Equal to Zero branches to the specified label if the contents of the source register is not equal to zero.


Branch if Less Than Zero (blt)

Syntax

blt $s_reg, label

Description

Branch if Less Than Zero branches to the specified label if the contents of the source register is less than zero. The comparison treats the source register as a signed 64-bit value.


Branch if Less Than or Equal to Zero (ble)

Syntax

ble $s_reg, label

Description

Branch if Less Than or Equal to Zero branches to the specified label if the contents of the source register is less than or equal to zero. The comparison treats the source register as a signed 64-bit value.


Branch if Greater Than Zero (bgt)

Syntax

bgt $s_reg, label

Description

Branch if Greater Than Zero branches to the specified label if the contents of the source register is greater than zero. The comparison treats the source register as a signed 64-bit value.


Branch if Greater Than or Equal to Zero (bge)

Syntax

bge $s_reg, label

Description

Branch if Greater Than or Equal to Zero branches to the specified label if the contents of the source register is greater than or equal to zero. The comparison treats the source register as a signed 64-bit value.


Branch if Low Bit is Clear (blbc)

Syntax

blbc $s_reg, label

Description

Branch if Low Bit is Clear branches to the specified label if the low-order bit of the source register is equal to zero.


Branch if Low Bit is Set (blbs)

Syntax

blbs $s_reg, label

Description

Branch if Low Bit is Set branches to the specified label if the low-order bit of the source register is not equal to zero.


Branch (br)

Syntax

br $s_reg, label

Description

Branch branches unconditionally to the specified label. If a destination register is specified, the address of the instruction following the br instruction is stored in that register.


Branch to Subroutine (bsr)

Syntax

bsr $d_reg, label

bsr label

Description

Branch to Subroutine branches unconditionally to the specified label and stores the return address in the destination register. If a destination register is not specified, register $ra ($26) is used.


Jump (jmp)

Syntax

jmp $d_reg, ($s_reg), jhint

jmp $d_reg, ($s_reg)

jmp ($s_reg), jhint

jmp ($s_reg)

jmp ($s_reg), jhint

jmp $d_reg, address

jmp address

Description

Jump unconditionally jumps to a specified location. A symbolic address or the source register specifies the target location. If a destination register is specified, the address of the instruction following the jmp instruction is stored in the specified register.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.

See Also

For information about branch prediction logic, see the Alpha Architecture Reference Manual.


Jump to Subroutine (jsr)

Syntax

jsr $d_reg, ($s_reg), jhint

jsr $d_reg, ($s_reg)

jsr ($s_reg), jhint

jsr ($s_reg)

jsr ($s_reg), jhint

jsr $d_reg, address

jsr address

Description

Jump to Subroutine unconditionally jumps to a specified location and stores the return address in the destination register. If a destination register is not specified, register $ra ($26) is used. A symbolic address or the source register specifies the target location. The instruction jsr procname transfers to procname and saves the return address in register $26.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.

See Also

For information about branch prediction logic, see the Alpha Architecture Reference Manual.


Return from Subroutine (ret)

Syntax

ret $d_reg, ($s_reg), rhint

ret $d_reg, ($s_reg)

ret $d_reg, rhint

ret $d_reg

ret ($s_reg), rhint

ret rhint

ret

Description

Return from Subroutine unconditionally returns from a subroutine. If a destination register is specified, the address of the instruction following the ret instruction is stored in the specified register. The source register contains the return address. If the source register is not specified, register $ra ($26) is used. If a hint is not specified, a hint value of 1 is used.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.

See Also

For information about branch prediction logic, see the Alpha Architecture Reference Manual.


Jump to Subroutine Return (jsr_coroutine)

Syntax

jsr_coroutine $d_reg, ($s_reg), rhint

jsr_coroutine $d_reg, ($s_reg)

jsr_coroutine $d_reg, rhint

jsr_coroutine $d_reg

jsr_coroutine ($s_reg), rhint

jsr_coroutine rhint

jsr_coroutine

Description

Jump to Subroutine Return unconditionally returns from a subroutine and stores the return address in the destination register. If a destination register is not specified, register $26 (ra) is used. The source register contains the target address. If the source register is not specified, register $26 (ra) is used.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.


Byte-Manipulation Instructions

Byte-manipulation instructions perform byte operations on values in registers.


Compare Byte Instruction

Compare Byte Instruction (cmpbge)

Syntax

cmpbge $s_reg1, $s_reg2, d_reg

cmpbge $d_reg/$s_reg1, $s_reg2

cmpbge $s_reg1, val_immed, $d_reg

cmpbge $d_reg/$s_reg1, val_immed

Description

Compare Byte performs eight parallel unsigned byte comparisons between corresponding bytes of register $s_reg1 and $s_reg2 or the immediate value. A bit is set in the destination register if a byte in $s_reg1 is greater than or equal to the corresponding byte in $s_reg2 or the immediate value.

The results of the comparisons are stored in the eight low-order bits of the destination register; bit 0 of the destination register corresponds to byte 0 and so forth. The 56 high-order bits of the destination register are cleared.


Extract Instructions

AExtract Instructions

Extract Instructions are a class of byte-manipulation instructions that extract byte or word data from values in registers.


Extract Byte Low (extbl)

Syntax

extbl $s_reg1, $s_reg2, $d_reg

extbl $d_reg/$s_reg1, $s_reg2

extbl $s_reg1, val_immed, $d_reg

extbl $d_reg/$s_reg1, val_immed

Description

Extract Byte Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the low-order byte into the destination register. The seven high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Extract Word Low (extwl)

Syntax

extwl $s_reg1, $s_reg2, $d_reg

extwl $d_reg/$s_reg1, $s_reg2

extwl $s_reg1, val_immed, $d_reg

extwl $d_reg/$s_reg1, val_immed

Description

Extract Word Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the two low-order bytes and stores them in the destination register. The six high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Extract Longword Low (extll)

Syntax

extll $s_reg1, $s_reg2, $d_reg

extll $d_reg/$s_reg1, $s_reg2

extll $s_reg1, val_immed, $d_reg

extll $d_reg/$s_reg1, val_immed

Description

Extract Longword Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the four low-order bytes and stores them in the destination register. The four high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Extract Quadword Low (extql)

Syntax

extql $s_reg1, $s_reg2, $d_reg

extql $d_reg/$s_reg1, $s_reg2

extql $s_reg1, val_immed, $d_reg

extql $d_reg/$s_reg1, val_immed

Description

Extract Quadword Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts all eight bytes and stores them in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the shift count.


Extract Word High (extwh)

Syntax

extwh $s_reg1, $s_reg2, $d_reg

extwh $d_reg/$s_reg1, $s_reg2

extwh $s_reg1, val_immed, $d_reg

extwh $d_reg/$s_reg1, val_immed

Description

Extract Word High shifts the register $s_reg1 left by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the two low-order bytes and stores them in the destination register. The six high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Extract Longword High (extlh)

Syntax

extlh $s_reg1, $s_reg2, $d_reg

extlh $d_reg/$s_reg1, $s_reg2

extlh $s_reg1, val_immed, $d_reg

extlh $d_reg/$s_reg1, val_immed

Description

Extract Longword High shifts the register $s_reg1 left by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the four low-order bytes and stores them in the destination register. The four high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Extract Quadword High (extqh)

Syntax

extqh $s_reg1, $s_reg2, $d_reg

extqh $d_reg/$s_reg1, $s_reg2

extqh $s_reg1, val_immed, $d_reg

extqh $d_reg/$s_reg1, val_immed

Description

Extract Quadword High shifts the register $s_reg1 left by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts all eight bytes and stores them in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the shift count.


Insert Instructions

Insert instructions are a form of byte-manipulation instructions in which byte and word quantities are inserted into the proper place into a register value.


Insert Byte Low (insbl)

Syntax

insbl $s_reg1, $s_reg2, $d_reg

insbl $d_reg/$s_reg1, $s_reg2

insbl $s_reg1, val_immed, $d_reg

insbl $d_reg/$s_reg1, val_immed

Description

Insert Byte Low shifts the register $s_reg1 left by 0-7 bytes, inserts the byte into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Insert Word Low (inswl)

Syntax

inswl $s_reg1, $s_reg2, $d_reg

inswl $d_reg/$s_reg1, $s_reg2

inswl $s_reg1, val_immed, $d_reg

inswl $d_reg/$s_reg1, val_immed

Description

Insert Word Low shifts the register $s_reg1 left by 0-7 bytes, inserts the word into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Insert Longword Low (insll)

Syntax

insll $s_reg1, $s_reg2, $d_reg

insll $d_reg/$s_reg1, $s_reg2

insll $s_reg1, val_immed, $d_reg

insll $d_reg/$s_reg1, val_immed

Description

Insert Longword Low shifts the register $s_reg1 left by 0-7 bytes, inserts the longword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Insert Quadword Low (insql)

Syntax

insql $s_reg1, $s_reg2, $d_reg

insql $d_reg/$s_reg1, $s_reg2

insql $s_reg1, val_immed, $d_reg

insql $d_reg/$s_reg1, val_immed

Description

Insert Quadword Low shifts the register $s_reg1 left by 0-7 bytes, inserts the quadword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Insert Word High (inswh)

Syntax

inswh $s_reg1, $s_reg2, $d_reg

inswh $d_reg/$s_reg1, $s_reg2

inswh $s_reg1, val_immed, $d_reg

inswh $d_reg/$s_reg1, val_immed

Description

Insert Word High shifts the register $s_reg1 right by 0-7 bytes, inserts the word into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Insert Longword High (inslh)

Syntax

inslh $s_reg1, $s_reg2, $d_reg

inslh $d_reg/$s_reg1, $s_reg2

inslh $s_reg1, val_immed, $d_reg

inslh $d_reg/$s_reg1, val_immed

Description

Insert Longword High shifts the register $s_reg1 right by 0-7 bytes, inserts the longword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Insert Quadword High (insqh)

Syntax

insqh $s_reg1, $s_reg2, $d_reg

insqh $d_reg/$s_reg1, $s_reg2

insqh $s_reg1, val_immed, $d_reg

insqh $d_reg/$s_reg1, val_immed

Description

Insert Quadword High shifts the register $s_reg1 right by 0-7 bytes, inserts the quadword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the byte shift count.


Mask Instructions

Mask instructions set byte, word and longword positions to zero in a register.


Mask Byte Low (mskbl)

Syntax

mskbl $s_reg1, $s_reg2, $d_reg

mskbl $d_reg/$s_reg1, $s_reg2

mskbl $s_reg1, val_immed, $d_reg

mskbl $d_reg/$s_reg1, val_immed

Description

Mask Byte Low sets a byte in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the offset of the byte.


Mask Word Low (mskwl)

Syntax

mskwl $s_reg1, $s_reg2, $d_reg

mskwl $d_reg/$s_reg1, $s_reg2

mskwl $s_reg1, val_immed, $d_reg

mskwl $d_reg/$s_reg1, val_immed

Description

Mask Word Low sets a word in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the offset of the word.


Mask Longword Low (mskll)

Syntax

mskll $s_reg1, $s_reg2, $d_reg

mskll $d_reg/$s_reg1, $s_reg2

mskll $s_reg1, val_immed, $d_reg

mskll $d_reg/$s_reg1, val_immed

Description

Mask Longword Low sets a longword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the offset of the longword.


Mask Quadword Low (mskql)

Syntax

mskql $s_reg1, $s_reg2, $d_reg

mskql $d_reg/$s_reg1, $s_reg2

mskql $s_reg1, val_immed, $d_reg

mskql $d_reg/$s_reg1, val_immed

Description

Mask Quadword Low sets a quadword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the offset of the quadword.


Mask Word High (mskwh)

Syntax

mskwh $s_reg1, $s_reg2, $d_reg

mskwh $d_reg/$s_reg1, $s_reg2

mskwh $s_reg1, val_immed, $d_reg

mskwh $d_reg/$s_reg1, val_immed

Description

Mask Word High sets a word in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the offset of the word.


Mask Longword High (msklh)

Syntax

msklh $s_reg1, $s_reg2, $d_reg

msklh $d_reg/$s_reg1, $s_reg2

msklh $s_reg1, val_immed, $d_reg

msklh $d_reg/$s_reg1, val_immed

Description

Mask Longword High sets a longword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the offset of the longword.


Mask Quadword High (mskqh)

Syntax

mskqh $s_reg1, $s_reg2, $d_reg

mskqh $d_reg/$s_reg1, $s_reg2

mskqh $s_reg1, val_immed, $d_reg

mskqh $d_reg/$s_reg1, val_immed

Description

Mask Quadword High sets a quadword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specifies the offset of the quadword.


Zero-Byte Instructions

The zero byte instructions set selected bytes in a register to zero.


Zero Bytes (zap)

Syntax

zap $s_reg1, $s_reg2, $d_reg

zap $d_reg/$s_reg1, $s_reg2

zap $s_reg1, val_immed, $d_reg

zap $d_reg/$s_reg1, val_immed

Description

Zero Bytes sets selected bytes of register $s_reg1 to zero and puts the result in the destination register. Bits 0-7 of register $s_reg2 or an immediate value specifies the bytes to be cleared to zeros. Each bit corresponds to one byte in register $s_reg1; for example, bit 0 corresponds to byte 0. A bit with a value of 1 indicates its corresponding byte should be cleared to zeros.


Zero Bytes NOT (zapnot)

Syntax

zapnot $s_reg1, $s_reg2, $d_reg

zapnot $d_reg/$s_reg1, $s_reg2

zapnot $s_reg1, val_immed, $d_reg

zapnot $d_reg/$s_reg1, val_immed

Description

Zero Bytes NOT sets selected bytes of register $s_reg1 to zero and puts the result in the destination register. Bits 0-7 of register $s_reg2 or an immediate value specifies the bytes to be cleared to zeros. Each bit corresponds to one byte in register $s_reg1; for example, bit 0 corresponds to byte 0. A bit with a value of zero indicates its corresponding byte should be cleared to zeros.


Special-Purpose Instructions

The special-purpose instructions perform miscellaneous tasks.


Call Privileged Architecture Library (call_pal)

Syntax

call_pal palcode

Description

Call Privileged Architecture Library unconditionally transfers control to the exception handler. The palcode operand is interpreted by software conventions.


Architecture Mask (amask)

Syntax

amask s_reg, d_reg

amask val_immed, d_reg

Description

The value of the contents of s_reg or the immediate value represents a mask of architectural extensions whose presence or absence is being tested. Bits become cleared if they correspond to architectural extensions that are present, and the result is placed in the destination register. To test for the presence of all architectural extensions, place the value 1 in each bit of either s_reg or the immediate value. The bits in d_reg that contain 0 after the instruction has executed correspond to the architectural extensions that are present.

The correspondence between bits and supported architectural extensions is as follows:

Bit | Architectural extension
0 | Byte/word extension (BWX) The instructions that the BWX extension comprises are LDBU, LDWU, SEXTB, SEXTW, STB, and STW.
1 | Count extension (CIX) The instructions that the CIX extension comprises are CTLZ, CTPOP, CTTZ, FTOIS, FTOIT, ITOFF, ITOFS, ITOFT, SQRTF, SQRTG, SQRTS, and SQRTT.
8 | Multimedia extension (MAX) The instructions that the MAX extension comprises are MAXSB8, MAXSW4, MAXUB8, MAXUW4, MINSB8, MINSW4, MINUB8, MINUW4, PERR, PKLB, PKWB, UNPKBL, and UNPKBW.

Note Use amask to make decisions about what instructions are available. Use implver to make decisions about how best to tune your code.


Implementation Version (implver)

Syntax

implver d_reg

Description

The value in d_reg specifies the major implementation version of the processor on which it is executed. The association between values and processors is as follows:

Value | Meaning
0 | 21064 (EV4) 21064A (EV45) 21066A/21068A (LCA45)
1 | 21164 (EV5) 21164A (EV56) 21164PC (PCA56)
2 | 21264 (EV6)

Note Use implver to make decisions about how best to tune your code. Use amask to make decisions about what instructions are available.


Prefetch Data (fetch)

Syntax

fetch address

Description

Prefetch Data indicates that the 512-byte block of data specified by the effective address should be moved to a faster-access part of the memory hierarchy.


Prefetch Data, Modify Intent (fetch_m)

Syntax

fetch_m address

Description

Prefetch Data indicates that the 512-byte block of data specified by the effective address should be moved to a faster-access part of the memory hierarchy. In addition, this instruction is a hint that part or all of the data may be modified.


Read Process Cycle Counter (rpcc)

Syntax

rpcc d_reg

Description

Read Process Cycle Counter returns the contents of the process cycle counter in the destination register.


No Operation (nop)

Syntax

nop

Description

No Operation has no effect on the machine state.


Universal No Operation (unop)

Syntax

unop

Description

Universal No Operation has no effect on the machine state.


Trap Barrier (trapb)

Syntax

trapb

Description

Trap Barrier guarantees that all previous arithmetic instructions complete, without incurring any arithmetic traps, before any instructions after the trapb instruction are issued.


Exception Barrier (excb)

Syntax

excb

Description

Exception Barrier guarantees that all previous instructions complete any exception-related behavior or rounding-mode behavior before any instructions after the excb instruction are issued.


Memory Barrier (mb)

Syntax

mb

Description

Memory Barrier is used to serialize access to memory.

See Also

For information on memory barriers, see the Alpha Architecture Reference Manual.


Write Memory Barrier (wmb)

Syntax

wmb

Description

Write Memory Barrier guarantees that all previous store instructions access memory before any store instructions issued after the wmb instruction.


Floating-Point Instruction Operand Descriptions

A floating-point instruction takes one or more of the following operands:

Operand | Description
address | A symbolic expression whose effective value is used as an address.
$d_reg | Destination register. A floating-point register that receives a value as a result of an operation.
$d_reg/$s_reg | One floating-point register that is used as both a source register and a destination register.
label | A label that identifies a location in a program.
$s_reg, $s_reg1, $s_reg2 | Source registers. Floating-point registers whose contents are to be used in an operation.
val_expr | An expression whose value is a floating-point constant.


NaN Values

The term NaN, which stands for “not a number,” means a symbolic entity that represents a value not otherwise available in floating-point format.

There are two kinds of NaNs:

  • Quiet NaNs represent unknown or uninitialized values.

  • Signaling NaNs represent symbolic values and values that are too big or too precise for the format. Signaling NaNs raise an invalid operation exception whenever an operation is attempted on them.


Floating-Point Control Register

The floating-point control register (FPCR) contains status and control information. It controls the arithmetic rounding mode of instructions that specify dynamic rounding (d qualifier) and gives a summary for each exception type of the exception conditions detected by the floating-point instructions. It also contains an overall summary bit indicating whether an exception occurred.

The format of the floating-point control register is as follows:

The fields of the floating-point control register have the following definitions:

Bits | Name | Description
63 | sum | Summary: records the bitwise OR of the FPCR exception bits (bits 57 to 52).
62-60 | raz/ign | Read-As-Zero: ignored when written.
59-58 | dyn | Dynamic Rounding Mode: indicates the current rounding mode to be used by an IEEE floating-point instruction that specifies dynamic mode ( d qualifier). The bit as follows: 00 Chopped rounding mode. 01 Minus infinity. 10 Normal rounding. 11 Plus infinity.
57 | iov | Integer overflow.
56 | ine | Inexact result.
55 | unf | Underflow.
54 | ovf | Overflow.
53 | dze | Division by zero.
52 | inv | Invalid operation.
51-0 | raz/ign | Read-As-Zero: ignored when written.


Floating-Point Exceptions

Six exception conditions can result from the use of floating-point instructions. All of the exceptions are signaled by an arithmetic exception trap. These exceptions include:

  • Invalid Operation. An invalid operation exception is signaled if any operand of a floating-point instruction, other than cmpt xx, is nonfinite (cmpt xx operates normally with plus and minus infinity). This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

  • Division by Zero. A division by zero exception is taken if the numerator does not cause an invalid operation trap and the denominator is zero. This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

  • Overflow. An overflow exception is signaled if the rounded result exceeds, in magnitude, the largest finite number of the destination format. This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

  • Underflow. An underflow exception occurs if the rounded result is smaller, in magnitude, than the smallest finite number of the destination format. This trap may be enabled with the v instruction qualifier. If this trap occurs, a true zero is always stored in the destination register.

  • Inexact Result. An inexact result exception occurs if the infinitely precise result differs from the rounded result. This trap is disabled by default, and may be enabled. If this trap occurs, the normal rounded result is still stored in the destination register.

  • Integer Overflow. An integer overflow exception occurs if the conversion from a floating-point or integer format to an integer format results in a value that is outside of the range of values representable by the destination format. This trap is disabled by default, and may be enabled. If this trap occurs, the true result is truncated to the number of bits in the destination format and stored in the destination register.


Floating-Point Instruction Qualifiers

Many of the floating-point instructions accept a qualifier that specifies rounding and trapping modes.

Note The qualifier syntax used by Alpha assembler deviates slightly from the Alpha Architecture Reference Manual.


Rounding Mode Qualifiers

Appending one or more letters to a floating-point instruction determines the VAX or IEEE rounding mode to be used.

VAX Rounding Mode Qualifiers

Mode | Qualifier
Normal rounding | None
Chopped | c

IEEE Rounding Mode Qualifiers

Mode | Qualifiers
Normal rounding | None
Plus infinity | d (ensure that the dyn field of the FPCR is 11)
Minus infinity | m
Chopped | c


VAX Trapping Modes

The following tables detail VAX trapping modes and their qualifiers.

VAX Trapping Mode Qualifiers

Mode | Qualifier
Imprecise, underflow disabled | None
Imprecise, underflow enabled | u
Software, underflow disabled | s
Software, underflow enabled | su

VAX Convert-to-Integer Trapping Modes

Mode | Qualifier
Imprecise, integer overflow disabled | None
Imprecise, integer overflow enabled | v
Software, integer overflow disabled | s
Software, integer overflow enabled | sv


IEEE Trapping Modes

IEEE Trapping Modes and Their Qualifiers.

Mode | Qualifier
Imprecise, underflow disabled, inexact disabled | None
Imprecise, underflow enabled, inexact disabled | u
Software, underflow enabled, inexact disabled | su
Software, underflow enabled, inexact enabled | sui

IEEE Convert-to-Integer Trapping Modes

Mode | Qualifier
Imprecise, integer overflow disabled, inexact disabled | None
Imprecise, integer overflow enabled, inexact disabled | v
Software, integer overflow enabled, inexact disabled | sv
Software, integer overflow enabled, inexact enabled | svi


Floating-Point Data Types

Floating-point instructions operate on the following data types:

  • S_floating (IEEE single precision)

  • T_floating (IEEE double precision)

  • Longword integer and quadword integer

  • F_floating (VAX single precision)

  • D_floating (VAX double precision, limited support)

  • G_floating (VAX double precision)


S_floating Data Format

The format for the S_floating data type is as follows:


T_floating Data Format

The format for the T_floating data type is as follows:


F_floating Data Format

The format for the F_floating data type is as follows:


D_floating Data Format

The format for the D_floating data type is as follows:


G_floating Data Format

The format for the G_floating data type is as follows:


Floating-Point Load Instructions


Load F_floating (ldf)

Syntax

ldf $d_reg, address

Description

Load F_floating loads 4 bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load G_floating Load D_floating (ldg)

Syntax

ldg $d_reg, address

Description

Load G_floating Load D_floating loads 8 bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load S_floating Load Longword (lds)

Syntax

lds $d_reg, address

Description

Load S_floating Load Longword loads 4 bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load T_floating Load Quadword (ldt)

Syntax

ldt $d_reg, address

Description

Load T_floating Load Quadword loads 8 bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load Immediate F_floating (ldif)

Syntax

ldif $d_reg, val_expr

Description

Load Immediate F_floating loads 4 bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load Immediate D_floating (ldid)

Syntax

ldid $d_reg, val_expr

Description

Load Immediate D_floating loads 8 bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load Immediate G_floating (ldig)

Syntax

ldig $d_reg, val_expr

Description

Load Immediate G_floating loads 8 bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load Immediate S_floating Load Longword (ldis)

Load Immediate S_floating (ldis)

Syntax

ldis $d_reg, val_expr

Description

Load Immediate S_floating Load Longword) loads 4 bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load Immediate T_floating Load Quadword (ldit)

Syntax

ldit $d_reg, val_expr

Description

Load Immediate T_floating Load Quadword loads 8 bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Floating-Point Store Instructions


Store F_floating (stf)

Syntax

stf $s_reg, address

Description

Store F_floating stores 4 bytes from the source floating-point register into the specified effective address. The address must be longword aligned for 4-byte store instructions.


Store G_floating Store D_floating (stg)

Syntax

stg $s_reg, address

Description

Store G_floating Store D_floating stores 8 bytes from the source floating-point register into the specified effective address. The address must be quadword aligned for 8-byte store instructions.


Store S_floating Store Longword (sts)

Syntax

sts $s_reg, address

Description

Store S_floating Store Longword stores 4 bytes from the source floating-point register into the specified effective address. The address must be longword aligned for 4-byte store instructions.


Store T_floating Store Quadword (stt)

Syntax

stt $s_reg, address

Description

Store T_floating Store Quadword stores 8 bytes from the source floating-point register into the specified effective address. The address must be quadword aligned for 8-byte store instructions.


Floating-Point Arithmetic Instructions


Floating Clear Instruction

Floating Clear Instruction (fclr)

Syntax

fclr $d_reg

Description

Floating Clear places a 0 in the destination register.


Floating Absolute Value Instruction

Floating Absolute Value Instruction (fabs)

Syntax

fabs $s_reg, $d_reg

fabs $d_reg/$s_reg

Description

Floating Absolute Value computes the absolute value of the contents of the source register and places the floating-point result in the destination register.


Negate F_floating (negf)

Syntax

negf $s_reg, $d_reg

negf $d_reg/$s_reg

Description

Negate F_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negf instruction:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
negfs | VAX Trap Mode: Software, underflow disabled
 | VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled


Negate G_floating (negg)

Syntax

negg $s_reg, $d_reg

negg $d_reg/$s_reg

Description

Negate G_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negg instruction:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
neggs | VAX Trap Mode: Software, underflow disabled
 | VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled


Negate S_floating (negs)

Syntax

negs $s_reg, $d_reg

negs $d_reg/$s_reg

Description

Negate S_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negs instruction:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
negssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled


Negate T_floating (negt)

Syntax

negt $s_reg, $d_reg

negt $d_reg/$s_reg

Description

Negate T_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negt instruction:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
negtsu | IEEE Trap Mode: Software, underflow enabled, inexact disabled


Add F_floating (addf)

Syntax

addf $s_reg1, $s_reg2, $d_reg

addf $d_reg/$s_reg1, $s_reg2

Description

Add F_floating adds the contents of $s_reg1 or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly 0, the sum has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the addf instructions:

Instruction | Qualifier Description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
addfc | VAX Rounding Mode: Chopped
addfu | VAX Trap Mode: Imprecise, underflow enabled
addfuc | Combined meanings of addfc and addfu
addfs | VAX Trap Mode: Software, underflow disabled
addfsc | Combined meanings of addfs and addfc
addfsu | VAX Trap Mode: Software, underflow enabled
addfsuc | Combined meanings of addfs and addfuc


Add G_floating (addg)

Syntax

addg $s_reg1, $s_reg2, $d_reg

addg $d_reg/$s_reg1, $s_reg2

Description

Add G_floating adds the contents of $s_reg1 or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly 0, the sum has a positive sign for all rounding modes except round toward minus infinity (–¥). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the addg instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
addgc | VAX Rounding Mode: Chopped
addgu | VAX Trap Mode: Imprecise, underflow enabled
addguc | Combined meanings of addgc and addgu
addgs | VAX Trap Mode: Software, underflow disabled
addgsc | Combined meanings of addgs and addgc
addgsu | VAX Trap Mode: Software, underflow enabled
addgsuc | Combined meanings of addgs and addguc


Add S_floating (adds)

Syntax

adds $s_reg1, $s_reg2, $d_reg

adds $d_reg/$s_reg1, $s_reg2

Description

Add S_floating adds the contents of $s_reg1 or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly 0, the sum has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the adds instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
addsc | IEEE Rounding Mode: Chopped
addsm | IEEE Rounding Mode: Minus infinity
addsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
addsu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
addsuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
addsum | Combined meanings of addsu and addsm
addsud | Combined meanings of addsu and addsd
addssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
addssuc | Combined meanings of addss, addsu, and addsc
addssum | Combined meanings of addss, addsu, and addsm
addssud | Combined meanings of addss, addsu, and addsd
addssui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
addssuic | Combined meanings of addssui and addsc
addssuim | Combined meanings of addssui and addsm


Add T_floating (addt)

Syntax

addt $s_reg1, $s_reg2, $d_reg

addt $d_reg/$s_reg1, $s_reg2

Description

Add T_floating adds the contents of $s_reg1 or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly 0, the sum has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the addt instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
addtc | IEEE Rounding Mode: Chopped
addtm | IEEE Rounding Mode: Minus infinity
addtd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
addtu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
addtuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
addtum | Combined meanings of addtu and addtm
addtud | Combined meanings of addtu and addtd
addtsu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
addtsuc | Combined meanings of addts, addtu, and addtc
addtsum | Combined meanings of addts, addtu, and addtm
addtsud | Combined meanings of addts, addtu, and addtd
addtsui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
addtsuic | Combined meanings of addtsui and addtc
addtsuim | Combined meanings of addtsui and addtm


Divide F_floating (divf)

Syntax

divf $s_reg1, $s_reg2, $d_reg

divf $d_reg/$s_reg1, $s_reg2

Description

Divide F_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and place the result in $d_reg. If the divisor is 0, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divf instructions:

Instruction | Description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
divfc | VAX Rounding Mode: Chopped
divfu | VAX Trap Mode: Imprecise, underflow enabled
divfuc | VAX Trap Mode: Underflow enabled
 | VAX Rounding Mode: Chopped
divfs | VAX Trap Mode: Software, underflow disabled
divfsc | Combined meanings of divfs and divfc
divfsu | VAX Trap Mode: Software, underflow enabled
divfsuc | Combined meanings of divfs, divfu, and divfc


Divide G_floating (divg)

Syntax

divg $s_reg1, $s_reg2, $d_reg

divg $d_reg/$s_reg1, $s_reg2

Description

Divide G_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and place the result in $d_reg. If the divisor is 0, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divg instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
divgc | VAX Rounding Mode: Chopped
divgu | VAX Trap Mode: Imprecise, underflow enabled
divguc | VAX Trap Mode: Underflow enabled
 | VAX Rounding Mode: Chopped
divgs | VAX Trap Mode: Software, underflow disabled
divgsc | Combined meanings of divgs and divgc
divgsu | VAX Trap Mode: Software, underflow enabled
divgsuc | Combined meanings of divgs, divgu, and divgc


Divide S_floating (divs)

Syntax

divs $s_reg1, $s_reg2, $d_reg

divs $d_reg/$s_reg1, $s_reg2

Description

Divide S_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and place the result in $d_reg. If the divisor is 0, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divs instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
divsc | IEEE Rounding Mode: Chopped
divsm | IEEE Rounding Mode: Minus infinity
divsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
divsu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
divsuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
divsum | Combined meanings of divsu and divsm
divsud | Combined meanings of divsu and divsd
divssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
divssuc | Combined meanings of divss, divsu, and divsc
divssum | Combined meanings of divss, divsu, and divsm
divssud | Combined meanings of divss, divsu, and divsd
divssu | IEEE Trap Mode: Software, underflow enabled, inexact enabled
divssuic | Combined meanings of divssui and divsc
divssuim | Combined meanings of divssui and divsm


Divide T_floating (divt)

Syntax

divt $s_reg1, $s_reg2, $d_reg

divt $d_reg/$s_reg1, $s_reg2

Description

Divide T_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and place the result in $d_reg. If the divisor is 0, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divt instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
divtc | IEEE Rounding Mode: Chopped
divtm | IEEE Rounding Mode: Minus infinity
divtd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
divtu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
divtuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
divtum | Combined meanings of divtu and divtm
divtud | Combined meanings of divtu and divtd
divtsu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
divtsuc | Combined meanings of divts, divtu, and divtc
divtsum | Combined meanings of divts, divtu, and divtm
divtsud | Combined meanings of divts, divtu, and addtd
divtsui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
divtsuic | Combined meanings of divtsui and divtc
divtsuim | Combined meanings of divtsui and divtm


Multiply F_floating (mulf)

Syntax

mulf $s_reg1, $s_reg2, $d_reg

mulf $d_reg/$s_reg1, $s_reg2

Description

Multiply F_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode. The single-precision operation on canonical single-precision values produces a canonical single-precision result.

Qualifiers

The following table describes the qualifiers for the mulf instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
mulfc | VAX Rounding Mode: Chopped
mulfu | VAX Trap Mode: Imprecise, underflow enabled
mulfuc | Combined meanings of mulfc and mulfu
mulf | VAX Trap Mode: Software, underflow disabled
mulfsc | Combined meanings of mulfs and mulfc
mulfsu | VAX Trap Mode: Software, underflow enabled
mulfsuc | Combined meanings of mulfs and mulfuc


Multiply G_floating (mulg)

Syntax

mulg $s_reg1, $s_reg2, $d_reg

mulg $d_reg/$s_reg1, $s_reg2

Description

Multiply G_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode.

Qualifiers

The following table describes the qualifiers for the mulg instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
mulgc | VAX Rounding Mode: Chopped
mulgu | VAX Trap Mode: Imprecise, underflow enabled
mulguc | Combined meanings of mulgc and mulgu
mulgs | VAX Trap Mode: Software, underflow disabled
mulgsc | Combined meanings of mulgs and mulgc
mulgsu | VAX Trap Mode: Software, underflow enabled
mulgsuc | Combined meanings of mulgs and mulguc


Multiply S_floating (muls)

Syntax

muls $s_reg1, $s_reg2, $d_reg

muls $d_reg/$s_reg1, $s_reg2

Description

Multiply S_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode. The single-precision operation on canonical single-precision values produces a canonical single-precision result.

Qualifiers

The following table describes the qualifiers for the muls instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
mulsc | IEEE Rounding Mode: Chopped
mulsm | IEEE Rounding Mode: Minus infinity
mulsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
mulsu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
mulsuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
mulsum | Combined meanings of mulsu and mulsm
mulsud | Combined meanings of mulsu and mulsd
mulssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
mulssuc | Combined meanings of mulss, mulsu, and mulsc
mulssum | Combined meanings of mulss, mulsu, and mulsm
mulssud | Combined meanings of mulss, mulsu, and mulsd
mulssui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
mulssuic | Combined meanings of mulssui and mulsc
mulssuim | Combined meanings of mulssui and mulsm


Multiply T_floating (mult)

Syntax

mult $s_reg1, $s_reg2, $d_reg

mult $d_reg/$s_reg1, $s_reg2

Description

Multiply T_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode.

Qualifiers

The following table describes the qualifiers for the mult instructions:

Instruction | Description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
multc | IEEE Rounding Mode: Chopped
multm | IEEE Rounding Mode: Minus infinity
multd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
multu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
multuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
multum | Combined meanings of multu and multm
multud | Combined meanings of multu and multd
multsu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
multsuc | Combined meanings of mults, multu, and multc
multsum | Combined meanings of mults, multu, and multm
multsud | Combined meanings of mults, multsu, and multd
multsui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
multsuic | Combined meanings of multsui and multc
multsuim | Combined meanings of multsui and multm


Subtract F_floating (subf)

Syntax

subf $s_reg1, $s_reg2, $d_reg

subf $d_reg/$s_reg1, $s_reg2

Description

Subtract F_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly 0, the difference has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subf instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
subfc | VAX Rounding Mode: Chopped
subfu | VAX Trap Mode: Imprecise, underflow enabled
subfuc | Combined meanings of subfc and subfu
subfs | VAX Trap Mode: Software, underflow disabled
subfsc | Combined meanings of subfs and subfc
subfsu | VAX Trap Mode: Software, underflow enabled
subfsuc | Combined meanings of subfs and subfuc


Subtract G_floating (subg)

Syntax

subg $s_reg1, $s_reg2, $d_reg

subg $d_reg/$s_reg1, $s_reg2

Description

Subtract G_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly 0, the difference has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subg instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
subgc | VAX Rounding Mode: Chopped
subgu | VAX Trap Mode: Imprecise, underflow enabled
subguc | Combined meanings of subgc and subgu
subgs | VAX Trap Mode: Software, underflow disabled
subgsc | Combined meanings of subgs and subgc
subgsu | VAX Trap Mode: Software, underflow enabled
subgsuc | Combined meanings of subgs and subguc


Subtract S_floating (subs)

Syntax

subs $s_reg1, $s_reg2, $d_reg

subs $d_reg/$s_reg1, $s_reg2

Description

Subtract S_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly 0, the difference has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subs instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
subsc | IEEE Rounding Mode: Chopped
subsm | IEEE Rounding Mode: Minus infinity
subsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
subsu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
subsuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
subsum | Combined meanings of subsu and subsm
subsud | Combined meanings of subsu and subsd
subssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
subssuc | Combined meanings of subss, subsu, and subsc
subssum | Combined meanings of subss, subsu, and subsm
subssud | Combined meanings of subss, subsu, and subsd
subssui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
subssuic | Combined meanings of subssui and subsc
subssuim | Combined meanings of subssui and subsm


Subtract T_floating (subt)

Syntax

subt $s_reg1, $s_reg2, $d_reg

subt $d_reg/$s_reg1, $s_reg2

Description

Subtract T_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly 0, the difference has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subt instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
subtc | IEEE Rounding Mode: Chopped
subtm | IEEE Rounding Mode: Minus infinity
subtd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
subtu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
subtuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
subtum | Combined meanings of subtu and subtm
subtud | Combined meanings of subtu and subtd
subtsu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
subtsuc | Combined meanings of subts, subtu, and subtc
subtsum | Combined meanings of subts, subtu, and subtm
subtsud | Combined meanings of subts, subtu, and subtd
subtsui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
subtsuic | Combined meanings of subtsui and subtc
Subtsuim | Combined meanings of subtsui and subtm


Convert Quadword to Longword (cvtql)

Syntax

cvtql $s_reg, $d_reg

cvtql $d_reg/$s_reg

Description

Convert Quadword to Longword converts the quadword integer contents of $s_reg to the longword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtql instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cvtqlv | IEEE Convert-to-Integer Trap Mode: Imprecise, integer overflow enabled, inexact disabled
cvtqlsv | IEEE Convert-to-Integer Trap Mode: Software, integer overflow enabled, inexact disabled


Convert Longword to Quadword (cvtlq)

Syntax

cvtlq $s_reg, $d_reg

cvtlq $d_reg/$s_reg

Description

Convert Longword to Quadword converts the longword integer contents of $s_reg to the quadword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.


Convert G_floating to Quadword (cvtgq)

Syntax

cvtgq $s_reg, $d_reg

cvtgq $d_reg/$s_reg

Description

Convert G_floating to Quadword converts the G_floating contents of $s_reg to the quadword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtgq instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cvtgqc | VAX Rounding Mode: Chopped
cvtgqv | VAX Convert-to-Integer Trap Mode: Imprecise, integer overflow enabled
cvtgqvc | Combined meanings of cvtgqv and cvtgqc
cvtgqs | VAX Trap Mode: Software, underflow enabled
 | VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled
cvtgqsc | Combined meanings of cvtgqs and cvtgqc
cvtgqsv | VAX Convert-to-Integer Trap Mode: Software, integer overflow enabled
cvtgqsvc | Combined meanings of cvtgqs, cvtgqv, and cvtgqc


Convert T_floating to Quadword (cvttq)

Syntax

cvttq $s_reg, $d_reg

cvttq $d_reg/$s_reg

Description

Convert T_floating to Quadword converts the T_floating contents of $s_reg to the quadword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.

Qualifiers

The following table describes the qualifiers for the cvttq instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cvttqc | IEEE Rounding Mode: Chopped
cvttqv | IEEE Convert-to-Integer Trap Mode: Imprecise, integer overflow enabled, inexact disabled
cvttqvc | Combined meanings of cvtgqv and cvtgqc
cvttqsv | IEEE Convert-to-Integer Trap Mode: Software, integer overflow enabled, inexact disabled
cvttqsvc | Combined meanings of cvttqs, cvtgqv, and cvttqc
cvttqsvi | IEEE Convert-to-Integer Trap Mode: Software, integer overflow enabled, inexact enabled
cvttqsvic | Combined meanings of cvttqsvi and cvttqc
cvttqd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
cvttqvd | Combined meanings of cvttqv and cvttqd
cvttqsvd | Combined meanings of cvttqsv and cvttqd
cvttqsvid | Combined meanings of cvttqsvi and cvttqd


Convert Quadword to F_floating (cvtqf)

Syntax

cvtqf $s_reg, $d_reg

cvtqf $d_reg/$s_reg

Description

Convert Quadword to F_floating converts the quadword integer contents of $s_reg to the F_floating-point format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqf instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cvtqfc | VAX Rounding Mode: Chopped


Convert Quadword to G_floating (cvtqg)

Syntax

cvtqg $s_reg, $d_reg

cvtqg $d_reg/$s_reg

Description

Convert Quadword to G_floating converts the quadword integer contents of $s_reg to the G_floating format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqg instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cvtqgc | VAX Rounding Mode: Chopped


Convert Quadword to S_floating (cvtqs)

Syntax

cvtqs $s_reg, $d_reg

cvtqs $d_reg/$s_reg

Description

Convert Quadword to S_floating converts the quadword integer contents of $s_reg to the S_floating format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqs instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cvtqsc | IEEE Rounding Mode: Chopped
cvtqsm | IEEE Rounding Mode: Minus infinity
cvtqsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
cvtqssu | IEEE Trap Mode: Software, underflow enabled, inexact enabled
cvtqssuic | Combined meanings of cvtqssui and cvtqsc
cvtqssuim | Combined meanings of cvtqssui and cvtqsm
cvtqssuid | Combined meanings of cvtqssui and cvtqsd


Convert Quadword to T_floating (cvtqt)

Syntax

cvtqt $s_reg, $d_reg

cvtqt $d_reg/$s_reg

Description

Convert Quadword to T_floating converts the quadword integer contents of $s_reg to the T_floating format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqt instructions:

Instruction | Qualifier description
cvtqtc | IEEE Rounding Mode: Chopped
cvtqtm | IEEE Rounding Mode: Minus infinity
cvtqtd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
cvtqtsui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
cvtqtsuic | Combined meanings of cvtqtsui and cvtqtc
cvtqtsuim | Combined meanings of cvtqssui and cvtqtm
cvtqtsuid | Combined meanings of cvtqtsui and cvtqtd


Convert D_floating to G_floating (cvtdg)

Syntax

cvtdg $s_reg, $d_reg

cvtdg $d_reg/$s_reg

Description

Convert D_floating to G_floating converts the D_floating contents of $s_reg to the G_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtdg instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cvtdgc | VAX Rounding Mode: Chopped
cvtdgu | VAX Trap Mode: Imprecise, underflow enabled
cvtdguc | Combined meanings of cvtdgc and cvtdgu
cvtdgs | VAX Trap Mode: Software, underflow disabled
 | VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled
cvtdgsc | Combined meanings of cvtdgs and cvtdgc
cvtdgsu | VAX Trap Mode: Software, underflow enabled
cvtdgsuc | Combined meanings of cvtdgs and cvtdguc


Convert G_floating to D_floating (cvtgd)

Syntax

cvtgd $s_reg, $d_reg

cvtgd $d_reg/$s_reg

Description

Convert G_floating to D_floating converts the G_floating contents of $s_reg to the D_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtgd instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cvtgdc | VAX Rounding Mode: Chopped
cvtgdu | VAX Trap Mode: Imprecise, underflow enabled
cvtgduc | Combined meanings of cvtgdc and cvtgdu
cvtgds | VAX Trap Mode: Software, underflow disabled
 | VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled
cvtgdsc | Combined meanings of cvtgds and cvtgdc
cvtgdsu | VAX Trap Mode: Software, underflow enabled
cvtgdsuc | Combined meanings of cvtgds and cvtgduc


Convert G_floating to F_floating (cvtgf)

Syntax

cvtgf $s_reg, $d_reg

cvtgf $d_reg/$s_reg

Description

Convert G_floating to F_floating converts the G_floating contents of $s_reg to the F_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtgf instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cvtgfc | VAX Rounding Mode: Chopped
cvtgfu | VAX Trap Mode: Imprecise, underflow enabled
cvtgfuc | Combined meanings of cvtgfc and cvtgfu
cvtgfs | VAX Trap Mode: Software, underflow disabled
 | VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled
cvtgfsc | Combined meanings of cvtgfs and cvtgfc
cvtgfsu | VAX Trap Mode: Software, underflow enabled
cvtgfsuc | Combined meanings of cvtgfs and cvtgfuc


Convert T_floating to S_floating (cvtts)

Syntax

cvtts $s_reg, $d_reg

cvtts $d_reg/$s_reg

Description

Convert T_floating to S_floating converts the T_floating contents of $s_reg to the S_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtts instructions:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cvttsc | IEEE Rounding Mode: Chopped
cvttsm | IEEE Rounding Mode: Minus infinity
cvttsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
cvttsu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
cvttsuc | IEEE Trap Mode: Underflow enabled
 | IEEE Rounding Mode: Chopped
cvttsum | Combined meanings of cvttsu and cvttsm
cvttsud | Combined meanings of cvttsu and cvttsd
cvttssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled
cvttssuc | Combined meanings of cvttss, cvttsu, and cvttsc
cvttssum | Combined meanings of cvttss, cvttsu, and cvttsm
cvttssud | Combined meanings of cvttss, cvttsu, and cvttd
cvttssui | IEEE Trap Mode: Software, underflow enabled, inexact enabled
cvttssuic | Combined meanings of cvttssui and cvttsc
cvttssuim | Combined meanings of cvttssui and cvttsm


Convert S_floating to T_floating (cvtst)

Syntax

cvtst $s_reg, $d_reg

cvtst $d_reg/$s_reg

Description

Convert S_floating to T_floating converts the S_floating contents of $s_reg to the T_floating precision. No rounding occurs and the result is exact. No underflow, overflow, or inexact result can occur. In fact, the conversion for finite values is the identity transformation.

Qualifiers

The following table describes the qualifiers for the cvtst instructions:

Instruction | Qualifier description
no qualifier | Exact result, no traps.
Cvtsts | IEEE Trap Mode: A trap handler can convert an S_floating denormal value int the corresponding T_floating finite value by adding 896 to the exponent and normalizing.


Compare G_floating Equal (cmpgeq)

Syntax

cmpgeq $s_reg1, $s_reg2, $d_reg

cmpgeq $d_reg/$s_reg1, $s_reg2

Description

Compare G_floating Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 equals $s_reg2, a nonzero value is written to the destination register; otherwise, a true 0 value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpgeq instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cmpgeqs | VAX Trap Mode: Software, underflow disabled


Compare G_floating Less Than (cmpglt)

Syntax

cmpglt $s_reg1, $s_reg2, $d_reg

cmpglt $d_reg/$s_reg1, $s_reg2

Description

Compare G_floating Less Than compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than s_reg2, a nonzero value is written to the destination register; otherwise, a true 0 value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpglt instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cmpglts | VAX Trap Mode: Software, underflow disabled


Compare G_floating Less Than or Equal (cmpgle)

Syntax

cmpgle $s_reg1, $s_reg2, $d_reg

cmpgle $d_reg/$s_reg1, $s_reg2

Description

Compare G_floating Less Than or Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than or equal to $s_reg2, a nonzero value is written to the destination register; otherwise, a true 0 value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpgle instructions:

Instruction | Qualifier description
no qualifier | VAX Rounding Mode: Normal rounding
 | VAX Trap Mode: Imprecise, underflow disabled
cmpgles | VAX Trap Mode: Software, underflow_disabled


Compare T_floating Equal (cmpteq)

Syntax

cmpteq $s_reg1, $s_reg2, $d_reg

cmpteq $d_reg/$s_reg1, $s_reg2

Description

Compare T_floating Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 equals $s_reg2, a nonzero value is written to the destination register; otherwise, a true 0 value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpteq instruction:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cmpteqsu | IEEE Trap Mode: Software, underflow enabled, inexact_disabled


Compare T_floating Less Than (cmptlt)

Syntax

cmptlt $s_reg1, $s_reg2, $d_reg

cmptlt $d_reg/$s_reg1, $s_reg2

Description

Compare T_floating Less Than compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than $s_reg2, a nonzero value is written to the destination register; otherwise, a true 0 value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmptlt instruction:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cmptltsu | IEEE Trap Mode: Software, underflow enabled, inexact disabled


Compare T_floating Less Than or Equal (cmptle)

Syntax

cmptle $s_reg1, $s_reg2, $d_reg

cmptle $d_reg/$s_reg1, $s_reg2

Description

Compare T_floating Less Than or Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than or equal to $s_reg2, a nonzero value is written to the destination register; otherwise, a true 0 value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmptle instruction:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cmptlesu | IEEE Trap Mode: Software, underflow enabled, inexact disabled


Compare T_floating Unordered (cmptun)

Syntax

cmptun $s_reg1, $s_reg2, $d_reg

cmptun $d_reg/$s_reg1, $s_reg2

Description

Compare T_floating Unordered compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If either $s_reg1 or $s_reg2 is unordered, a nonzero value is written to the destination register; otherwise, a true 0 value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmptun instruction:

Instruction | Qualifier description
no qualifier | IEEE Rounding Mode: Normal rounding
 | IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
cmptunsu | IEEE Trap Mode: Software, underflow enabled, inexact disabled


Floating Move (fmov)

Syntax

fmov $s_reg, $d_reg

Description

Floating Move moves the double- or single-precision contents of $s_reg to $d_reg.


Copy Sign (cpys)

Syntax

cpys $s_reg1, $s_reg2, $d_reg

cpys $d_reg/$s_reg1, $s_reg2

Description

Copy Sign fetches the sign bit of $s_reg1 or $d_reg, combines it with the exponent and fraction of $s_reg2, and copies the result to $d_reg.


Copy Sign Negate (cpysn)

Syntax

cpysn $s_reg1, $s_reg2, $d_reg

cpysn $d_reg/$s_reg1, $s_reg2

Description

Copy Sign Negate fetches the sign bit of $s_reg1 or $d_reg, complements it, combines it with the exponent and fraction of $s_reg2, and copies the result to $d_reg.


Copy Sign and Exponent (cpyse)

Syntax

cpyse $s_reg1, $s_reg2, $d_reg

cpyse $d_reg/$s_reg1, $s_reg2

Description

Copy Sign and Exponent fetches the sign and exponent of $s_reg1 or $d_reg, combines them with the fraction of $s_reg2, and copies the result to $d_reg.


Move if Equal to Zero (fcmoveq)

Syntax

fcmoveq $s_reg1, $s_reg2, $d_reg

fcmoveq $d_reg1/$s_reg1, $s_reg2

Description

Move if Equal to Zero compares the contents of $s_reg1 or $d_reg against 0. If equal to 0, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Not Equal to Zero (fcmovne)

Syntax

fcmovne $s_reg1, $s_reg2, $d_reg

fcmovne $d_reg1/$s_reg1, $s_reg2

Description

Move if Not Equal to Zero compares the contents of $s_reg1 or $d_reg against 0. If not equal to 0, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move If Less Than Zero (fcmovlt)

Syntax

fcmovlt $s_reg1, $s_reg2, $d_reg

fcmovlt $d_reg1/$s_reg1, $s_reg2

Description

Move if Less Than Zero compares the contents of $s_reg1 or $d_reg against 0. If less than 0, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Less Than or Equal to Zero (fcmovle)

Syntax

fcmovle $s_reg1, $s_reg2, $d_reg

fcmovle $d_reg1/$s_reg1, $s_reg2

Description

Move if Less Than or Equal to Zero compares the contents of $s_reg1 or $d_reg against 0. If less than or equal to 0, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Greater Than Zero (fcmovgt)

Syntax

fcmovgt $s_reg1, $s_reg2, $d_reg

fcmovgt $d_reg1/$s_reg1, $s_reg2

Description

Move if Greater Than Zero compares the contents of $s_reg1 or $d_reg against 0. If greater than 0, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Greater Than or Equal to Zero (fcmovge)

Syntax

fcmovge $s_reg1, $s_reg2, $d_reg

fcmovge $d_reg1/$s_reg1, $s_reg2

Description

Move if Greater Than or Equal to Zero compares the contents of $s_reg1 or $d_reg against 0. If greater than or equal to 0, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Branch Equal to Zero (fbeq)

Syntax

fbeq $s_reg, lab

Description

Branch Equal to Zero compares the contents of the source register with 0. If equal to 0, a branch is made to the specified label.


Branch Not Equal to Zero (fbne)

Syntax

fbne $s_reg, label

Description

Branch Not Equal to Zero compares the contents of the source register with 0. If not equal to 0, a branch is made to the specified label.


Branch Less Than Zero (fblt)

Syntax

fblt $s_reg, label

Description

Branch Less Than Zero compares the contents of the source register with 0. If less than 0, a branch is made to the specified label.


Branch Less Than or Equal to Zero (fble)

Syntax

fble $s_reg, label

Description

Branch Less Than or Equal to Zero compares the contents of the source register with 0. If less than or equal to 0, a branch is made to the specified label.


Branch Greater Than Zero (fbgt)

Syntax

fbgt $s_reg, label

Description

Branch Greater Than Zero compares the contents of the source register with 0. If greater than 0, a branch is made to the specified label.


Branch Greater Than or Equal to Zero (fbge)

Syntax

fbge $s_reg, label

Description

Branch Greater Than or Equal to Zero compares the contents of the source register with 0. If greater than or equal to 0, a branch is made to the specified label.


Move from FP Control Register (mf_fpcr)

Syntax

mf_fpcr $d_reg

Description

Move from FP Control Register copies the value in the specified source register to the FPCR.


Move to FP Control Register (mt_fpcr)

Syntax

mt_fpcr $d_reg

Description

Move to FP Control Register copies the value in the FPCR to the specified destination register.


No Operation (fnop)

Syntax

fnop

Description

No Operation has no effect on the machine state.


Assembler Directives

Assembler directives are instructions to the assembler to perform various bookkeeping tasks, storage reservation, and other control functions. To distinguish them from other instructions, directive names begin with a period.

The assembler directives fall into the following categories:

  • Compiler-Use-Only Directives

  • Data Storage Directives

  • Location Control Directives

  • Symbol Declaration Directives

  • Routine Entry Point Definition Directives

  • Repeat Block Directives

  • Assembler Option Directive (.set)

  • Procedure Attribute Directives

  • Version Control Directive (.verstamp)


Compiler Use Only Directives

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.arch Directive

Syntax

.arch model

Description

The .arch directive specifies the version of the Alpha architecture for which the Assembler is to generate instructions. Regardless of the version actually being used, any instruction in the entire instruction set is potentially available through it. If the version does not support an instruction in its hardware, then the compiler can produce a combination of instructions that perform the same actions and that the version does support.

Note The instructions that the assembler generates in this manner are usually inefficient. However, if the instructions are generated for a particular version of the Alpha architecture, then they will perform relatively well on that architecture. On the other hand, they might perform very badly on another architecture.

The valid values for model, along with descriptions of the instructions that the Assembler is to generate, are as follows:

Model | Instructions to generate
generic All instructions that are hard-wired into every Alpha processor.

This is the model that the Assembler assumes if you omit the .arch directive.
host | All instructions directly supported by the Alpha processor on which the Assembler is running.
ev4,ev5 All instructions for the EV4 processor (21064, 20164A, 21066, and 21068 chips) and the EV5 processor (the 21164 chips that house the EV5 processor).

None of these instructions requires emulation on any Alpha processor.
ev56 All instructions for the EV56 processor (the 21164 chips that house the EV56 processor).

These are the instructions supported by the EV4 processor, as well as the instructions in the byte/word extension (BWX).

Applications compiled with this model might incur emulation overhead on EV4 and EV5 processors.
pca56 All instructions for the PCA56 processor (21164PC chips).

These are the instructions supported by the EV4 processor, as well as the instructions in the byte/word extension (BWX) and the multimedia extension (MAX).

Applications compiled with this model might incur emulation overhead on EV4, EV5, and EV56 processors.

Note This directive is for use only by compilers.


.file Directive

Syntax

.file file_number file_name_string

Description

The .file directive specifies the source file corresponding to the assembly instructions following the directive. This directive causes the assembler to stop generating line numbers that are used by the debugger. A subsequent .loc directive causes the assembler to resume generating line numbers.

Note This directive is for use only by compilers.


.livereg Directive

Syntax

.livereg int_bitmask fp_bitmask

Description

The .livereg directive affects the next jump instruction even if it is not the successive instruction. By default, external br instructions and jmp instructions are treated as external calls; that is, all registers are assumed to be live. The .livereg directive cannot appear before an external br instruction because it will affect the next ret, jsr, bsr, jmp, or call_pal instruction instead of the br instruction.

Note This directive is for use only by compilers.


Data Storage Directives

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.loc Directive

Syntax

.loc file_number line_number

Description

The .loc directive specifies the source file and the line within it that corresponds to the assembly instructions that follow. The assembler ignores the file number when this directive appears in the assembly source file. Then, the assembler assumes that the directive refers to the most recent .file directive.

Note This directive is for use only by compilers.


.tune Directive

Syntax

.tune option

Description

The .tune directive identifies the processor-specific instruction tuning algorithm that the Assembler is to use, based on the setting of the .arch directive and the processor on which the generated code will run.

The valid values for option are as follows:

Option | Instructions to generate
generic All instructions that are hard-wired into every Alpha processor.

This is the option that the Assembler assumes if you omit the .tune directive.
host | All instructions directly supported by the Alpha processor on which the Assembler is running.
ev4,ev5 All instructions for the EV4 processor (21064, 20164A, 21066, and 21068 chips) and the EV5 processor (the 21164 chips that house the EV5 processor).

None of these instructions require emulation on any Alpha processor.
ev56 All instructions for the EV56 processor (the 21164 chips that house the EV56 processor).

These are the instructions supported by the EV4 processor, as well as the instructions in the byte/word extension (BWX).

Applications compiled with this model might incur emulation overhead on EV4 and EV5 processors.
pca56 All instructions for the PCA56 processor (21164PC chips).

These are the instructions supported by the EV4 processor, as well as the instructions in the byte/word extension (BWX) or the multimedia extension (MAX).

Applications compiled with this model might incur emulation overhead on EV4, EV5, and EV56 processors.

Note The .tune directive is for use only by compilers.


.ascii Directive

Syntax

.ascii string [, string] ...

Description

The .ascii directive assembles each string from the list into successive locations. The .ascii directive does not pad the string with null characters. You must put quotation marks (") around each string. You can optionally use the backslash escape characters.


.asciiz Directive

Syntax

.asciiz string [, string]

Description

The .asciiz directive assembles each string in the list into successive locations and adds a null character. You can optionally use the backslash escape characters.


.byte Directive

Syntax

.byte expression1 [, expression2] ... [, expressionN]

Description

The .byte directive truncates the expression values specified in the comma-separated list to 8-bit values and assembles the values in successive locations. The expression values must be absolute.

The operands in a .byte directive can optionally have the form expressionVal [ :expressionRep].

The expressionVal is an 8-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.


.comm Directive

Syntax

.comm name, expression

Description

The .comm directive causes name (unless defined elsewhere) to become a global common symbol at the head of a block of at least expression bytes of storage. The linker overlays like-named common blocks, using the expression value of the largest block as the byte size of the overlay.


.d_floating Directive

Syntax

.d_floating expression1 [, expression2] ... [,expressionN]

Description

The .d_floating directive initializes memory to double-precision (64-bit) VAX D_ floating numbers. The expression values must be absolute.

The operands can optionally have the form expressionVal [ : expressionRep ]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and any preceding labels to a double-word boundary. You can disable this feature with the .align 0 directive.


.double Directive

Syntax

.double expression1 [, expression2] ... [, expressionN]

Description

The .double directive is a synonym for .t_floating .


.float Directive

Syntax

.float expression1 [, expression2] ... [, expressionN]

Description

The .float directive is a synonym for .s_floating .


.f_floating Directive

Syntax

.f_floating expression1 [, expression2] ... [, expressionN]

Description

The .f_floating directive initializes memory to single-precision (32-bit) VAX F_floating numbers. The expression values must be absolute.

The operands can optionally have the form expressionVal [ :expressionRep]

The expressionVal is a 32-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a longword boundary. You can disable this feature by using the .align 0 directive.


.g_floating Directive

Syntax

.g_floating expression1 [, expression2] ... [, expressionN]

Description

The .g_floating directive initializes memory to double-precision (64-bit) VAX G_ floating numbers. The expression values must be absolute.

The operands can optionally have the form expressionVal [ :expressionRep]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count ( expressionRep) must be absolute. This directive automatically aligns its data and any preceding labels to a quadword boundary. You can disable this feature with the .align 0 directive.


.lcomm Directive

Syntax

.lcomm name, expression

Description

The .lcomm directive gives the named symbol (name) a data type of bss. The assembler allocates the named symbol to the bss area, and the expression defines the named symbol's length. If a .globl directive also specifies name, the assembler allocates the named symbol to external bss.


.long Directive

Syntax

.long expression1 [, expression2] ... [, expressionN]

Description

The .long directive truncates the expression values specified in the comma-separated list to 32-bit values and assembles the values in successive locations. The expression values can be relocatable.

The operands can optionally have the form expressionVal [ :expressionRep]

The expressionVal is a 32-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a longword boundary. You can disable this feature with the .align 0 directive.


.quad Directive

Syntax

.quad expression1 [,expression2] ... [, expressionN]

Description

The .quad directive truncates the expression values specified in the comma-separated list to 64-bit values and assembles the values in successive locations. The expression values can be relocatable.

The operands can optionally have the form expressionVal [ :expressionRep]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a quadword boundary. You can disable this feature with the .align 0 directive.


.s_floating Directive

Syntax

.s_floating expression1 [, expression2] ... [, expressionN]

Description

The .s_floating directive initializes memory to single-precision (32-bit) IEEE floating-point numbers. The expression values must be absolute.

The operands for the .s_floating directive can optionally have the form expressionVal [ :expressionRep]

The expressionVal is a 32-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a longword boundary. This feature can be disabled with the .align 0 directive.


.t_floating Directive

Syntax

.t_floating expression1 [, expression2] ... [, expressionN]

Description

The .t_floating directive initializes memory to double-precision (64-bit) IEEE floating-point numbers. The expression values must be absolute.

The operands can optionally have the form expressionVal [ :expressionRep]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and any preceding labels to a quadword boundary. This feature can be disabled with the .align 0 directive.


.word Directive

Syntax

.word expression1 [, expression2] ... [, expressionN]

Description

The .word directive truncates the expression values specified in the comma-separated list to 16-bit values and assembles the values in successive locations. The expression values must be absolute. The operands in the .word directive can optionally have the form expressionVal [ :expressionRep]

The expressionVal is a 16-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels on a word boundary. This feature can be disabled with the .align 0 directive.


Location Control Directives

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.align Directive

Syntax

.align expression

Description

The .align directive sets low-order bits in the location counter to zero. The value of expression establishes the number of bits to be zeroed. The maximum value for expression is 6 (64-byte alignment). Windows NT default alignment is .align 4 (octaword alignment).

If the .align directive advances the location counter, the assembler fills the skipped bytes with zeros in data sections or nop instructions in text sections.

Normally, the following directives automatically allign their data appropriately: .word, .long, .quad, .float, .double, .d_floating, .f_floating, .g_floating, .s_floating, and .t_floating. For example, .word does an implicit .align 1, and .double does an implicit .align 3.

The automatic alignment feature can be disabled with .align 0. The assembler reinstates automatic alignment at the next .text, .data, .rdata, or .sdata directive that it encounters.

Labels immediately preceding an automatic or explicit alignment are also realigned. For example:

foo: .align 3
.word 0

is the same as

.align 3
foo: .word 0


.data Directive

Syntax

.data expression

Description

The .data directive directs the assembler to add all subsequent data to the .data section, named with the expression provided.


.rdata Directive

Syntax

.rdata expression

Description

The .rdata directive instructs the assembler to add subsequent data into the .rdata section, named with the expression provided.


.sdata Directive

Syntax

.sdata expression

Description

The .sdata directive instructs the assembler to add subsequent data to the .sdata section, named with the expression provided.


.space Directive

Syntax

.space expression

Description

The .space directive advances the location counter by the number of bytes specified by the value of expression. The assembler fills the space with zeros.


.text Directive

Syntax

.text expression

Description

The .text directive instructs the assembler to add subsequent code to the .text section, named with the expression provided. (This is the default.)

The assembler allows a non-text directive to occur within the scope of a procedure. The use of the .text directive following the non-text instructions causes the assembler to reset its context to the procedure. The Alpha assembler does produce a warning in this case. This feature has been retained in the Alpha assembler to support code generated by the acc compiler.


.tls$ Directive

Syntax

.tls$ expression

Note Support for the .tls$ directive is a feature that may not be available on all versions of the Alpha assembler.

Description

The .tls$ directive instructs the assembler to add subsequent code to the .tls$ section, named with the expression provided. Symbols defined in the .tls$ section (thread local storage) are local to the currently executing thread and are equivalent to variables defined in the C language as __declspec(thread).

To access a symbol in thread local storage, it is necessary to obtain access to the Thread Environment Block (TEB). A pointer to the TLS array is located at offset 0x2c from the TEB. The tls index (_tls_index) is multiplied by 4 and added to the address of the TLS array to obtain the address of the thread’s TLS data area. Refer to the example that illustrates how to obtain this value.


Thread Local Storage Example

#include <ksalpha.h>               #For definition of
                                 #rdteb PAL call
   .extern _tls_index             #Need to reference
                                 #this.
   .extern (thread) extern_tls_var   #Declare a symbol
                                 #in tls defined
                                 #elsewhere
   .tls$
local_tls_var:
   .long 0
   .globl dotls                  #Export dotls
   .ent dotls                     #Set entry point
   .text
dotls:
   lda $sp, -16($sp)               #Adjust stack for
                                 #$ra guard
   stq $ra, 0($sp)                #Store $ra.
   .prologue 1
                                 #Begin Load address
                                 #of TlsArray
   ldl $1, _tls_index            #Generates normally
                                 #relocated code
   call_pal rdteb                  #Get address of tls
                                 #into register $0
   ldl $0, 0x2c($0)               #Load address of
                                 #TlsArray
   s4addl $1, $0, $0               #Apply the index
   ldl $0, 0($0)                   #TLSArray[TlsIndex]
                                 #END of TLS Array
                                 #section
   ldl $1, extern_tls_var($0)    #Get contents of
                                 #extern_tls_var in
                                 #T0
   stl $1, local_tls_var($0)      #T0 stored into
                                 #Local_tls_var
                                 #Secrel relocation
                                 #applied
   ldq $ra, 0($sp)               #Restore $ra and
                                 #$sp
   lda $sp, 16($sp)
   ret $ra
   .end dotls


Symbol Declaration Directives

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.extern Directive

Syntax

.extern name

.extern (thread) name

Description

The .extern directive indicates that the specified symbol is global and external; that is, the symbol is defined in another object module and cannot be defined until link time. The name operand is a global undefined symbol. Symbols declared as thread are declared to reside in the .tls$ (thread local storage) section. Please refer to the .tls$ directive description for an example of how to use symbols in thread local storage.

Note This directive must be used prior to the first reference of name.


.globl Directive

Syntax

.globl name

Description

The .globl directive identifies name as an external symbol. If the name is otherwise defined (for example, by its appearance as a label), the assembler exports the symbol; otherwise, it imports the symbol. In general, the assembler imports undefined symbols; that is, it gives them the storage class "global undefined" and requires the linker to resolve them.

Note This directive must be used prior to the first reference of name.


.struct Directive

Syntax

.struct expression

Description

The .struct directive permits you to lay out a structure using labels plus directives such as .word or .byte. It ends at the next segment directive (.data, .text, and so forth). It does not emit any code or data, but defines the labels within it to have values that are the sum of expression plus their offsets from the .struct itself.


(symbolic equate) Directive

Syntax

name = expression

name = register

Description

The symbolic equate directive takes one of the following forms:

name = expression

name = register

You must define name only once in the assembly, and you cannot redefine name. The expression value must be computable when you assemble the program, and expression must involve only operators, constants, or equated symbols. The name value can be used as a constant in any later statement.


.weakref Directive

Syntax

.weakref name[, refname]

Description

The .weakref directive indicates that symbol name is a weak reference for the global symbol refname. If referenced at link time, the symbol name resolves to the symbol refname. Within a user module, a different symbol may preempt name. Otherwise, if name is not used, the linkage editor does not place it in the symbol table and does not issue unresolved symbol warnings for it.

The assembler treats the global symbol refname the same as a symbol declared in either a .extern or globl directive. The symbol refname may be defined in the same module as the .weakref directive or in a different module. The attached example indicates how a run-time library developer would use the .weakref directive to allow an application developer to define a function of the same name without conflicting with symbols of the same name in the libraries.


.weakref Example

The following example makes three weak references to a C language library function called _A_Internal_function and shows how two user modules implement the weak references.

In the library:

_A_Internal_function()
<{>
...................
<}>
.weakref Intfunc1, _A_Internal_function
.weakref Intfunc2, _A_Internal_function
.weakref Intfunc3, _A_Internal_function

In user module 1:

jsr IntFunc1       #__A_Internal_function is called
                  #here
jsr IntFunc2         #IntFunc2 is called.
.end

In user module 2:

.globl IntFunc2
IntFunc2:          #IntFunc2 preempts the weak
                  #reference.
.......
.end


Routine Entry Point Definition Directives

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.aent Directive

Syntax

.aent name

Description

The .aent directive sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. This directive must appear between a pair of .ent and .end directives.


.ent Directive

Syntax

.ent proc_name

Description

The .ent directive sets the beginning of the procedure proc_name. Use this directive when you want to generate information for the debugger. The .end directive sets the end of a procedure.


Repeat Block Directives

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.endr Directive

Syntax

.endr

Description

The .endr directive signals the end of a repeat block. The .repeat directive starts a repeat block.


.repeat Directive

Syntax

.repeat expression

Description

The .repeat directive repeats all instructions or data between the .repeat and .endr directives. The expression value defines how many times the enclosing text and data repeats.

You can take advantage of macro substitution in the .repeat/.endr block by using the %r token in the expression. For example:

.repeat 3
.globl aglob%r
.endr

This expands to:

.globl aglob1
.globl aglob2
.globl aglob3


Procedure Attribute Directives

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.edata Directive

Syntax

.edata flag [ [data] lang-handler ]

Description

The .edata directive marks data related to exception handling.

If flag is 0, the assembler moves the data following the directive to the .xdata section.

If flag is 1, the assembler creates a function table entry for the next .ent directive. The function table entry contains the language-specific handler and data. If data is not specified, the data field in the procedure descriptor is set to zeros.


.eflag Directive

Syntax

.eflag flags

Description

The .eflag directive encodes exception-related flags to be stored in the PDSC_ RPD_FLAGS field of the procedure's run-time procedure descriptor. Refer to the /Qapd xx and /eflag Command Options. Also refer to the Windows NT for Alpha Calling Standard.


.end Directive

Syntax

.end [proc_name]

Description

The .end directive sets the end of a procedure. The .ent directive sets the beginning of a procedure. Use the .ent and .end directives when you want to generate information for the debugger.


.fmask Directive

Syntax

.fmask mask offset

Description

The .fmask directive sets a mask with a bit turned on for each floating-point register that the current routine saved. The least-significant bit corresponds to register $f0. The offset is the distance in bytes from the virtual frame pointer to where the floating-point registers are saved.

You must use .ent before .fmask, and you can use only one .fmask for each .ent. Space should be allocated for those registers specified in the .fmask.


.frame Directive

Syntax

.frame frame-register frame-size return_pc-register [local_offset]

Description

The .frame directive describes a stack frame. The first register contains values for the frame-register and frame-size. The frame-size parameter is the number of bytes between the frame register and the virtual frame pointer. The second register specifies the register that contains the return address. The local_offset parameter, which is for use only by compilers, specifies the number of bytes between the virtual frame pointer and the local variables.

You must use .ent before .frame, and you can use only one .frame for each .ent. No stack traces can be done in the debugger without the .frame directive.


.prologue Directive

Syntax

.prologue flag

Description

The .prologue directive marks the end of the prologue section of a procedure. The .prologue directive is also used by the instruction scheduling optimization. The scheduler will not move instructions across the boundary set up by the .prologue directive.

A flag of 0 indicates that the procedure does not use $gp; the caller does not need to set up $pv prior to calling the procedure or restore $gp on return from the procedure.

A flag of 1 indicates that the procedure does use $gp; the caller must set up $pv prior to calling the procedure and restore $gp on return from the procedure.

On Windows NT, the flag value is ignored and the behavior is as if the flag value were 0.


.save_ra Directive

Syntax

.save_ra saved_ra_register

Description

The .save_ra directive specifies that saved_ra_register is the register in which the return address is saved during the execution of the procedure. If .save_ra is not used, the saved return address register is assumed to be the same as the return_ pc_register argument of the .frame directive. The .save_ra directive is valid only for register frame procedures.


Version Control Directive

Version Control Directive (.verstamp)

Syntax

.verstamp major minor

Description

The .verstamp directive specifies the major and minor version numbers (for example, version 0.15 would be .verstamp 0 15).


.set Directive

Assembler Option Directive (.set)

Syntax

.set option

Description

The .set directive instructs the assembler to enable or disable certain options. The assembler has the following default options: reorder, macro, move, novolatile, and at. Only one option can be specified for each .set directive:

  • The reorder option permits the assembler to reorder machine language instructions to improve performance.

  • The noreorder option prevents the assembler from reordering machine language instructions. If a machine language instruction violates the hardware pipeline constraints, the assembler issues a warning message.

  • The macro option permits the assembler to generate multiple machine instructions from a single assembler instruction. This is the default action.

  • The nomacro option causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. You must select the noreorder option before using the nomacro option; otherwise, an error results.

  • The at option permits the assembler to use the $at register for macros, but generates warnings if the source program uses $at .

  • When you use the noat option and an assembler operation requires the $at register, the assembler issues a warning message; however, the noat option does permit source programs to use $at without warnings being issued.

  • The nomove options instructs the assembler to mark each subsequent instruction so that it cannot be moved during reorganization. The assembler can still move instructions from below the nomove region to above the region or vice versa. The nomove option has part of the effect of the "volatile" C declaration; it prevents otherwise independent loads or stores from occurring in a different order than intended.

  • The move option cancels the effect of nomove.

  • The volatile option instructs the assembler that subsequent load and store instructions may not be moved in relation to each other or removed by redundant load removal or other optimization. The volatile option is less restrictive than noreorder; it allows the assembler to move other instructions (that is, instructions other than load and store instructions) without restrictions.

  • The novolatile option cancels the effect of the volatile option.


.split Directive

Syntax

.split proc_name

Description

The proc_name value refers to the procedure name of the associated mainline procedure. The proc_name value must have been the subject of a previous .ent directive. The .split directive differs from the .aent directive in that it is part of the referenced procedure. The segment defined by the .split directive does not need to be adjacent to the procedure referenced by proc_name.

For example:

     .globl fubar
     .ent   fubar
fubar:
     lda $sp, -16($sp)
     stq $26, 0($sp)
     .prologue
     br around
     .end fubar  # end of initial main procedure
along:
     .long      x
     < more data - possibly even another procedure>
     .split fubar  # Continuation of fubar procedure
around:
      ldq $26, 0($sp)
      lda $sp, 16($sp)
      ret
      .end fubar        #end of fubar procedure