Copyright: Copyright (c) 1995 Digital Equipment Corporation
Citation: Copyright (c) 1995 Digital Equipment Corporation


Assembler Directives

Assembler directives are instructions to the assembler to perform various bookkeeping tasks, storage reservation, and other control functions. To distinguish them from other instructions, directive names begin with a period.

The assembler directives fall into the following categories:

•	Compiler-Use-Only Directives

•	Data Storage Directives

•	Location Control Directives

•	Symbol Declaration Directives

•	Routine Entry Point Definition Directives

•	Repeat Block Directives

•	Assembler Option Directive(.set)

•	Procedure Attribute Directives

•	Version Control Directive


.file Directive

Syntax

.file	file_number file_name_string
Description

The .file directive specifies the source file corresponding to the assembly instructions following the directive. This directive causes the assembler to stop generating line numbers that are used by the debugger. A subsequent .loc directive causes the assembler to resume generating line numbers.

Note: This directive is for use only by compilers.


.livereg Directive

Syntax

.livereg	int_bitmask fp_bitmask
Description

The .livereg directive affects the next jump instruction even if it is not the successive instruction. By default, external br instructions and jmp instructions are treated as external calls; that is; all registers are assumed to be live. The .livereg directive cannot appear before an external br instruction because it will affect the next ret, jsr, bsr, jmp, or call_pal instruction instead of the br instruction.

Note: This directive is for use only by compilers.


.loc Directive

Syntax

.loc	file_number line_number
Description

The .loc directive specifies the source file and the line within it that corresponds to the assembly instructions that follow. The assembler ignores the file number when this directive appears in the assembly source file. Then, the assembler assumes that the directive refers to the most recent .file directive.

Note: This directive is for use only by compilers.


.ascii Directive

Syntax

.ascii	string [ , string ] ...
Description

The .ascii directive assembles each string from the list into successive locations. The .ascii directive does not pad the string with null characters. You must put quotation marks (") around each string. You can optionally use the backslash escape characters.


.asciiz Directive

Syntax

.asciiz	string [ , string ]
Description

The .asciiz directive assembles each string in the list into successive locations and adds a null character. You can optionally use the backslash escape characters.


.byte Directive

Syntax

.byte	expression1 [ , expression2 ] ... [ , expressionN ]
Description

The .byte directive truncates the values of the expressions specified in the comma-separated list to 8-bit values and assembles the values in successive locations. The values of the expressions must be absolute. The operands in a .byte directive can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is an 8-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.


.comm Directive

Syntax

.comm	name, expression
Description

The .comm directive causes name (unless defined elsewhere) to become a global common symbol at the head of a block of at least expression bytes of storage. The linker overlays like-named common blocks, using the expression value of the largest block as the byte size of the overlay.


.d_floating Directive

Syntax

.d_floating	expression1 [, expression2 ] ... [ ,expressionN]
Description

The .d_floating directive initializes memory to double precision (64-bit) VAX D_ floating numbers. The values of the expressions must be absolute.

The operands can optionally have the form:

expressionVal [ : expressionRep ]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and any preceding labels to a double-word boundary. You can disable this feature with the .align 0 directive .


.double Directive

Syntax

.double	expression1 [, expression2] ... [, expressionN]
The .double directive is a synonym for .t_floating.


.float Directive

Syntax

.float	expression1 [, expression2] ... [, expressionN]
The .float directive is a synonym for .s_floating.


.f_floating Directive

Syntax

.f_floating	expression1 [, expression2] ... [, expressionN]
Description

The .f_floating directive initializes memory to single precision (32-bit) VAX F_floating numbers. The values of the expressions must be absolute.

The operands can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is a 32-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a longword boundary. You can disable this feature by using the .align 0 directive.


.g_floating Directive

Syntax

.g_floating	expression1 [, expression2] ... [, expressionN]
Description

The .g_floating directive initializes memory to double precision (64-bit) VAX G_ floating numbers. The values of the expressions must be absolute.

The operands can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count ( expressionRep) must be absolute. This directive automatically aligns its data and any preceding labels to a quadword boundary. You can disable this feature with the .align 0 directive.


.lcomm Directive

Syntax

.lcomm	name, expression
Description

The .lcomm directive gives the named symbol (name) a data type of bss. The assembler allocates the named symbol to the bss area, and the expression defines the named symbol's length. If a .globl directive also specifies name, the assembler allocates the named symbol to external bss.


.long Directive

Syntax

.long	expression1 [, expression2] ... [, expressionN]
Description

The .long directive truncates the values of the expressions specified in the comma-separated list to 32-bit values and assembles the values in successive locations. The values of the expression can be relocatable.

The operands can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is a 32-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a longword boundary. You can disable this feature with the .align 0 directive.


.quad Directive

Syntax

.quad	expression1 [,expression2] ... [, expressionN]
Description

The .quad directive truncates the values of the expressions specified in the comma-separated list to 64-bit values and assembles the values in successive locations. The values of the expressions can be relocatable.

The operands can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a quadword boundary. You can disable this feature with the .align 0 directive.


.s_floating Directive

Syntax

.s_floating	expression1 [, expression2] ... [, expressionN]
Description

The .s_floating directive initializes memory to single precision (32-bit) IEEE floating-point numbers. The values of the expressions must be absolute.

The operands for the .s_floating directive can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is a 32-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels to a longword boundary. This feature can be disabled with the .align 0 directive.


.t_floating Directive

Syntax

.t_floating	expression1 [, expression2] ... [, expressionN]
Description

The .t_floating directive initializes memory to double precision (64-bit) IEEE floating-point numbers. The values of the expressions must be absolute.

The operands can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is a 64-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and any preceding labels to a quadword boundary. This feature can be disabled with the .align 0 directive.


.word Directive

Syntax

.word	expression1 [, expression2] ... [, expressionN]
Description

The .word directive truncates the values of the expressions specified in the comma-separated list to 16-bit values and assembles the values in successive locations. The values of the expressions must be absolute. The operands in the .word directive can optionally have the form:

expressionVal [ :expressionRep]

The expressionVal is a 16-bit value. The optional expressionRep is a non-negative expression that specifies how many times to replicate the value of expressionVal. The expression value (expressionVal) and repetition count (expressionRep) must be absolute.

This directive automatically aligns its data and preceding labels on a word boundary. This feature can be disabled with the .align 0 directive.


.align Directive

Syntax

.align	expression
Description

The .align directive sets low-order bits in the location counter to zero. The value of expression establishes the number of bits to be zeroed. The maximum value for expression is 6 (64 byte alignment). Windows NT default alignment is .align 4 (octaword alignment).

If the .align directive advances the location counter, the assembler fills the skipped bytes with zeros in data sections or nop instructions in text sections.

Normally, the .word, .long, .quad, .float, .double, .d_floating, .f_floating, .g_floating, .s_floating, and .t_floating directives automatically align their data appropriately. For example, .word does an implicit .align 1, and .double does an implicit .align 3.

The automatic alignment feature can be disabled with .align 0. The assembler reinstates automatic alignment at the next .text, .data, .rdata, or .sdata directive that it encounters.

Labels immediately preceding an automatic or explicit alignment are also realigned. For example:

foo: .align 3
.word 0

is the same as

.align 3
foo: .word 0


.data Directive

Syntax

.data

Description

The .data directive directs the assembler to add all subsequent data to the .data section.


.rdata Directive

Syntax

.rdata

Description

The .rdata directive instructs the assembler to add subsequent data into the .rdata section.


.sdata Directive

Syntax

.sdata

Description

The .sdata directive instructs the assembler to add subsequent data to the .sdata section.


.space Directive

Syntax

.space	expression
Description

The .space directive advances the location counter by the number of bytes specified by the value of expression. The assembler fills the space with zeros.


.text Directive

Syntax

.text

Description

The .text directive instructs the assembler to add subsequent code to the .text section. (This is the default.)


.tls$ Directive

Syntax

.tls$

NOTE:	Support for the .tls$ Directive is a feature which may not be available on all versions of the asaxp assembler.

Description

The .tls$ directive instructs the assembler to add subsequent code to the .tls$ section. Symbols defined in the .tls$ section (thread local storage) are local to the currently executing thread and are equivalent to variables defined in the C language as __declspec(thread).

To access a symbol in thread local storage, it is necessary to obtain access to the Thread Environment Block (TEB). A pointer to the TLS array is located at offset 0x2c from the TEB. The tls index (_tls_index) is multiplied by 4 and added to the address of the TLS array to obtain the address of the thread’s TLS data area. Refer to the example which illustrates how to obtain this value


Thread Local Storage Example

#include <ksalpha.h>	# For definition of rdteb PAL call

.extern _tls_index 	# need to reference this.

.extern (thread) extern_tls_var	# declare a symbol in tls defined elsewhere

.tls$

local_tls_var:

.long 0

.globl dotls	# export dotls

.ent dotls	# set entry point

.text

dotls:

lda $sp, -16($sp)	#adjust stack for $ra guard

stq $ra, 0($sp) 	#Store $ra.

.prologue 1

# Begin Load address of TlsArray

ldl $1, _tls_index	# generates normally relocated code

call_pal rdteb	# Get address of tls into register $0

ldl $0, 0x2c($0)	# Load address of TlsArray

s4addl $1, $0, $0	# Apply the index

ldl $0, 0($0) 	# TLSArray[TlsIndex]

# END of TLS Array section

ldl $1, extern_tls_var($0) 	# Get contents of

# extern_tls_var in T0

stl $1, local_tls_var($0)	# T0 stored into local_tls_var

# secrel relocation applied

ldq $ra, 0($sp)	# Restore $ra and $sp

lda $sp, 16($sp)

ret $ra

.end dotls


.extern Directive

Syntax

.extern	name
.extern(thread)	name
Description

The .extern directive indicates that the specified symbol is global and external; that is, the symbol is defined in another object module and cannot be defined until link time. The name operand is a global undefined symbol. Symbols declared as (thread) are declared to reside in the .tls$ (thread local storage) section. Please refer to the .tls$ Directive  description for an example of how to use symbols in thread local storage.

NOTE: This directive must be used prior to the first reference of name.


.globl Directive

Syntax

.globl	name
Description

The .globl directive identifies name as an external symbol. If the name is otherwise defined (for example, by its appearance as a label), the assembler exports the symbol; otherwise, it imports the symbol. In general, the assembler imports undefined symbols; that is, it gives them the storage class "global undefined" and requires the linker to resolve them.

NOTE: This directive must be used prior to the first reference of name.


.struct Directive

Syntax

.struct	expression
Description

The .struct directive permits you to lay out a structure using labels plus directives such as .word or .byte. It ends at the next segment directive (.data, .text, and so forth). It does not emit any code or data, but defines the labels within it to have values that are the sum of expression plus their offsets from the .struct itself.


(symbolic equate) Directive

Syntax

(symbolic equate)

Description

The (symbolic equate) directive takes one of the following forms:

name = expression

name = register

You must define name only once in the assembly, and you cannot redefine name. The expression must be computable when you assemble the program, and the expression must involve only operators, constants, or equated symbols. name can be used as a constant in any later statement.


.weakref Directive

Syntax

.weakref	name[, refname]
Description

Indicates that symbol name is a weak reference for the global symbol refname. If referenced at link time, the symbol name resolves to the symbol refname. Within a user module, a different symbol may preempt name. Otherwise, if name is not used, the linkage editor does not place it in the symbol table and does not issue unresolved symbol warnings for it.

The assembler treats the global symbol refname the same as a symbol declared in either a .extern or .globl directive. The symbol refname may be defined in the same module as the .weakref directive or in a different module. The attached example indicates how a run time library developer would use the .weakref Directive to allow an application developer to define a function of the same name without conflicting with symbols of the same name in the libraries.


.weakref Example

The following example makes three weak references to a C language library function called _A_Internal_function and shows how two user modules implement the weak references.

In the library:

_A_Internal_function()

<{>

...................

<}>

.weakref Intfunc1, _A_Internal_function

.weakref Intfunc2, _A_Internal_function

.weakref Intfunc3, _A_Internal_function

In user module 1:

jsr IntFunc1 # __A_Internal_function is called here

jsr IntFunc2 # IntFunc2 is called.

.end

In user module 2:

.globl IntFunc2

IntFunc2: # IntFunc2 preempts the weak reference.

.......

.end


.aent Directive

Syntax

.aent	name
Description

The .aent directive sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. This directive must appear between a pair of .ent and .end directives.


.ent Directive

Syntax

.ent	proc_name
Description

The .ent directive sets the beginning of the procedure proc_name. Use this directive when you want to generate information for the debugger. The .end directive sets the end of a procedure.


.endr Directive

Syntax

.endr

Description

The .endr directive signals the end of a repeat block. The .repeat directive starts a repeat block.


.repeat Directive

Syntax

.repeat	expression
Description

The .repeat directive repeats all instructions or data between the .repeat and .endr directives. The expression defines how many times the enclosing text and data repeats.


Assembler Option Directive

There is one assembler option directive.

.set Directive

Syntax

.set	option
Description

The .set directive instructs the assembler to enable or disable certain options. The assembler has the following default options: reorder, macro, move, novolatile, and at. Only one option can be specified for each .set directive:

•	The reorder option permits the assembler to reorder machine language instructions to improve performance.

•	The noreorder option prevents the assembler from reordering machine language instructions. If a machine language instruction violates the hardware pipeline constraints, the assembler issues a warning message.

•	The macro option permits the assembler to generate multiple machine instructions from a single assembler instruction. This is the default action.

•	The nomacro option causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. You must select the noreorder option before using the nomacro option; otherwise, an error results.

•	The at option permits the assembler to use the $at register for macros, but generates warnings if the source program uses $at .

•	When you use the noat option and an assembler operation requires the $at register, the assembler issues a warning message; however, the noat option does permit source programs to use $at without warnings being issued.

•	The nomove options instructs the assembler to mark each subsequent instruction so that it cannot be moved during reorganization. The assembler can still move instructions from below the nomove region to above the region or vice versa. The nomove option has part of the effect of the "volatile" C declaration; it prevents otherwise independent loads or stores from occurring in a different order than intended.

•	The move option cancels the effect of nomove.

•	The volatile option instructs the assembler that subsequent load and store instructions may not be moved in relation to each other or removed by redundant load removal or other optimization. The volatile option is less restrictive than noreorder; it allows the assembler to move other instructions (that is, instructions other than load and store instructions) without restrictions.

•	The novolatile option cancels the effect of the volatile option.


.edata Directive

Syntax

.edata	flag [ [data] lang-handler ]
Description

The .edata directive marks data related to exception handling.

If flag is 0, the assembler moves the data following the directive to the .xdata section.

If flag is 1, the assembler creates a function table entry for the next .ent directive. The function table entry contains the language-specific handler and data. If the data is not specified the data field in the procedure descriptor is set to zeros.


.eflag Directive

Syntax

.eflag	flags
Description

The .eflag directive encodes exception-related flags to be stored in the PDSC_ RPD_FLAGS field of the procedure's run-time procedure descriptor. Refer to the /Qapdxx and /eflag Command Options. Also refer to the Windows NT for Alpha AXP Calling Standard


.end Directive

Syntax

.end	[proc_name]
Description

The .end directive sets the end of a procedure. The .ent directive sets the beginning of a procedure. Use the .ent and .end directives when you want to generate information for the debugger.


.fmask Directive

Syntax

.fmask	mask offset
Description

The .fmask directive sets a mask with a bit turned on for each floating-point register that the current routine saved. The least-significant bit corresponds to register $f0. The offset is the distance in bytes from the virtual frame pointer to where the floating-point registers are saved.

You must use .ent before .fmask, and you can use only one .fmask for each .ent. Space should be allocated for those registers specified in the .fmask.


.frame Directive

Syntax

.frame	frame-register frame-size return_pc-register [local_ offset]
Description

The .frame directive describes a stack frame. The first register is the frame register, frame-size is the size of the stack frame, that is, the number of bytes between the frame register and the virtual frame pointer. The second register specifies the register that contains the return address. The local_offset parameter, which is for use only by compilers, specifies the number of bytes between the virtual frame pointer and the local variables.

You must use .ent before .frame, and you can use only one .frame for each .ent. No stack traces can be done in the debugger without the .frame directive.


.prologue Directive

Syntax

.prologue	flag
Description

The .prologue directive marks the end of the prologue section of a procedure. The .prologue directive is also used by the instruction scheduling optimization. The scheduler will not move instructions across the boundary set up by the .prologue directive.

A flag of 0 indicates that the procedure does not use $gp; The caller does not need to set up $pv prior to calling the procedure or restore $gp on return from the procedure.

A flag of 1 indicates that the procedure does use $gp; the caller must set up $pv prior to calling the procedure and restore $gp on return from the procedure.

On Windows NT, the flag value is ignored, and the behavior is if the flag value were 0.


.save_ra Directive

Syntax

.save_ra	saved_ra_register
Description

The .save_ra directive specifies that saved_ra_register is the register in which the return address is saved during the execution of the procedure. If .save_ra is not used, the saved return address register is assumed to be the same as the return_ pc_register argument of the .frame directive. The .save_ra directive is valid only for register frame procedures.


Version Control Directive

There is one version control directive.

.verstamp Directive

Syntax

.verstamp	major minor
Description

The .verstamp directive specifies the major and minor version numbers (for example, version 0.15 would be .verstamp 0 15).


Introduction and Release Information

The Windows NT Software Development Kit (SDK) includes the Windows NT Assembler for Alpha. This assembler converts assembly language statements into Alpha machine code. In most assembly languages, each instruction corresponds to a single machine instruction. some instructions in this assembly language can, however, generate several machine instructions. This feature results in assembly programs that can run without modification on future machines that might have different machine instructions.

The assembler is intended primarily for producing object modules from the assembly instructions generated by some high-level language compilers. Because of its limited purpose, the assembler lacks many functions normally present in full featured products.


Intended Users

The Windows NT Assembler for Alpha is provided for experienced assembly language programmers who need to:

•	Maximize the efficiency of a routine, for example, in a low level I/O driver, which might not be possible in another high-level language such as C, Fortran-77, or Pascal.

•	Access machine functions unavailable from high-level languages or satisfy special constraints such as restricted register usage


Associated Documents

This assembler help occasionally refers to the following publication for further information about the Alpha architecture:

Alpha AXP Architecture Reference Manual
Edited by Richard L. Sites
Digital Press
1992

You can obtain this publication by calling Digital and ordering part number EY-L520E-DP

The assembler help also refers to the following document which is included with Microsoft Visual C+4.0 for Digital Alpha Systems.

Windows NT Calling Standard for Digital Alpha Systems.


Typographic Conventions

This assembler Help file uses the following typographic conventions:

Convention	Description
variable	Italic text indicates variable values and instruction operands.
instruction	Monospaced text indicates an instruction or other literal text used in the assembly source file.
$	The dollar sign ($) is the first character in a register name.
As applicable, the following types of information are provided for each instruction or assembly directive listed:

Section	Description
Syntax	This section shows the mnemonic and operands for each instruction or assembly directive. If an instruction accepts more than one string of operands, the Syntax section contains a separate line for each operand string. For example: divf $s_reg1, $s_reg2, $d_reg divf $d_reg/$s_reg1, $s_reg2
Description	This section describes the function of the instruction or assembly directive, what it does with the given operands, and any side effects. The instruction descriptions also include one of the following hotspots, whichever is appropriate, to provide quick access to operand descriptions:
	Main Instruction Operand Descriptions
	Floating-Point Instruction Operand Descriptions
Qualifiers	This section appears only in floating-point instruction descriptions. Many floating-point instructions accept one or more appended letters that specify particular rounding and trapping modes. See Divide F_floating (divf) for an example of a Qualifiers section. See Also: Floating-Point Instruction Qualifiers for descriptions of the rounding and trapping mode qualifiers.


Copyright Notice and Disclaimers

The information in this Windows NT Assembler for Alpha online Help is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this information.

No responsibility is assumed for the use or reliability of the software on equipment that is not supplied by Digital Equipment Corporation or its affiliated companies.

Copyright Digital Equipment Corporation 1995.

All Rights Reserved.

Portions of this information are Copyright 1990 MIPS Computer Systems, Inc.

The following are trademarks of Digital Equipment Corporation: Digital, DEC, AlphaStation, AlphaServer, and the DIGITAL logo.

Windows, and Windows NT are registered trademarks of Microsoft Corporation.

All other trademarks and registered trademarks are the property of their respective holders.


asaxp Command Line Syntax

To assemble your programs, use the asaxp command.

Note:	The cl.exe program must be installed in order for the asaxp preprocessor to work.

The asaxp command line uses the following syntax:

asaxp [option...] filename

where]

option	is one or more asaxp options, as defined in asaxp Command Options.
filename	is the name of the assembly source file. The command assumes that a .i filename extension means that the source has already been preprocessed.


asaxp Command Options

The asaxp command options are as follows:

Option	Description
/? /help	Display help text.
/nologo	Suppress the display of the sign-on banner.
/nopp	Do not invoke the C language preprocessor on the input file.
/Dsymbol	Define constants and macros (1)
/Dsymbol=string
/Usymbol	Undefine constants and macros (1)
/Zd	Emit line numbers and public symbols for debugging.
/Zi	Emit CodeView(tm) symbolic information for windbg
/I	Specify path for include files (1)
/Fo filename /o filename	Specify an output filename other than the default. The default is the base name of the source file with the extension .obj.
/O0	Turn off code scheduling optimization
/O1	Turn on code scheduling optimization (default).
/resumption_safe	Prevent the scheduler from moving floating point operating instructions. This should be used when using IEEE mode instructions with exception handling.
/symbols_aligned_0mod4	Symbols are longword granular (default).
/symbols_not_aligned	No attempt is made to align symbols.
/stack_aligned_0mod8	Align stack on a quadword boundary(default)
/stack_not_aligned	No attempt is made to align stack.
/eflag flags	Encode the exception-related flags to be stored in the PDSC_RPD_FLAGS field of the procedures run-time procedure descriptor. This is equivalent to the .eflag directive except that it is for the entire module. (2)
/QApdst	Set the exception-related flags to EXCEPTION_MODE_SILENT(default) (2)
/QApdsg	Set the exception-related flags to EXCEPTION_MODE_SIGNAL (2)
/QApdsa	Set the exception-related flags to EXCEPTION_MODE_SIGNAL_ALL (2)
/QApdie	Set the exception-related flags to EXCEPTION_MODE_IEEE (2). This should be used if the user desires IEEE behavior when making RTL calls from assembler.
/QApdca	Set the exception-related flags to EXCEPTION_MODE_CALLER (2). This should be used if the user is writing an RTL which should behave according to the user’s exception mode.
(1) For further information, see the descriptions of the /D and /I options for the cl command in the section Using CL in the Microsoft Win32 SDK Tools User's Guide.

(2) For further information, refer to the Windows NT for Alpha AXP Calling Standard.


Preprocessing

The cl compiler is used to preprocess assembly sources. This compiler's preprocessor expands macros into source that is lexically compatible with the asaxp assembler. You can also use preprocessor directives for conditional assembly and for including other files.

Note:	File names with the extension .i are assumed to have been preprocessed.

See Also

See the Microsoft C/C+Language Help for information about using the preprocessor.


Alpha Registers General Notes

Alpha systems have the following types of registers:

•	Integer Registers

•	Floating-Point Registers

You must use integer and floating point registers appropriately according to the type of register expected in the assembly instructions. If you confuse the two, the assembler issues an error message.

The assembler reserves all register names. All register names start with a dollar sign ($), and all alphabetic characters in register names are lowercase.


Integer Registers

Alpha systems have 32 integer registers. Each register is 64 bits wide. In other system architectures, integer registers are sometimes referred to as general registers.

The integer registers have the names $0 to $31.

Note: 	You must include the leading dollar sign ($) whenever you specify a register.

Integer register $31 always contains the value 0. All other integer registers can be used interchangeably, except for integer register $30, which is assumed to be the stack pointer (certain PALcode assumes that $30 is the stack pointer).

The following table describes the Alpha integer registers:

Register Name	Alternate Name	Use
$0	$v0	Used for expression evaluations and to hold the integer function results. Not preserved across procedure calls.
$1-8	$t0-$t7	Temporary registers used for expression evaluations. Not preserved across procedure calls.
$9-14	$s0-$s5	Saved registers. Preserved across procedure calls.
$15	$s6 or $fp	Contains the frame pointer (if needed); otherwise, a saved register.
$16-21	$a0-$a5	Used to pass the first six integer type actual arguments. Not preserved across procedure calls.
$22-25	$t8-$t11	Temporary registers used for expression evaluations. Not preserved across procedure calls.
$26	$ra	Contains the return address. Preserved across procedure calls.
$27	$pv or $t12	Contains the procedure value and used for expression evaluation. Not preserved across procedure calls.
$28 or $at	$at	Reserved for the assembler. Not preserved across procedure calls.
$29 or $gp	$gp	Contains the global pointer for compiler-generated code. Not preserved across procedure calls. Note: Register $gp should not be altered. For more information, refer to the Windows NT for Alpha AXP Calling Standard.
$30 or $sp	$sp	Contains the stack pointer. Preserved across procedure calls.
$31	$zero	Always has the value 0.


Floating-Point Registers

Alpha systems have 32 floating-point registers. Each register 64 bits wide. Each register can hold one 32-bit single-precision value, or one 64-bit double-precision value.

The floating-point registers have the names $f0 to $f31.

Note: 	You must include the leading dollar sign ($) whenever you specify a register.

Floating-point register $f31 always contains the value 0.0. All other floating-point registers can be used interchangeably.

The floating-point register assignments are as follows:

Register Name	Use
$f0	Used to hold floating-point type function results. In a standard call that returns a complex floating point result, this register is used to return the real part of the result.
$f1	Used to hold floating-point type function results. In a standard call that returns a complex floating point result, this register is used to return the imaginary part of the result.
$f2-$f9	Saved registers. Preserved across procedure calls.
$f10-$f15	Temporary registers used for expression evaluation. Not preserved across procedure calls.
$f16-$f21	Used to pass the first six single- or double-precision actual arguments. Not preserved across procedure calls.
$f22-$f30	Temporary registers used for expression evaluations. Not preserved across procedure calls.
$f31	Always has the value 0.0.


Alpha Addressing General Notes

This topic describes the byte-addressing schemes for load and store instructions used in aligned data operations and unaligned data operations.

See also:

Atomic Updates


Atomic Updates(lock flags)

Alpha includes 2 per-processor registers associated with the load locked and store conditional instructions noted below. These instructions together provide for the atomic update of an aligned quadword or aligned longword. Refer to the Alpha AXP Architecture Reference Manual for further information.

The code sequence, below illustrates atomic updates. This load-locked/store-conditional paradigm may be used whenever an atomic update of a shared aligned quadword is desired, including getting the effect of atomic bytes writes.

try_again:

ldq_l	R1, a_quadword	#Load and set flag
<modify register R1>
stq_c	R1, a_quadword
beq	R1, no_store
:
:

no_store:

<code to check for excessive iterations>
br	try_again


Aligned Data Operations

All Alpha systems use the following byte-addressing scheme for aligned data:

•	Access to words requires alignment on byte boundaries that are evenly divisible by 2.

•	Access to longwords requires alignment on byte boundaries that are evenly divisible by 4.

•	Access to quadwords requires alignment on byte boundaries that are evenly divisible by 8.

Any attempt to address a data item that does not have the proper alignment may cause an alignment exception.

Aligned data operations include:

•	Load Quadword (ldq)

•	Store Quadword (stq)

•	Load Sign Extended Longword (ldl)

•	Store Longword (stl)

•	Load Word (ldw)

•	Store Word (stw)


Unaligned Data Operations

The assembler's unaligned load and store instructions operate on arbitrary byte boundaries. They all generate multiple machine-code instructions. They do not raise alignment exceptions.

Unaligned data operations include:

•	Unaligned Load Quadword (uldq)

•	Unaligned Store Quadword (ustq)

•	Unaligned Load Longword (uldl)

•	Unaligned Store Longword (ustl)

•	Unaligned Load Word (uldw)

•	Unaligned Store Word (ustw)

•	Unaligned Load Word Unsigned (uldwu)

•	Load Byte (ldb)

•	Store Byte (stb)

•	Load Byte Unsigned (ldbu)

•	Store Quadword Conditional (stq_c)

•	Store Longword Conditional (stl_c)

•	Load Sign Extended Longword Locked (ldl_l)

•	Load Quadword Locked (ldq_l)


Blank and Tab Characters

You can use blank and tab characters anywhere between operators, identifiers, and constants. Adjacent identifiers or constants that are not otherwise separated must be separated by a blank or tab.

These characters can also be used within character constants; however, they are not allowed within operators and identifiers.


Comments

The number sign character ( # ) introduces a line comment. Comments that start with a number sign extend through the end of the line on which they appear. You can also use C and C+language notation ( /*...*/ or // ) to delimit comments.

Notes:	Do not start a comment with a number sign in column one.
Comments beginning with the number sign character ( # ) are not allowed in header files.


Identifiers

An identifier consists of a case-sensitive sequence of alphanumeric characters (A-Z, a-z, 0-9), and the following special characters:

•	. (period)

•	_ (underscore)

•	$ (dollar sign)

•	@ (at sign)

•	? (question mark)

Identifiers can be up to 31 characters long, and the first character cannot be numeric (0-9).

If an identifier is not defined to the assembler (only referenced), the assembler assumes that the identifier is an external symbol. The assembler treats the identifier like a name specified by an .extern directive.

If the identifier is defined to the assembler and the identifier has not been specified as global, the assembler assumes that the identifier is a local symbol.


Backslash Conventions

The C backslash conventions and their meanings are as follows:

Convention	Meaning
\a	Alert (0x07)
\b	Backspace (0x08)
\f	Form feed (0x0c)
\n	Newline (0x0a)
\r	Carriage return (0x0d)
\t	Horizontal tab (0x09)
\v	Vertical feed (0x0b)
\\	Backslash (0x5c)
\"	Quotation mark (0x22)
\'	Single quote (0x27)
\nnn	Character whose octal value is nnn (where n is 0-7)
\Xnn	Character whose hexadecimal value is nn (where n is 0-9, a-f, or A-F)


Scalar Constants

The assembler interprets all scalar constants as twos complement numbers. Scalar constants can be any of the digits 0123456789abcdefABCDEF.

Scalar constants can be one of the following constants:

•	Decimal constants. These consist of a sequence of decimal digits (0-9) without a leading zero.

•	Hexadecimal constants. These consist of the characters 0x (or 0X) followed by a sequence of hexadecimal digits

•	Octal constants. These consist of a leading zero followed by a sequence of octal digits (0-7).


Floating-Point Constants

Floating-point constants can appear only in floating-point directives and in the floating-point load immediate instructions. Floating-point constants have the following format:

+/-d1[d2][e|E+/-d3]

d1	is written as a decimal integer and denotes the integral part of the floating-point value.
d2	is written as a decimal integer and denotes the fractional part of the floating-point value.
d3	is written as a decimal integer and denotes a power of 10.
The "+'' symbol is optional.

For example, the number .02173 can be represented as follows:

21.73E-3

The floating-point directives (such as .float and .double) may optionally use hexadecimal floating-point constants instead of decimal constants. A hexadecimal floating-point constant consists of the following elements:

[+/-]0x[1/0]<hex-digits>h0x<hex-digits>

The assembler places the first set of hexadecimal digits (excluding the 0 or 1 preceding the decimal point) in the mantissa field of the floating-point format without attempting to normalize it. It stores the second set of hexadecimal digits in the exponent field without biasing them. If the mantissa appears to be denormalized, it checks to determine whether the exponent is appropriate. Hexadecimal floating-point constants are useful for generating IEEE special symbols and for writing hardware diagnostics.

For example, either of the following directives generates the single-precision number 1.0:

.float 1.0e+0
.float 0x1.0h0x7f

The assembler uses normal (nearest) rounding mode to convert floating-point constants.


String Constants

All characters except the newline character are allowed in string constants. String constants begin and end with double quotation marks (").

The assembler observes most of the backslash conventions used by the C language. Click on Backslash Conventions for a list of the conventions and their meanings.

Deviations from C conventions are as follows:

•	The assembler does not recognize "?".

•	The assembler does not recognize the prefix "L" (wide character constant).

•	The assembler limits hexadecimal character constants to two characters.

•	The assembler allows the leading "x" character in hexadecimal constants to be either uppercase or lowercase; that is, both \xnn and \Xnn are allowed.

For octal notation, the backslash conventions require three characters when the next character could be confused with the octal number.

For hexadecimal notation, the backslash conventions require two characters when the next character could be confused with the hexadecimal number (that is, use a 0 for the first character of a single-character hexadecimal number).


Multiple Lines per Physical Line

You can include multiple statements on the same line by separating the statements with semicolons.

Note:	The assembler does not recognize semicolons as separators when they follow comment symbols #, // or /*.


Statements

Each statement consists of an optional label, an operation code, and one or more operands.


Label Definitions

A label definition consists of an identifier followed by a colon. Label definitions assign the current value and type of the location counter to the name. An error results when the name is already defined.

Label definitions always end with a colon. You can put a label definition on a line by itself.

A generated label is a single numeric value (1-255). To reference a generated label, put an f (forward) or a b (backward) immediately after the digit. The reference tells the assembler to look for the nearest generated label that corresponds to the specified number in the lexically forward or backward direction.


Null Statements

A null statement is an empty statement that the assembler ignores. Null statements can have label definitions. For example, the following line has three null statements in it:

label: ; ;


Keyword Statements

A keyword statement begins with a predefined keyword. The syntax for the rest of the statement depends on the keyword. Keywords are either assembler instructions (mnemonics) or directives.


Expressions

An expression is a sequence of symbols that represents a value. Each expression and its result have data types. The assembler does arithmetic in twos complement integers with 64 bits of precision. Expressions follow precedence rules and consist of the following elements:

•	Operators

•	Identifiers

•	Constants

You can also use a single character string in place of an integer within an expression. For example, the following two pairs of statements are equivalent:

.byte "a" ; .word "a"+0x19

.byte 0x61 ; .word 0x7a


Expression Operators

The assembler supports the following expression operators:

Operator	Meaning
+	Addition
-	Subtraction
*	Multiplication
/	Division
%	Remainder
<<	Shift left
>>	Shift right (sign is not extended)
^	Bitwise EXCLUSIVE OR
&	Bitwise AND
I	Bitwise OR
-	Minus (unary)
+	Identity (unary)
~	Complement


Expression Operator Precedence Rules

The assembler supports the following expression operator precedence rules:

Precedence	Operators
Least binding, lowest precedence	Binary +, -
.
.	Binary *, /, %, <<, >>, ^, &, |
.
Most binding, highest precedence	Unary -, +, ~
Note:	The assembler's precedence scheme differs from that of the C language.


base-register

Specifies an indexed address, which assumes a zero offset. The base register's contents specify the address.


expression

Specifies an absolute address.


expression (base-register)

Specifies a based address. To get the address, the value of the expression is added to the contents of the base register. The assembler generates the most locally efficient code for referencing the value at the specified address.


relocatable-symbol

Specifies a relocatable address. The assembler generates the necessary instructions to address the item and generates relocation information for the linker.


relocatable-symbol+/-expression

Specifies a relocatable address. To get the address, the value of the expression, which has an absolute value, is added to or subtracted from the relocatable symbol. The assembler generates the necessary instructions to address the item and generates relocation information for the linker. If the symbol name does not appear as a label anywhere in the assembly, the assembler assumes that the symbol is external.


relocatable-symbol (index-register)

Specifies an indexed relocatable address. To get the address, the index register is added to the relocatable symbol's address. The assembler generates the necessary instructions to address the item and generates relocation information for the linker. If the symbol name does not appear as a label anywhere in the assembly, the assembler assumes that the symbol is external.


relocatable-symbol+/-expression (index-register)

Specifies an indexed relocatable address. To get the address, the assembler adds or subtracts the relocatable symbol, the expression, and the contents of the index register. The assembler generates the necessary instructions to address the item and generates relocation information for the linker. If the symbol name does not appear as a label anywhere in the assembly, the assembler assumes that the symbol is external.


Using Floating Point Operations
Using Floating-Point Operations

This following topics contain useful information you should be familiar with before using floating-point instructions:

•	NaN Values

•	Floating-Point Data Types

•	Floating-Point Control Register

•	Floating-Point Exceptions

•	Floating-Point Instruction Qualifiers


Floating-Point Instruction Operand Descriptions

A floating-point instruction takes one or more of the following operands:

Specifier	Operand Description
address	A symbolic expression whose effective value is used as an address.
$d_reg	Destination register. A floating-point register that receives a value as a result of an operation.
$d_reg/$s_reg	One floating-point register that is used as both a source register and a destination register.
label	A label that identifies a location in a program.
$s_reg, $s_reg1, $s_reg2	Source registers. Floating-point registers whose contents are to be used in an operation.
val_expr	An expression whose value is a floating-point constant.


NaN Values

The term NaN, which stands for Not a Number, means a symbolic entity that represents a value not otherwise available in floating-point format.

There are two kinds of NaNs:

•	Quiet NaNs represent unknown or uninitialized values.

•	Signaling NaNs represent symbolic values and values that are too big or too precise for the format. Signaling NaNs raise an invalid operation exception whenever an operation is attempted on them.


Floating Point Data Types
Floating-Point Data Types

Floating-point instructions operate on the following data types:

•	S_floating (IEEE single precision)

•	T_floating (IEEE double precision)

•	Longword integer and quadword integer

•	F_floating (VAX single precision)

•	D_floating (VAX double precision, limited support)

•	G_floating (VAX double precision)


S_Floating Data Format

The format for the S_floating data type is as follows:

S_floating Format


T_Floating Data Format

The format for the T_floating data type is as follows:

T_floating Format


F_Floating Data Format

The format for the F_floating data type is as follows:

F_floating Format


D_Floating Data Format

The format for the D_floating data type is as follows:

D_floating Format


G_Floating Data Format

The format for the G_floating data type is as follows:

G_floating Format


Floating Point Control Register
Floating-Point Control Register

The floating-point control register (FPCR) contains status and control information. It controls the arithmetic rounding mode of instructions that specify dynamic rounding (d qualifier), and gives a summary for each exception type of the exception conditions detected by the floating-point instructions. It also contains an overall summary bit indicating whether an exception occurred.

The format of the floating-point control register is as follows:

The fields of the floating-point control register have the following definitions:

Bits	Name	Description
63	sum	Summary: records the bitwise OR of the FPCR exception bits (bits 57 to 52).
62-60	raz/ign	Read-As-Zero: ignored when written.
59-58	dyn	Dynamic Rounding Mode: indicates the current rounding mode to be used by an IEEE floating-point instruction that specifies dynamic mode ( d qualifier). The bit as follows:
		00 Chopped rounding mode.
		01 Minus infinity.
		10 Normal rounding.
		11 Plus infinity.
57	iov	Integer overflow.
56	ine	Inexact result.
55	unf	Underflow.
54	ovf	Overflow.
53	dze	Division by zero.
52	inv	Invalid operation.
51-0	raz/ign	Read-As-Zero: ignored when written.


Floating Point Exceptions
Floating-Point Exceptions

Six exception conditions can result from the use of floating-point instructions. All of the exceptions are signaled by an arithmetic exception trap. These exceptions include:

•	Invalid Operation. An invalid operation exception is signaled if any operand of a floating-point instruction, other than cmpt xx, is nonfinite (cmpt xx operates normally with plus and minus infinity). This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

•	Division by Zero. A division by zero exception is taken if the numerator does not cause an invalid operation trap and the denominator is zero. This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

•	Overflow. An overflow exception is signaled if the rounded result exceeds, in magnitude, the largest finite number of the destination format. This trap is always enabled. If this trap occurs, an unpredictable value is stored in the destination register.

•	Underflow. An underflow exception occurs if the rounded result is smaller, in magnitude, than the smallest finite number of the destination format. This trap may be enabled with the v instruction qualifier. If this trap occurs, a true zero is always stored in the destination register.

•	Inexact Result. An inexact result exception occurs if the infinitely precise result differs from the rounded result. This trap is disabled by default, and may be enabled. If this trap occurs, the normal rounded result is still stored in the destination register.

•	Integer Overflow. An integer overflow exception occurs if the conversion from a floating-point or integer format to an integer format results in a value that is outside of the range of values representable by the destination format. This trap is disabled by default, and may be enabled. If this trap occurs, the true result is truncated to the number of bits in the destination format and stored in the destination register.


Floating Point Instruction Qualifiers
Floating-Point Instruction Qualifiers

Many of the floating-point instructions accept a qualifier that specifies rounding and trapping modes.

NOTE:	The qualifier syntax used by ASAXP deviates slightly from The Alpha AXP Architecture Manual.


Rounding Mode Qualifiers

Appending one or more letters to a floating-point instruction determines the VAX or IEEE rounding mode to be used.

VAX Rounding Mode Qualifiers

The following table shows the qualifiers used to specify VAX rounding modes:

Mode	Qualifier
Normal rounding	None
Chopped	c
IEEE Rounding Mode Qualifiers

The following table shows the qualifiers used to specify IEEE rounding modes:

Mode	Qualifiers
Normal rounding	None
Plus infinity	d (ensure that the dyn field of the FPCR is 11)
Minus infinity	m
Chopped	c


VAX Trapping Modes

VAX Trapping Mode Qualifiers

The following table shows the qualifiers used to specify VAX trapping modes:

Mode	Qualifier
Imprecise, underflow disabled	None
Imprecise, underflow enabled	u
Software, underflow disabled	s
Software, underflow enabled	su
VAX Convert-to-Integer Trapping Modes

The following table shows the qualifiers used to specify VAX convert-to-integer trapping modes:

Mode	Qualifier
Imprecise, integer overflow disabled	None
Imprecise, integer overflow enabled	v
Software, integer overflow disabled	s
Software, integer overflow_enabled	sv


IEEE Trapping Modes

IEEE Trapping Modes

The following table shows the qualifiers used to specify IEEE trapping modes:

Mode	Qualifier
Imprecise, underflow disabled, inexact disabled	None
Imprecise, underflow enabled, inexact disabled	u
Software, underflow enabled, inexact disabled	su
Software, underflow enabled, inexact_enabled	sui
IEEE Convert-to-Integer Trapping Modes

The following table shows the qualifiers used to specify IEEE convert-to-integer trapping modes:

Mode	Qualifier
Imprecise, integer overflow disabled, inexact disabled	None
Imprecise, integer overflow enabled, inexact disabled	v
Software, integer overflow enabled, inexact disabled	sv
Software, integer overflow enabled, inexact enabled	svi


Load F_floating (ldf)

Syntax

ldf	$d_reg, address
Description

Load F_floating loads four bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load G_floating (Load D_floating) (ldg)

Syntax

ldg	$d_reg, address
Description

Load G_floating (Load D_floating) loads eight bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load S_floating (Load Longword) (lds)

Syntax

lds	$d_reg, address
Description

Load S_floating (Load Longword) loads four bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load T_floating (Load Quadword) (ldt)

Syntax

ldt	$d_reg, address
Description

Load T_floating (Load Quadword) loads eight bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load Immediate F_floating (ldif)

Syntax

ldif	$d_reg, val_expr
Description

Load Immediate F_floating loads four bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load Immediate D_floating (ldid)

Syntax

ldid	$d_reg, val_expr
Description

Load Immediate D_floating loads eight bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load Immediate G_floating (ldig)

Syntax

ldig	$d_reg, val_expr
Description

Load Immediate G_floating loads eight bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Load Immediate S_floating (Load Longword) (ldis)

Syntax

ldis	$d_reg, val_expr
Description

Load Immediate S_floating (Load Longword) loads four bytes from the specified effective address into the destination register. The address must be longword aligned for 4-byte load instructions.


Load Immediate T_floating (Load Quadword) (ldit)

Syntax

ldit	$d_reg, val_expr
Description

Load Immediate T_floating (Load Quadword) loads eight bytes from the specified effective address into the destination register. The address must be quadword aligned for 8-byte load instructions.


Store F_floating (stf)

Syntax

stf	$s_reg,address
Description

Store F_floating stores four bytes the source floating- point register into the specified effective address. The address must be longword aligned for 4-byte store instructions.


Store G_floating (Store D_floating) (stg)

Syntax

stg	$s_reg, address
Description

Store G_floating (Store D_floating) stores eight bytes from the source floating-point register into the specified effective address. The address must be quadword aligned for 8-byte store instructions.


Store S_floating (Store Longword) (sts)

Syntax

sts	$s_reg, address
Description

Store S_floating (Store Longword) stores four bytes from the source floating-point register into the specified effective address. The address must be longword aligned for 4-byte store instructions.


Store T_floating (Store Quadword) (stt)

Syntax

stt	$s_reg, address
Description

Store T_floating (Store Quadword) stores eight bytes from the source floating-point register into the specified effective address. The address must be quadword aligned for 8-byte store instructions.


Floating Clear Instruction

There is one floating clear instruction.

Floating Clear (fclr)

Syntax

fclr	$d_reg
Description

Floating Clear places zero in the destination register.


Floating Absolute Value Instruction

There is one floating absolute value instruction.

Floating Absolute Value (fabs)

Syntax

fabs	$s_reg, $d_reg
fabs	$d_reg/$s_reg
Description

Floating Absolute Value computes the absolute value of the contents of the source register and places the floating-point result in the destination register.


Negate F_floating (negf)

Syntax

negf	$s_reg, $d_reg
negf	$d_reg/$s_reg
Description

Negate F_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negf instruction:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding
	VAX Trap Mode: Imprecise, underflow disabled
negfs	VAX Trap Mode: Software, underflow disabled
	VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled


Negate G_floating (negg)

Syntax

negg	$s_reg, $d_reg
negg	$d_reg/$s_reg
Description

Negate G_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negg instruction:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding
	VAX Trap Mode: Imprecise, underflow disabled
neggs	VAX Trap Mode: Software, underflow disabled
	VAX Convert-to-Integer Trap Mode Software, integer overflow disabled


Negate S_floating (negs)

Syntax

negs	$s_reg, $d_reg
negs	$d_reg/$s_reg
Description

Negate S_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negs instruction:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
negssu	IEEE Trap Mode: Software, underflow enabled, inexact disabled


Negate T_floating (negt)

Syntax

negt	$s_reg, $d_reg
negt	$d_reg/$s_reg
Description

Negate T_floating computes the negative value of the contents of $s_reg or $d_reg and places the specified precision floating-point result in $d_reg.

Qualifiers

The following table describes the qualifiers for the negt instruction:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
negtsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled


Add F_floating (addf)

Syntax

addf	$s_reg1, $s_reg2, $d_reg
addf	$d_reg/$s_reg1, $s_reg2
Description

Add F_floating adds the contents of $s_reg or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly zero, the sum has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the addf instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
addfc	VAX Rounding Mode: Chopped.
addfu	VAX Trap Mode: Imprecise, underflow enabled.
addfuc	Combined meanings of addfc and addfu.
addfs	VAX Trap Mode: Software, underflow disabled.
addfsc	Combined meanings of addfs and addfc.
addfsu	VAX Trap Mode: Software, underflow enabled.
addfsuc	Combined_meanings of addfs and addfuc.


Add G_floating (addg)

Syntax

addg	$s_reg1, $s_reg2, $d_reg
addg	$d_reg/$s_reg1, $s_reg2
Description

Add G_floating adds the contents of $s_reg or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly zero, the sum has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the addg instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
addgc	VAX Rounding Mode: Chopped.
addgu	VAX Trap Mode: Imprecise, underflow enabled.
addguc	Combined meanings of addgc and addgu.
addgs	VAX Trap Mode: Software, underflow disabled.
addgsc	Combined meanings of addgs and addgc.
addgsu	VAX Trap Mode: Software, underflow enabled.
addgsuc	Combined meanings of addgs and addguc.


Add S_floating (adds)

Syntax

adds	$s_reg1, $s_reg2, $d_reg
adds	$d_reg/$s_reg1, $s_reg2
Description

Add S_floating adds the contents of $s_reg or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly zero, the sum has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the adds instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
addsc	IEEE Rounding Mode: Chopped.
addsm	IEEE Rounding Mode: Minus infinity.
addsd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
addsu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
addsuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
addsum	Combined meanings of addsu and addsm.
addsud	Combined meanings of addsu and addsd.
addssu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
addssuc	Combined meanings of addss, addsu, and addsc.
addssum	Combined meanings of addss, addsu, and addsm.
addssud	Combined meanings of addss, addsu, and addsd.
addssui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
addssuic	Combined meanings of addssui and addsc.
addssuim	Combined meanings of addssui and addsm.


Add T_floating (addt)

Syntax

addt	$s_reg1, $s_reg2, $d_reg
addt	$d_reg/$s_reg1, $s_reg2
Description

Add T_floating adds the contents of $s_reg or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly zero, the sum has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the sum has a negative sign.

Qualifiers

The following table describes the qualifiers for the addt instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
addtc	IEEE Rounding Mode: Chopped.
addtm	IEEE Rounding Mode: Minus infinity.
addtd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
addtu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
addtuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
addtum	Combined meanings of addtu and addtm.
addtud	Combined meanings of addtu and addtd.
addtsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
addtsuc	Combined meanings of addts, addtu, and addtc.
addtsum	Combined meanings of addts, addtu, and addtm.
addtsud	Combined meanings of addts, addtu, and addtd.
addtsui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
addtsuic	Combined meanings of addtsui and addtc.
addtsuim	Combined meanings of addtsui and addtm.


Divide F_floating (divf)

Syntax

divf	$s_reg1, $s_reg2, $d_reg
divf	$d_reg/$s_reg1, $s_reg2
Description

Divide F_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and places the result in $d_reg. If the divisor is a zero, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divf instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
divfc	VAX Rounding Mode: Chopped.
divfu	VAX Trap Mode: Imprecise, underflow enabled.
divfuc	VAX Trap Mode: Underflow enabled.
	VAX Rounding Mode: Chopped.
divfs	VAX Trap Mode: Software, underflow disabled.
divfsc	Combined meanings of divfs and divfc.
divfsu	VAX Trap Mode: Software, underflow enabled.
divfsuc	Combined meanings of divfs, divfu, and divfc.


Divide G_floating (divg)

Syntax

divg	$s_reg1, $s_reg2, $d_reg
divg	$d_reg/$s_reg1, $s_reg2
Description

Divide F_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and places the result in $d_reg. If the divisor is a zero, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divg instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
divgc	VAX Rounding Mode: Chopped.
divgu	VAX Trap Mode: Imprecise, underflow enabled.
divguc	VAX Trap Mode: Underflow enabled.
	VAX Rounding Mode: Chopped.
divgs	VAX Trap Mode: Software, underflow disabled.
divgsc	Combined meanings of divgs and divgc.
divgsu	VAX Trap Mode: Software, underflow enabled.
divgsuc	Combined meanings of divgs, divgu, and divgc.


Divide S_floating (divs)

Syntax

divs	$s_reg1, $s_reg2, $d_reg
divs	$d_reg/$s_reg1, $s_reg2
Description

Divide S_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and places the result in $d_reg. If the divisor is a zero, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divs instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
divsc	IEEE Rounding Mode: Chopped.
divsm	IEEE Rounding Mode: Minus infinity.
divsd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
divsu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
divsuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
divsum	Combined meanings of divsu and divsm.
divsud	Combined meanings of divsu and divsd.
divssu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
divssuc	Combined meanings of divss, divsu, and divsc.
divssum	Combined meanings of divss, divsu, and divsm.
divssud	Combined meanings of divss, divsu, and divsd.
divssu	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
divssuic	Combined meanings of divssui and divsc.
divssuim	Combined meanings of divssui and divsm.


Divide T_floating (divt)

Syntax

divt	$s_reg1, $s_reg2, $d_reg
divt	$d_reg/$s_reg1, $s_reg2
Description

Divide T_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and places the result in $d_reg. If the divisor is a zero, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divt instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
divtc	IEEE Rounding Mode: Chopped.
divtm	IEEE Rounding Mode: Minus infinity.
divtd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
divtu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
divtuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
divtum	Combined meanings of divtu and divtm.
divtud	Combined meanings of divtu and divtd.
divtsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
divtsuc	Combined meanings of divts, divtu, and divtc.
divtsum	Combined meanings of divts, divtu, and divtm.
divtsud	Combined meanings of divts, divtu, and addtd.
divtsui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
divtsuic	Combined meanings of divtsui and divtc.
divtsuim	Combined meanings of divtsui and divtm.


Multiply F_floating (mulf)

Syntax

mulf	$s_reg1, $s_reg2, $d_reg
mulf	$d_reg/$s_reg1, $s_reg2
Description

Multiply F_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode. The single-precision operation on canonical single-precision values produces a canonical single-precision result.

Qualifiers

The following table describes the qualifiers for the mulf instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
mulfc	VAX Rounding Mode: Chopped.
mulfu	VAX Trap Mode: Imprecise, underflow enabled.
mulfuc	Combined meanings of mulfc and mulfu.
mulf	VAX Trap Mode: Software, underflow disabled.
mulfsc	Combined meanings of mulfs and mulfc.
mulfsu	VAX Trap Mode: Software, underflow enabled.
mulfsuc	Combined meanings of mulfs and mulfuc.


Multiply G_floating (mulg)

Syntax

mulg	$s_reg1, $s_reg2, $d_reg
mulg	$d_reg/$s_reg1, $s_reg2
Description

Multiply G_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode.

Qualifiers

The following table describes the qualifiers for the mulg instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
mulgc	VAX Rounding Mode: Chopped.
mulgu	VAX Trap Mode: Imprecise, underflow enabled.
mulguc	Combined meanings of mulgc and mulgu.
mulgs	VAX Trap Mode: Software, underflow disabled.
mulgsc	Combined meanings of mulgs and mulgc.
mulgsu	VAX Trap Mode: Software, underflow enabled.
mulgsuc	Combined meanings of mulgs and mulguc.


Multiply S_floating (muls)

Syntax

muls	$s_reg1, $s_reg2, $d_reg
muls	$d_reg/$s_reg1, $s_reg2
Description

Multiply S_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode. The single-precision operation on canonical single-precision values produces a canonical single- precision result.

Qualifiers

The following table describes the qualifiers for the muls instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
mulsc	IEEE Rounding Mode: Chopped.
mulsm	IEEE Rounding Mode: Minus infinity.
mulsd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
mulsu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
mulsuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
mulsum	Combined meanings of mulsu and mulsm.
mulsud	Combined meanings of mulsu and mulsd.
mulssu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
mulssuc	Combined meanings of mulss, mulsu, and mulsc.
mulssum	Combined meanings of mulss, mulsu, and mulsm.
mulssud	Combined meanings of mulss, mulsu, and mulsd.
mulssui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
mulssuic	Combined meanings of mulssui and mulsc.
mulssuim	Combined meanings of mulssui and mulsm.


Multiply T_floating (mult)

Syntax

mult	$s_reg1, $s_reg2, $d_reg
mult	$d_reg/$s_reg1, $s_reg2
Description

Multiply T_floating multiplies the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and stores the results in $d_reg. The product is rounded according to the appropriate rounding mode.

Qualifiers

The following table describes the qualifiers for the mult instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
multc	IEEE Rounding Mode: Chopped.
multm	IEEE Rounding Mode: Minus infinity.
multd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
multu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
multuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
multum	Combined meanings of multu and multm.
multud	Combined meanings of multu and multd.
multsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
multsuc	Combined meanings of mults, multu, and multc.
multsum	Combined meanings of mults, multu, and multm.
multsud	Combined meanings of mults, multsu, and multd.
multsui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
multsuic	Combined meanings of multsui and multc.
multsuim	Combined meanings of multsui and multm.


Subtract F_floating (subf)

Syntax

subf	$s_reg1, $s_reg2, $d_reg
subf	$d_reg/$s_reg1, $s_reg2
Description

Subtract F_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly zero, the difference has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subf instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
subfc	VAX Rounding Mode: Chopped.
subfu	VAX Trap Mode: Imprecise, underflow enabled.
subfuc	Combined meanings of subfc and subfu.
subfs	VAX Trap Mode: Software, underflow disabled.
subfsc	Combined meanings of subfs and subfc.
subfsu	VAX Trap Mode: Software, underflow enabled.
subfsuc	Combined meanings of subfs and subfuc.


Subtract G_floating (subg)

Syntax

subg	$s_reg1, $s_reg2, $d_reg
subg	$d_reg/$s_reg1, $s_reg2
Description

Subtract G_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly zero, the difference has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subg instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
subgc	VAX Rounding Mode: Chopped.
subgu	VAX Trap Mode: Imprecise, underflow enabled.
subguc	Combined meanings of subgc and subgu.
subgs	VAX Trap Mode: Software, underflow disabled.
subgsc	Combined meanings of subgs and subgc.
subgsu	VAX Trap Mode: Software, underflow enabled.
subgsuc	Combined meanings of subgs and subguc.


Subtract S_floating (subs)

Syntax

subs	$s_reg1, $s_reg2, $d_reg
subs	$d_reg/$s_reg1, $s_reg2
Description

Subtract S_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly zero, the difference has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subs instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
subsc	IEEE Rounding Mode: Chopped.
subsm	IEEE Rounding Mode: Minus infinity.
subsd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
subsu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
subsuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
subsum	Combined meanings of subsu and subsm.
subsud	Combined meanings of subsu and subsd.
subssu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
subssuc	Combined meanings of subss, subsu, and subsc.
subssum	Combined meanings of subss, subsu, and subsm.
subssud	Combined meanings of subss, subsu, and subsd.
subssui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
subssuic	Combined meanings of subssui and subsc.
subssuim	Combined meanings of subssui and subsm.


Subtract T_floating (subt)

Syntax

subt	$s_reg1, $s_reg2, $d_reg
subt	$d_reg/$s_reg1, $s_reg2
Description

Subtract T_floating subtracts the contents of $s_reg2 from the contents of $s_reg1 or $d_reg and places the result into $d_reg. When the difference of the two operands is exactly zero, the difference has a positive sign for all rounding modes except round toward minus infinity (-). For that rounding mode, the difference has a negative sign.

Qualifiers

The following table describes the qualifiers for the subt instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
subtc	IEEE Rounding Mode: Chopped.
subtm	IEEE Rounding Mode: Minus infinity.
subtd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
subtu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
subtuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
subtum	Combined meanings of subtu and subtm.
subtud	Combined meanings of subtu and subtd.
subtsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
subtsuc	Combined meanings of subts, subtu, and subtc.
subtsum	Combined meanings of subts, subtu, and subtm.
subtsud	Combined meanings of subts, subtu, and subtd.
subtsui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
subtsuic	Combined meanings of subtsui and subtc.
subtsuim	Combined meanings of subtsui and subtm.


Convert Quadword to Longword (cvtql)

Syntax

cvtql	$s_reg, $d_reg
cvtql	$d_reg/$s_reg
Description

Convert Quadword to Longword converts the quadword integer contents of $s_reg to the longword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtql instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cvtqlv	IEEE Convert-to-Integer Trap Mode: Imprecise, integer overflow enabled, inexact disabled.
cvtqlsv	IEEE Convert-to-Integer Trap Mode: Software, integer overflow enabled, inexact disabled.


Convert Longword to Quadword (cvtlq)

Syntax

cvtlq	$s_reg, $d_reg
cvtlq	$d_reg/$s_reg
Description

Convert Longword to Quadword converts the longword integer contents of $s_reg to the quadword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.


Convert G_floating to Quadword (cvtgq)

Syntax

cvtgq	$s_reg, $d_reg
cvtgq	$d_reg/$s_reg
Description

Convert G_floating to Quadword converts the G_floating contents of $s_reg to the quadword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtgq instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cvtgqc	VAX Rounding Mode: Chopped.
cvtgqv	VAX Convert-to-Integer Trap Mode: Imprecise, integer overflow enabled.
cvtgqvc	Combined meanings of cvtgqv and cvtgqc.
cvtgqs	VAX Trap Mode: Software, underflow enabled.
	VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled.
cvtgqsc	Combined meanings of cvtgqs and cvtgqc.
cvtgqsv	VAX Convert-to-Integer Trap Mode: Software, integer overflow enabled.
cvtgqsvc	Combined meanings of cvtgqs, cvtgqv, and cvtgqc.


Convert T_floating to Quadword (cvttq)

Syntax

cvttq	$s_reg, $d_reg
cvttq	$d_reg/$s_reg
Description

Convert T_floating to Quadword converts the T_floating contents of $s_reg to the quadword integer format and places the result in $d_reg. If an integer overflow occurs, the truncated result is stored in $d_reg and, if enabled, an arithmetic trap occurs.

Qualifiers

The following table describes the qualifiers for the cvttq instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cvttqc	IEEE Rounding Mode: Chopped.
cvttqv	IEEE Convert-to-Integer Trap Mode: Imprecise, integer overflow enabled, inexact disabled.
cvttqvc	Combined meanings of cvtgqv and cvtgqc.
cvttqsv	IEEE Convert-to-Integer Trap Mode: Software, integer overflow enabled, inexact disabled.
cvttqsvc	Combined meanings of cvttqs, cvtgqv, and cvttqc.
cvttqsvi	IEEE Convert-to-Integer Trap Mode: Software, integer overflow enabled, inexact enabled.
cvttqsvic	Combined meanings of cvttqsvi and cvttqc.
cvttqd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
cvttqvd	Combined meanings of cvttqv and cvttqd.
cvttqsvd	Combined meanings of cvttqsv and cvttqd.
cvttqsvid	Combined meanings of cvttqsvi and cvttqd.


Convert Quadword to F_floating (cvtqf)

Syntax

cvtqf	$s_reg, $d_reg
cvtqf	$d_reg/$s_reg
Description

Convert Quadword to F_floating converts the quadword integer contents of $s_reg to the F_floating-point format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqf instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cvtqfc	VAX Rounding Mode: Chopped.


Convert Quadword to G_floating (cvtqg)

Syntax

cvtqg	$s_reg, $d_reg
cvtqg	$d_reg/$s_reg
Description

Convert Quadword to G_floating converts the quadword integer contents of $s_reg to the G_floating format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqg instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cvtqgc	VAX Rounding Mode: Chopped.


Convert Quadword to S_floating (cvtqs)

Syntax

cvtqs	$s_reg, $d_reg
cvtqs	$d_reg/$s_reg
Description

Convert Quadword to S_floating converts the quadword integer contents of $s_reg to the S_floating format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqs instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cvtqsc	IEEE Rounding Mode: Chopped.
cvtqsm	IEEE Rounding Mode: Minus infinity.
cvtqsd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
cvtqssu	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
cvtqssuic	Combined meanings of cvtqssui and cvtqsc.
cvtqssuim	Combined meanings of cvtqssui and cvtqsm.
cvtqssuid	Combined meanings of cvtqssui and cvtqsd.


Convert Quadword to T_floating (cvtqt)

Syntax

cvtqt	$s_reg, $d_reg
cvtqt	$d_reg/$s_reg
Description

Convert Quadword to T_floating converts the quadword integer contents of $s_reg to the T_floating format and places the result in $d_reg.

Qualifiers

The following table describes the qualifiers for the cvtqt instructions:

Instruction	Qualifier Description
cvtqtc	IEEE Rounding Mode: Chopped.
cvtqtm	IEEE Rounding Mode: Minus infinity.
cvtqtd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
cvtqtsui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
cvtqtsuic	Combined meanings of cvtqtsui and cvtqtc.
cvtqtsuim	Combined meanings of cvtqssui and cvtqtm.
cvtqtsuid	Combined meanings of cvtqtsui and cvtqtd.


Convert D_floating to G_floating (cvtdg)

Syntax

cvtdg	$s_reg, $d_reg
cvtdg	$d_reg/$s_reg
Description

Convert D_floating to G_floating converts the D_floating contents of $s_reg to the G_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtdg instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cvtdgc	VAX Rounding Mode: Chopped.
cvtdgu	VAX Trap Mode: Imprecise, underflow enabled.
cvtdguc	Combined meanings of cvtdgc and cvtdgu.
cvtdgs	VAX Trap Mode: Software, underflow disabled.
	VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled.
cvtdgsc	Combined meanings of cvtdgs and cvtdgc.
cvtdgsu	VAX Trap Mode: Software, underflow enabled.
cvtdgsuc	Combined meanings of cvtdgs and cvtdguc.


Convert G_floating to D_floating (cvtgd)

Syntax

cvtgd	$s_reg, $d_reg
cvtgd	$d_reg/$s_reg
Description

Convert G_floating to D_floating converts the G_floating contents of $s_reg to the D_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtgd instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cvtgdc	VAX Rounding Mode: Chopped.
cvtgdu	VAX Trap Mode: Imprecise, underflow enabled.
cvtgduc	Combined meanings of cvtgdc and cvtgdu.
cvtgds	VAX Trap Mode: Software, underflow disabled.
	VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled.
cvtgdsc	Combined meanings of cvtgds and cvtgdc.
cvtgdsu	VAX Trap Mode: Software, underflow enabled.
cvtgdsuc	Combined meanings of cvtgds and cvtgduc.


Convert G_floating to F_floating (cvtgf)

Syntax

cvtgf	$s_reg, $d_reg
cvtgf	$d_reg/$s_reg
Description

Convert G_floating to F_floating converts the G_floating contents of $s_reg to the F_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtgf instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cvtgfc	VAX Rounding Mode: Chopped.
cvtgfu	VAX Trap Mode: Imprecise, underflow enabled.
cvtgfuc	Combined meanings of cvtgfc and cvtgfu.
cvtgfs	VAX Trap Mode: Software, underflow disabled.
	VAX Convert-to-Integer Trap Mode: Software, integer overflow disabled.
cvtgfsc	Combined meanings of cvtgfs and cvtgfc.
cvtgfsu	VAX Trap Mode: Software, underflow enabled.
cvtgfsuc	Combined meanings of cvtgfs and cvtgfuc.


Convert T_floating to S_floating (cvtts)

Syntax

cvtts	$s_reg, $d_reg
cvtts	$d_reg/$s_reg
Description

Convert T_floating to S_floating converts the T_floating contents of $s_reg to the S_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtts instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cvttsc	IEEE Rounding Mode: Chopped.
cvttsm	IEEE Rounding Mode: Minus infinity.
cvttsd	IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11).
cvttsu	IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled.
cvttsuc	IEEE Trap Mode: Underflow enabled.
	IEEE Rounding Mode: Chopped.
cvttsum	Combined meanings of cvttsu and cvttsm.
cvttsud	Combined meanings of cvttsu and cvttsd.
cvttssu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.
cvttssuc	Combined meanings of cvttss, cvttsu, and cvttsc.
cvttssum	Combined meanings of cvttss, cvttsu, and cvttsm.
cvttssud	Combined meanings of cvttss, cvttsu, and cvttd.
cvttssui	IEEE Trap Mode: Software, underflow enabled, inexact enabled.
cvttssuic	Combined meanings of cvttssui and cvttsc.
cvttssuim	Combined meanings of cvttssui and cvttsm.


Convert S_floating to T_floating (cvtst)

Syntax

cvtst	$s_reg, $d_reg
cvtst	$d_reg/$s_reg
Description

Convert S_floating to T_floating converts the S_floating contents of $s_reg to the T_floating precision, rounds according to the rounding mode, and places the result in $d_reg. If an overflow occurs, an unpredictable value is stored in $d_reg and a floating-point trap occurs.

Qualifiers

The following table describes the qualifiers for the cvtst instructions:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cvtstsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.


Compare G_floating Equal (cmpgeq)

Syntax

cmpgeq	$s_reg1, $s_reg2, $d_reg
cmpgeq	$d_reg/$s_reg1, $s_reg2
Description

Compare G_floating Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 equals $s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpgeq instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cmpgeqs	VAX Trap Mode: Software, underflow disabled.


Compare G_floating Less Than (cmpglt)

Syntax

cmpglt	$s_reg1, $s_reg2, $d_reg
cmpglt	$d_reg/$s_reg1, $s_reg2
Description

Compare G_floating Less Than compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpglt instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cmpglts	VAX Trap Mode: Software, underflow disabled.


Compare G_floating Less Than or Equal (cmpgle)

Syntax

cmpgle	$s_reg1, $s_reg2, $d_reg
cmpgle	$d_reg/$s_reg1, $s_reg2
Description

Compare G_floating Less Than or Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than or equal to $s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpgle instructions:

Instruction	Qualifier Description
no qualifier	VAX Rounding Mode: Normal rounding.
	VAX Trap Mode: Imprecise, underflow disabled.
cmpgles	VAX Trap Mode: Software, underflow_disabled.


Compare T_floating Equal (cmpteq)

Syntax

cmpteq	$s_reg1, $s_reg2, $d_reg
cmpteq	$d_reg/$s_reg1, $s_reg2
Description

Compare T_floating Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 equals $s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmpteq instruction:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cmpteqsu	IEEE Trap Mode: Software, underflow enabled, inexact_disabled.


Compare T_floating Less Than (cmptlt)

Syntax

cmptlt	$s_reg1, $s_reg2, $d_reg
cmptlt	$d_reg/$s_reg1, $s_reg2
Description

Compare T_floating Less Than compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than $s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmptlt instruction:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cmptltsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.


Compare T_floating Less Than or Equal (cmptle)

Syntax

cmptle	$s_reg1, $s_reg2, $d_reg
cmptle	$d_reg/$s_reg1, $s_reg2
Description

Compare T_floating Less Than or Equal compares the contents of $s_reg1 or $d_reg with the contents of $s_reg2. If $s_reg1 is less than or equal to $s_reg2, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmptle instruction:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cmptlesu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.


Compare T_floating Unordered (cmptun)

Syntax

cmptun	$s_reg1, $s_reg2, $d_reg
cmptun	$d_reg/$s_reg1, $s_reg2
Description

Compare T_floating Unordered compares the contents of $s_ reg1 or $d_reg with the contents of $s_reg2. If either $s_reg1 or $s_reg 2 is unordered, a nonzero value is written to the destination register; otherwise, a true zero value is written to the destination. Exceptions are not signaled for unordered values.

Qualifiers

The following table describes the qualifiers for the cmptun instruction:

Instruction	Qualifier Description
no qualifier	IEEE Rounding Mode: Normal rounding.
	IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled.
cmptunsu	IEEE Trap Mode: Software, underflow enabled, inexact disabled.


Floating Move (fmov)

Syntax

fmov	$s_reg, $d_reg
Description

Floating Move moves the double-or single-precision contents of the $s_reg to $d_reg.


Copy Sign (cpys)

Syntax

cpys	$s_reg1, $s_reg2, $d_reg
cpys	$d_reg1/$s_reg1, $s_reg2
Description

Copy Sign fetches the sign bit of $s_reg1 or $d_reg, combines it with the exponent and fraction of $s_reg2, and copies the result to $d_reg.


Copy Sign Negate (cpysn)

Syntax

cpysn	$s_reg1, $s_reg2, $d_reg
cpysn	$d_reg1/$s_reg1, $s_reg2
Description

Copy Sign Negate Fetches the sign bit of $s_reg1 or $d_reg, complements it, combines it with the exponent and fraction of $s_reg2, and copies the result to $d_reg.


Copy Sign and Exponent (cpyse)

Syntax

cpyse	$s_reg1, $s_reg2, $d_reg
cpyse	$d_reg1/$s_reg1, $s_reg2
Description

Copy Sign and Exponent fetches the sign and exponent of $s_reg1 or $d_reg, combines them with the fraction of $s_reg2, and copies the result to $d_reg.


Move if Equal to Zero (fcmoveq)

Syntax

fcmoveq	$s_reg1, $s_reg2, $d_reg
fcmoveq	$d_reg1/$s_reg1, $s_reg2
Description

Move if Equal to Zero compares the contents of $s_reg1 or $d_reg against zero. If equal to zero, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Not Equal to Zero (fcmovne)

Syntax

fcmovne	$s_reg1, $s_reg2, $d_reg
fcmovne	$d_reg1/$s_reg1, $s_reg2
Description

Move if Not Equal to Zero compares the contents of $s_ reg1 or $d_reg against zero. If not equal to zero, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move If Less Than Zero (fcmovlt)

Syntax

fcmovlt	$s_reg1, $s_reg2, $d_reg
fcmovlt	$d_reg1/$s_reg1, $s_reg2
Description

Move if Less Than Zero compares the contents of $s_reg1 or $d_reg against zero. If less than zero, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Less Than or Equal to Zero (fcmovle)

Syntax

fcmovle	$s_reg1, $s_reg2, $d_reg
fcmovle	$d_reg1/$s_reg1, $s_reg2
Description

Move if Less Than or Equal to Zero compares the contents of $s_reg1 or $d_reg against zero. If less than or equal to zero, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Greater Than Zero (fcmovgt)

Syntax

fcmovgt	$s_reg1, $s_reg2, $d_reg
fcmovgt	$d_reg1/$s_reg1, $s_reg2
Description

Move if Greater Than Zero compares the contents of $s_reg1 or $d_reg against zero. If greater than zero, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Move if Greater Than or Equal to Zero (fcmovge)

Syntax

fcmovge	$s_reg1, $s_reg2, $d_reg
fcmovge	$d_reg1/$s_reg1, $s_reg2
Description

Move if Greater Than or Equal to Zero compares the contents of $s_reg1 or $d_reg against zero. If greater than or equal to zero, the contents of $s_reg2 are copied to $d_reg; otherwise, $d_reg is unchanged.


Branch Equal to Zero (fbeq)

Syntax

fbeq	$s_reg, lab
Description

Branch Equal to Zero compares the contents of the source register with zero. If equal to zero, a branch is made to the specified label.


Branch Not Equal to Zero (fbne)

Syntax

fbne	$s_reg, label
Description

Branch Not Equal to Zero compares the contents of the source register with zero. If not equal to zero, a branch is made to the specified label.


Branch Less Than Zero (fblt)

Syntax

fblt	$s_reg, label
Description

Branch Less Than Zero compares the contents of the source register with zero. If less than zero, a branch is made to the specified label.


Branch Less Than or Equal to Zero (fble)

Syntax

fble	$s_reg, label
Description

Branch Less Than or Equal to Zero compares the contents of the source register with zero. If less than or equal to zero, a branch is made to the specified label.


Branch Greater Than Zero (fbgt)

Syntax

fbgt	$s_reg, label
Description

Branch Greater Than Zero compares the contents of the source register with zero. If greater than zero, a branch is made to the specified label.


Branch Greater Than or Equal to Zero (fbge)

Syntax

fbge	$s_reg, label
Description

Branch Greater Than or Equal to Zero compares the contents of the source register with zero. If greater than or equal to zero, a branch is made to the specified label.


Move from FP Control Register (mf_fpcr)

Syntax

mf_fpcr	$d_reg
Description

Move from FP Control Register copies the value in the specified source register to the FPCR.


Move to FP Control Register (mt_fpcr)

Syntax

mt_fpcr	$d_reg
Description

Move to FP Control Register copies the value in the FPCR to the specified destination register.


No Operation (fnop)

Syntax

fnop

Description

No Operation has no effect on the machine state.


Main Instruction Operand Descriptions

A main instruction accepts one or more of the following operands:

Operand Specifier	Description
address	A symbolic expression whose effective value is used as an address.
$d_reg	Destination register. An integer register that receives a value as a result in an operation.
$d_reg/$s_reg	One integer register that is used as both a destination register and a source register.
label	A label that identifies a location in a program.
offset	An immediate value that is added to the contents of a base register to calculate an effective address.
palcode	A value that determines the operation performed by a PAL instruction.
$s_reg, $s_reg1, $s_reg2	Registers whose contents are to be used in an operation.
val_expr	An expression whose value is used as an absolute value.
val_immed	An immediate value that is to be used in an operation.
jhint	An address operand that provides a hint of where a jmp or jsr instruction will transfer control.
rhint	An immediate operand that provides software with a hint about how a ret or jsr coroutine instruction is used.


Load Instruction General Notes

These general-purpose load instructions are used to load immediate values.

Load instructions can generate many code sequences for which the linker must fix the address by resolving external data items.


Load Address (lda)

Syntax

lda	$d_reg, address
Description

Load Address loads the destination register with the effective address of the specified data item.


Load Address High (ldah)

Syntax

ldah	$d_reg, offset (b_reg)
Description

Load Address High loads the destination register with the effective address of the specified data item. In computing the effective address, the signed constant offset is multiplied by 65536 before adding to the base register. The signed offset must be in the range -32768 to 32767.


Load Byte (ldb)

Syntax

ldb	$d_reg, address
Description

Load Byte loads the least significant byte of the destination register with the contents of the byte specified by the effective address. Because the loaded byte is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

Note: The assembler destroys the contents of temporary registers $at and $t9 for this instruction.


Load Byte Unsigned (ldbu)

Syntax

ldbu	$d_reg, address
Description

Load Byte Unsigned loads the least significant byte of the destination register with the contents of the byte specified by the effective address. Because the loaded byte is an unsigned value, the other bytes of the destination register are cleared to zeros.

Note: The assembler destroys the contents of temporary registers $at and $t9 for this instruction.


Load Word (ldw)

Syntax

ldw	$d_reg, address
Description

Load Word loads the two least significant bytes of the destination register with the contents of the word specified by the effective address. Because the loaded word is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

If the effective address is not evenly divisible by 2, a data alignment exception may be signaled.

Note: The assembler destroys the contents of temporary registers $at and $t9 for this instruction.


Load Word Unsigned (ldwu)

Syntax

ldwu	$d_reg, address
Description

Load Word Unsigned loads the two least significant bytes of the destination register with the contents of the word specified by the effective address. Because the loaded word is an unsigned value, the other bytes of the destination register are cleared to zeros.

If the effective address is not evenly divisible by 2, a data alignment exception may be signaled.

Note: The assembler destroys the contents of temporary registers $at and $t9 for this instruction.


Load Sign Extended Longword (ldl)

Syntax

ldl	$d_reg, address
Description

Load Sign Extended Longword loads the four least significant bytes of the destination register with the contents of the longword specified by the effective address. Because the loaded longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.


Load Sign Extended Longword Locked (ldl_l)

Syntax

ldl_l	$d_reg, address
Description

Load Sign Extended Longword Locked loads the four least significant bytes of the destination register with the contents of the longword specified by the effective address. Because the loaded longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.

If a ldl_l instruction executes without faulting, the processor records the target physical address in a per- processor locked-physical-address register and sets the per-processor lock flag.

If the per-processor lock flag is still set when a Store Longword Conditional (stl_c) instruction is executed, the store occurs; otherwise, it does not occur.

See Also

Atomic Updates


Load Quadword (ldq)

Syntax

ldq	$d_reg, address
Description

Load Quadword loads the destination register with the contents of the quadword specified by the effective address. All bytes of the register are replaced with the contents of the loaded quadword.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.


Load Quadword Locked (ldq_l)

Syntax

ldq_l	$d_reg, address
Description

Load Quadword Locked loads the destination register with the contents of the quadword specified by the effective address. All bytes of the register are replaced with the contents of the loaded quadword.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.

If an ldq_l instruction executes without faulting, the processor records the target physical address in a per-processor locked-physical-address register and sets the per-processor lock flag. If the per-processor lock flag is still set when a Store Quadword Conditional (stq_c) instruction is executed, the store occurs; otherwise, it does not occur.

See Also

Atomic Updates


Load Quadword Unaligned (ldq_u)

Syntax

ldq_u	$d_reg, address
Description

Load Quadword Unaligned loads the destination register with the contents of the quadword specified by the effective address with the three low-order bits cleared. The address does not have to be aligned on an 8-byte boundary, it can be any byte address.


Unaligned Load Word (uldw)

Syntax

uldw	$d_reg, address
Description

Unaligned Load Word loads the two least significant bytes of the destination register with the word at the specified address. The address does not have to be aligned on a 2-byte boundary, it can be any byte address. Because the loaded word is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Unaligned Load Word Unsigned (uldwu)

Syntax

uldwu	$d_reg, address
Description

Unaligned Load Word Unsigned loads the two least significant bytes of the destination register with the word at the specified address. The address does not have to be aligned on a 2-byte boundary, it can be any byte address. Because the loaded word is an unsigned value, the other bytes of the destination register are cleared to zeros.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Unaligned Load Longword (uldl)

Syntax

uldl	$d_reg, address
Description

Unaligned Load Longword loads the four least significant bytes of the destination register with the contents of the longword specified by the effective address. The address does not have to be aligned on a 4-byte boundary; it can be any address. Because the loaded longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Unaligned Load Quadword (uldq)

Syntax

uldq	$d_reg, address
Description

Unaligned Load Quadword loads the destination register with the quadword at the specified address. The address does not have to be aligned on an 8-byte boundary; it can be any byte address in memory.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10 for this instruction.


Load Immediate Longword

Syntax

ldil	$d_reg, val_expr
Description

Load Immediate Longword loads the destination register with the value of an expression that can be computed at assembly time. The value is converted to canonical longword form before being stored in the destination register; bit 31 is replicated in bits 32 though 63 of the destination register.


Load Immediate Quadword (ldiq)

Syntax

ldiq	$d_reg, val_expr
Description

Load Immediate Quadword loads the destination register with the value of an expression that can be computed at assembly time.


Store Instructions

This topic describes the general-purpose store instructions supported by the assembler. Store instructions move data between memory and general registers.


Store Byte (stb)

Syntax

stb	$s_reg, address
Description

Store Byte stores the least significant byte of the source register in the memory location specified by the effective address.

Note: The assembler destroys the contents of temporary registers $at, $t9, $t10, and $t11 for this instruction.


Store Word (stw)

Syntax

stw	$s_reg, address
Description

Store Word stores the two least significant bytes of the source register in the memory location specified by the effective address.

If the effective address is not evenly divisible by 2, a data alignment exception may be signaled.

Note: The assembler destroys the contents of temporary registers $at, $t9, $t10, and $t11 for this instruction.


Store Longword (stl)

Syntax

stl	$s_reg, address
Description

Store Longword stores the four least significant bytes of the source register in the memory location specified by the effective address.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.


Store Longword Conditional (stl_c)

Syntax

stl_c	$s_reg, address
Description

Store Longword Conditional stores the four least significant bytes of the source register in the memory location specified by the effective address, if the lock flag is set. The lock flag is returned in the source register and is then set to zero. For further information, see the Load Sign Extended Longword Locked (ldl_l) and Atomic Updates topics.

If the effective address is not evenly divisible by 4, a data alignment exception is signaled.

See Also

Atomic Updates


Store Quadword (stq)

Syntax

stq	$s_reg, address
Description

Store Quadword stores the contents of the source register in the memory location specified by the effective address.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.


Store Quadword Conditional (stq_c)

Syntax

stq_c	$s_reg, address
Description

Store Quadword Conditional stores the contents of the source register in the memory location specified by the effective address, if the lock flag is set. The lock flag is returned in the source register and is then set to zero. For further information, see the Load Quadword Locked (ldq_l) and Atomic Updates topics.

If the effective address is not evenly divisible by 8, a data alignment exception is signaled.

See Also

Atomic Updates


Store Quadword Unaligned (stq_u)

Syntax

stq_u	$s_reg, address
Description

Store Quadword Unaligned stores the contents of the source register in the memory location specified by the effective address with the three low-order bits cleared.


Unaligned Store Word (ustw)

Syntax

ustw	$s_reg, address
Description

Unaligned Store Word stores the two least significant bytes of the source register in the memory location specified by the effective address. The address does not have to be aligned on a 2-byte boundary, it can be any byte address.

Note:	The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Unaligned Store Longword (ustl)

Syntax

ustl	$s_reg, address
Description

Unaligned Store Longword stores the four least significant bytes of the source register in the memory location specified by the effective address. The address does not have to be aligned on a 4-byte boundary, it can be any byte address.

Note:	The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Unaligned Store Quadword (ustq)

Syntax

ustq	$s_reg, address
Description

Unaligned Store Quadword stores the contents of the source register in a memory location specified by the effective address. The address does not have to be aligned on an 8-byte boundary, it can be any byte address.

Note:	The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.


Clear Instruction

There is one clear instruction.

Clear (clr)

Syntax

clr	$d_reg
Description

Clear sets the contents of the destination register to

zero.


Sign Extension Instruction

There is one sign extension instruction.

Sign-Extension Longword (sextl)

Syntax

sextl	$s_reg, $d_reg
sextl	$d_reg/$s_reg
sextl	val_immed, $d_reg
Description

Sign-Extension Longword moves the four least significant bytes of the source register into the four least significant bytes of the destination register. Because the moved longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.


Absolute Value Longword (absl)

Syntax

absl	$s_reg, $d_reg
absl	$d_reg/$s_reg
absl	val_immed, $d_reg
Description

Absolute Value Longword computes the absolute value of the contents of the source register and puts the result in the destination register. If the value in the source register is -2147483648, an overflow exception is signaled.


Absolute Value Quadword (absq)

Syntax

absq	$s_reg, $d_reg
absq	$d_reg/$s_reg
absq	val_immed, $d_reg
Description

Absolute Value Quadword computes the absolute value of the contents of the source register and puts the result in the destination register. If the value in the source register is -9223372036854775808, an overflow exception is signaled.


Negate Longword (without overflow) (negl)

Syntax

negl	$s_reg, $d_reg
negl	$d_reg/$s_reg
negl	val_immed, $d_reg
Description

Negate Longword (without overflow) negates the integer contents of the four least significant bytes in the source register and puts the result in the destination register. An overflow occurs if the value in the source register is -2147483648, but the overflow exception is not signaled.


Negate Longword (with overflow) (neglv)

Syntax

neglv	$s_reg, $d_reg
neglv	$d_reg/$s_reg
neglv	val_immed, $d_reg
Description

Negate Longword (with overflow) negates the integer contents of the four least significant bytes in the source register and puts the result in the destination register. If the value in the source register is -2147483648, an integer overflow exception is signaled.


Negate Quadword (without overflow) (negq)

Syntax

negq	$s_reg, $d_reg
negq	$d_reg/$s_reg
negq	val_immed, $d_reg
Description

Negate Quadword (without overflow) negates the integer contents of the source register and puts the result in the destination register. An overflow occurs if the value in the source register is -9223372036854775808, but the overflow exception is not signaled.


Negate Quadword (with overflow) (negqv)

Syntax

negqv	$s_reg, $d_reg
negqv	$d_reg/$s_reg
negqv	val_immed, $d_reg
Description

Negate Quadword (with overflow) negates the integer contents of the source register and puts the result in the destination register. If the value in the source register is -9223372036854775808, an integer overflow exception is signaled.


Add Longword (without overflow) (addl)

Syntax

addl	$s_reg1, $s_reg2, $d_reg
addl	$d_reg/$s_reg1, $s_reg2
addl	$s_reg1, val_immed, $d_reg
addl	$d_reg/$s_reg1, val_immed
Description

Add Longword (without overflow) computes the sum of two signed 32-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. Overflow exceptions never occur.


Add Longword (with overflow) (addlv)

Syntax

addlv	$s_reg1, $s_reg2, $d_reg
addlv	$d_reg/$s_reg1, $s_reg2
addlv	$s_reg1, val_immed, $d_reg
addlv	$d_reg/$s_reg1, val_immed
Description

Add Longword (with overflow) computes the sum of two signed 32-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. If the result cannot be represented as a signed 32-bit number, an integer overflow exception is signaled.


Add Quadword (without overflow) (addq)

Syntax

addq	$s_reg1, $s_reg2, $d_reg
addq	$d_reg/$s_reg1, $s_reg2
addq	$s_reg1, val_immed, $d_reg
addq	$d_reg/$s_reg1, val_immed
Add Quadword (without overflow) computes the sum of two signed 64-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. Overflow exceptions never occur.


Add Quadword (with overflow) (addqv)

Syntax

addqv	$s_reg1, $s_reg2, $d_reg
addqv	$d_reg/$s_reg1, $s_reg2
addqv	$s_reg1, val_immed, $d_reg
addqv	$d_reg/$s_reg1, val_immed
Description

Add Quadword (with overflow) computes the sum of two signed 64-bit values. This instruction adds the contents of $s_reg1 to the contents of $s_reg2 or the immediate value and then puts the result in the destination register. If the result cannot be represented as a signed 64-bit number, an integer overflow exception is signaled.


Scaled Longword Add by 4 (s4addl)

Syntax

s4addl	$s_reg1, $s_reg2, $d_reg
s4addl	$d_reg/$s_reg1, $s_reg2
s4addl	$s_reg1, val_immed, $d_reg
s4addl	$d_reg/$s_reg1, val_immed
Description

Scaled Longword Add by 4 computes the sum of two signed 32-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 4 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Add by 4 (s4addq)

Syntax

s4addq	$s_reg1, $s_reg2, $d_reg
s4addq	$d_reg/$s_reg1, $s_reg2
s4addq	$s_reg1, val_immed, $d_reg
s4addq	$d_reg/$s_reg1, val_immed
Description

Scaled Quadword Add by 4 computes the sum of two signed 64-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 4 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Longword Add by 8 (s8addl)

Syntax

s8addl	$s_reg1, $s_reg2, $d_reg
s8addl	$d_reg/$s_reg1, $s_reg2
s8addl	$s_reg1, val_immed, $d_reg
s8addl	$d_reg/$s_reg1, val_immed
Description

Scaled Longword Add by 8 computes the sum of two signed 32-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 8 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Add by 8 (s8addq)

Syntax

s8addq	$s_reg1, $s_reg2, $d_reg
s8addq	$d_reg/$s_reg1, $s_reg2
s8addq	$s_reg1, val_immed, $d_reg
s8addq	$d_reg/$s_reg1, val_immed
Description

Scaled Quadword Add by 8 computes the sum of two signed 64-bit values. This instruction scales (multiplies) the contents of $s_reg1 by 8 and then adds the contents of $s_reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.


Multiply Longword (without overflow) (mull)

Syntax

mull	$s_reg1, $s_reg2, $d_reg
mull	$d_reg/$s_reg1, $s_reg2
mull	$s_reg1, val_immed, $d_reg
mull	$d_reg/$s_reg1, val_immed
Description

Multiply Longword (without overflow) computes the product of two signed 32-bit values. This instruction puts the 32-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. Overflows are not reported.


Multiply Longword (with overflow) (mullv)

Syntax

mullv	$s_reg1, $s_reg2, $d_reg
mullv	$d_reg/$s_reg1, $s_reg2
mullv	$s_reg1, val_immed, $d_reg
mullv	$d_reg/$s_reg1, val_immed
Description

Multiply Longword (with overflow) computes the product of two signed 32-bit values. This instruction puts the 32-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. If an overflow occurs, an integer overflow exception is signaled.


Multiply Quadword (without overflow) (mulq)

Syntax

mulq	$s_reg1, $s_reg2, $d_reg
mulq	$d_reg/$s_reg1, $s_reg2
mulq	$s_reg1, val_immed, $d_reg
mulq	$d_reg/$s_reg1, val_immed
Description

Multiply Quadword (without overflow) computes the product of two signed 64-bit values. This instruction puts the 64-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. Overflow is not reported.


Multiply Quadword (with overflow) (mulqv)

Syntax

mulqv	$s_reg1, $s_reg2, $d_reg
mulqv	$d_reg/$s_reg1, $s_reg2,
mulqv	$s_reg1, val_immed, $d_reg
mulqv	$d_reg/$s_reg1, val_immed
Description

Multiply Quadword (with overflow) computes the product of two signed 64-bit values. This instruction puts the 64-bit product of $s_reg1 and $s_reg2 or the immediate value in the destination register. If an overflow occurs, an integer overflow exception is signaled.


Subtract Longword (without overflow) (subl)

Syntax

subl	$s_reg1, $s_reg2, $d_reg
subl	$d_reg/$s_reg1, $s_reg2
subl	$s_reg1, val_immed, $d_reg
subl	$d_reg/$s_reg1, val_immed
Description

Subtract Longword (without overflow) computes the difference of two signed 32-bit values. This instruction subtracts either the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. Overflow exceptions never happen.


Subtract Longword (with overflow) (sublv)

Syntax

sublv	$s_reg1, $s_reg2, $d_reg
sublv	$d_reg/$s_reg1, $s_reg2
sublv	$s_reg1, val_immed, $d_reg
sublv	$d_reg/$s_reg1, val_immed
Description

Subtract Longword (with overflow) computes the difference of two signed 32-bit values. This instruction subtracts either the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. If the true result's sign differs from the destination register's sign, an integer overflow exception is signaled.


Subtract Quadword (without overflow) (subq)

Syntax

subq	$s_reg1, $s_reg2, $d_reg
subq	$d_reg/$s_reg1, $s_reg2
subq	$s_reg1, val_immed, $d_reg
subq	$d_reg/$s_reg1, val_immed
Description

Subtract Quadword (without overflow) computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. Overflow exceptions never occur.


Subtract Quadword (with overflow) (subqv)

Syntax

subqv	$s_reg1, $s_reg2, $d_reg
subqv	$d_reg/$s_reg1, $s_reg2
subqv	$s_reg1, val_immed, $d_reg
subqv	$d_reg/$s_reg1, val_immed
Description

Subtract Quadword (with overflow) computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or an immediate value from the contents of $s_reg1 and then puts the result in the destination register. If the true result's sign differs from the destination register's sign, an integer overflow exception is signaled.


Scaled Longword Subtract by 4 (s4subl)

Syntax

s4subl	$s_reg1, $s_reg2, $d_reg
s4subl	$d_reg/$s_reg1, $s_reg2
s4subl	$s_reg1, val_immed, $d_reg
s4subl	$d_reg/$s_reg1, val_immed
Description

Scaled Longword Subtract by 4 computes the difference of two signed 32-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 4) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Subtract by 4 (s4subq)

Syntax

s4subq	$s_reg1, $s_reg2, $d_reg
s4subq	$d_reg/$s_reg1, $s_reg2
s4subq	$s_reg1, val_immed, $d_reg
s4subq	$d_reg/$s_reg1, val_immed
Description

Scaled Quadword Subtract by 4 computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 4) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Longword Subtract by 8 (s8subl)

Syntax

s8subl	$s_reg1, $s_reg2, $d_reg
s8subl	$d_reg/$s_reg1, $s_reg2
s8subl	$s_reg1, val_immed, $d_reg
s8subl	$d_reg/$s_reg1, val_immed
Description

Scaled Longword Subtract by 8 computes the difference of two signed 32-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 8) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Scaled Quadword Subtract by 8 (s8subq)

Syntax

s8subq	$s_reg1, $s_reg2, $d_reg
s8subq	$d_reg/$s_reg1, $s_reg2
s8subq	$s_reg1, val_immed, $d_reg
s8subq	$d_reg/$s_reg1, val_immed
Description

Scaled Quadword Subtract by 8 computes the difference of two signed 64-bit values. This instruction subtracts the contents of $s_reg2 or the immediate value from the scaled (by 8) contents of $s_reg1. The result is stored in the destination register. Overflow exceptions never occur.


Unsigned Quadword Multiply High Instruction

There is one unsigned quadword multiply high instruction.

Unsigned Quadword Multiply High (umulh)

Syntax

umulh	$s_reg1, $s_reg2, $d_reg
umulh	$d_reg/$s_reg1, $s_reg2
umulh	$s_reg1, val_immed, $d_reg
umulh	$d_reg/$s_reg1, val_immed
Description

Unsigned Quadword Multiply High computes the product of two unsigned 64-bit values. This instruction multiplies the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the high-order 64 bits of the 128-bit product in the destination register.


Divide Longword (divl)

Syntax

divl	$s_reg1, $s_reg2, $d_reg
divl	$d_reg/$s_reg1, $s_reg2
divl	$s_reg1, val_immed, $d_reg
divl	$d_reg/$s_reg1, val_immed
Description

Divide Longword computes the quotient of two signed 32-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

Overflow is signaled when dividing -2147483648 by -1. A call_pal PAL_gentrap instruction may be issued for either divide-by-zero or overflow.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Divide Longword Unsigned (divlu)

Syntax

divlu	$s_reg1, $s_reg2, $d_reg
divlu	$d_reg/$s_reg1, $s_reg2
divlu	$s_reg1, val_immed, $d_reg
divlu	$d_reg/$s_reg1, val_immed
Description

Divide Longword Unsigned computes the quotient of two unsigned 32-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

If the divisor is zero, an exception is signaled and a call_pal PAL_gentrap instruction may be issued. Overflow exceptions never occur.

Note: The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Divide Quadword (divq)

Syntax

divq	$s_reg1, $s_reg2, $d_reg
divq	$d_reg/$s_reg1, $s_reg2
divq	$s_reg1, val_immed, $d_reg
divq	$d_reg/$s_reg1, val_immed
Description

Divide Quadword computes the quotient of two signed 64-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

Overflow is signaled when dividing -9223372036854775808 by -1. A call_pal PAL_gentrap instruction may be issued for either divide-by-zero or overflow.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Divide Quadword Unsigned (divqu)

Syntax

divqu	$s_reg1, $s_reg2, $d_reg
divqu	$d_reg/$s_reg1, $s_reg2
divqu	$s_reg1, val_immed, $d_reg
divqu $	d_reg/$s_reg1, val_immed
Description

Divide Quadword Unsigned computes the quotient of two unsigned 64-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.

If the divisor is zero, an exception is signaled and a call_pal PAL_gentrap instruction may be issued. Overflow exceptions never occur.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Longword Remainder (reml)

Syntax

reml	$s_reg1, $s_reg2, $d_reg
reml	$d_reg/$s_reg1, $s_reg2
reml	$s_reg1, val_immed, $d_reg
reml	$d_reg/$s_reg1, val_immed
Description

Longword Remainder computes the remainder of the division of two signed 32-bit values. The remainder reml(i, j) is defined as i-(j*divl(i, j)) where j != 0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or by the immediate value and then puts the remainder in the destination register.

The reml instruction rounds toward zero. For example, divl(5,-3)=-1 , and reml(5,-3)=2 .

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Longword Remainder Unsigned (remlu)

Syntax

remlu	$s_reg1, $s_reg2, $d_reg
remlu	$d_reg/$s_reg1, $s_reg2
remlu	$s_reg1, val_immed, $d_reg
remlu	$d_reg/$s_reg1, val_immed
Description

Longword Remainder Unsigned computes the remainder of the division of two unsigned 32-bit values. The remainder remlu(i, j) is defined as i-(j*divlu(i, j)) where j !=0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the remainder in the destination register.

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Quadword Remainder (remq)

Syntax

remq	$s_reg1, $s_reg2, $d_reg
remq	$d_reg/$s_reg1, $s_reg2
remq	$s_reg1, val_immed, $d_reg
remq	$d_reg/$s_reg1, val_immed
Description

Quadword Remainder computes the remainder of the division of two signed 64-bit values. The remainder remq (i, j) is defined as i-(j*divq(i, j)) where j != 0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the remainder in the destination register.

The remq instruction rounds toward zero. For example, divq (5,-3)=-1, and

remq (5,-3)=2 .

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Quadword Remainder Unsigned (remqu)

Syntax

remqu	$s_reg1, $s_reg2, $d_reg
remqu	$d_reg/$s_reg1, $s_reg2
remqu	$s_reg1, val_immed, $d_reg
remqu	$d_reg/$s_reg1, val_immed
Description

Quadword Remainder Unsigned computes the remainder of the division of two unsigned 64-bit values. The remainder remqu(i, j) is defined as i-(j*divqu(i, j)) where j !=0. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the remainder in the destination register.

For divide-by-zero, an error is signaled and a call_pal PAL_gentrap instruction may be issued.

Note:	The assembler destroys the contents of temporary registers $at, $t9, and $t10, $t11, and $t12 for this instruction.


Logical Complement (NOT) (not)

Syntax

not	$s_reg, $d_reg
not	$d_reg/$s_reg
not	val_immed, $d_reg
not	$s_reg1, $s_reg2, $d_reg
not	$d_reg/$s_reg1, $s_reg2
not	$s_reg1, val_immed, $d_reg
not	$d_reg/$s_reg1, val_immed
Description

Logical Complement (NOT) computes the Logical NOT of a value. This instruction complements (bit-wise) the contents of $s_reg1 and puts the result in the destination register.


Logical Product (AND) (and)

Syntax

and	$s_reg, $d_reg
and	$d_reg/$s_reg
and	val_immed, $d_reg
and	$s_reg1, $s_reg2, $d_reg
and	$d_reg/$s_reg1, $s_reg2
and	$s_reg1, val_immed, $d_reg
and	$d_reg/$s_reg1, val_immed
Description

Logical Product (AND) computes the Logical AND of two values. This instruction ANDs (bit-wise) the contents of $s_reg1 with the contents of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Sum (OR) (bis)

Syntax

bis	$s_reg, $d_reg
bis	$d_reg/$s_reg
bis	val_immed, $d_reg
bis	$s_reg1, $s_reg2, $d_reg
bis	$d_reg/$s_reg1, $s_reg2
bis	$s_reg1, val_immed, $d_reg
bis	$d_reg/$s_reg1, val_immed
Description

Logical Sum (OR) computes the Logical OR of two values. This instruction ORs (bit-wise) the contents of $s_reg1 with the contents of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Sum (OR) (or)

The instruction or is a synonym for bis.


Logical Difference (XOR) (xor)

Syntax

xor	$s_reg, $d_reg
xor	$d_reg/$s_reg
xor	val_immed, $d_reg
xor	$s_reg1, $s_reg2, $d_reg
xor	$d_reg/$s_reg1, $s_reg2
xor	$s_reg1, val_immed, $d_reg
xor	$d_reg/$s_reg1, val_immed
Description

Logical Difference (XOR) computes the XOR of two values. This instruction XORs (bit-wise) the contents of $s_reg1 with the contents of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Product with Complement (ANDNOT) (bic)

Syntax

bic	$s_reg, $d_reg
bic	$d_reg/$s_reg
bic	val_immed, $d_reg
bic	$s_reg1, $s_reg2, $d_reg
bic	$d_reg/$s_reg1, $s_reg2
bic	$s_reg1, val_immed, $d_reg
bic	$d_reg/$s_reg1, val_immed
Description

Logical Product with Complement (ANDNOT) computes the Logical AND of two values. This instruction ANDs (bit-wise) the contents of $s_reg1 with the ones complement of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Product with Complement (ANDNOT) (andnot)

The instruction andnot is a synonym for bic.


Logical Sum with Complement (ORNOT) (ornot)

Syntax

ornot	$s_reg, $d_reg
ornot	$d_reg/$s_reg
ornot	val_immed, $d_reg
ornot	$s_reg1, $s_reg2, $d_reg
ornot	$d_reg/$s_reg1, $s_reg2
ornot	$s_reg1, val_immed, $d_reg
ornot	$d_reg/$s_reg1, val_immed
Description

Logical Sum with Complement (ORNOT) computes the logical OR of two values. This instruction ORs (bit-wise) the contents of $s_reg1 with the ones complement of $s_reg2 or an immediate value and then puts the result in the destination register.


Logical Equivalence (XORNOT) (eqv)

Syntax

eqv	$s_reg, $d_reg
eqv	$d_reg/$s_reg
eqv	val_immed, $d_reg
eqv	$s_reg1, $s_reg2, $d_reg
eqv	$d_reg/$s_reg1, $s_reg2
eqv	$s_reg1, val_immed, $d_reg
eqv	$d_reg/$s_reg1, val_immed
Description

Logical Equivalence (XORNOT) computes the logical XOR of two values. This instruction XORs (bit-wise) the contents of $s_reg1 with the ones complement of $s_reg2 or the immediate value and then puts the result in the destination register.


Logical Equivalence (XORNOT) (xornot)

The instruction xornot is a synonym for eqv.


Shift Left Logical (sll)

Syntax

sll	$s_reg, $d_reg
sll	$d_reg/$s_reg
sll	val_immed, $d_reg
sll	$s_reg1, $s_reg2, $d_reg
sll	$d_reg/$s_reg1, $s_reg2
sll	$s_reg1, val_immed, $d_reg
sll	$d_reg/$s_reg1, val_immed
Description

Shift Left Logical shifts the contents of a register left (toward the sign bit) and inserts zeros in the vacated bit positions. The contents of $s_reg1 specifies the value to shift, and the contents of $s_reg2 or the immediate value specifies the number of bits to shift. If $s_reg2 or the immediate value is greater than 63 or less than zero, $s_reg1 shifts by the result of the following AND operation: $s_reg2 AND 63.


Shift Right Logical (srl)

Syntax

srl	$s_reg, $d_reg
srl	$d_reg/$s_reg
srl	val_immed, $d_reg
srl	$s_reg1, $s_reg2, $d_reg
srl	$d_reg/$s_reg1, $s_reg2
srl	$s_reg1, val_immed, $d_reg
srl	$d_reg/$s_reg1, val_immed
Description

Shift Right Logical shifts the contents of a register right (toward the least significant bit) and inserts zeros in the vacated bit positions. The contents of $s_reg1 specifies the value to shift, and the contents of $s_reg2 or the immediate value specifies the number of bits to shift. If $s_reg2 or the immediate value is greater than 63 or less than zero, $s_reg1 shifts by the result of the following AND operation: $s_reg2 AND 63.


Shift Right Arithmetic (sra)

Syntax

sra	$s_reg, $d_reg
sra	$d_reg/$s_reg
sra	val_immed, $d_reg
sra	$s_reg1, $s_reg2, $d_reg
sra	$d_reg/$s_reg1, $s_reg2
sra	$s_reg1, val_immed, $d_reg
sra	$d_reg/$s_reg1, val_immed
Description

Shift Right Arithmetic shifts the contents of a register right (toward the least significant bit) and inserts the sign bit in the vacated bit position. The contents of $s_reg1 specifies the value to shift, and the contents of $s_reg2 or the immediate value specifies the number of bits to shift. If $s_reg2 or the immediate value is greater than 63 or less than zero, $s_reg1 shifts by the result of the following AND operation: $s_reg2 AND 63.


Compare Signed Quadword Equal (cmpeq)

Syntax

cmpeq	$s_reg1, $s_reg2, $d_reg
cmpeq	$d_reg/$s_reg1, $s_reg2
cmpeq	$s_reg1, val_immed, $d_reg
cmpeq	$d_reg/$s_reg1, val_immed
Description

Compare Signed Quadword Equal compares two 64-bit values. If the contents of $s_reg1 equals the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1; otherwise, it sets the destination register to zero.


Compare Signed Quadword Less Than (cmplt)

Syntax

cmplt	$s_reg1, $s_reg2, $d_reg
cmplt	$d_reg/$s_reg1, $s_reg2
cmplt	$s_reg1, val_immed, $d_reg
cmplt	$d_reg/$s_reg1, val_immed
Description

Compare Signed Quadword Less Than compares two signed 64-bit values. If the contents of $s_reg1 is less than the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1; otherwise, it sets the destination register to zero.


Compare Signed Quadword Less Than or Equal (cmple)

Syntax

cmple	$s_reg1, $s_reg2, $d_reg
cmple	$d_reg/$s_reg1, $s_reg2
cmple	$s_reg1, val_immed, $d_reg
cmple	$d_reg/$s_reg1, val_immed
Description

Compare Signed Quadword Less Than or Equal compares two signed 64-bit values. If the contents of $s_reg1 is less than or equal to the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1. Otherwise, the destination register is set to zero.


Compare Unsigned Quadword Less Than (cmpult)

Syntax

cmpult	$s_reg1, $s_reg2, $d_reg
cmpult	$d_reg/$s_reg1, $s_reg2
cmpult	$s_reg1, val_immed, $d_reg
cmpult	$d_reg/$s_reg1, val_immed
Description

Compare Unsigned Quadword Less Than compares two unsigned 64-bit values. If the contents of $s_reg1 is less than the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1. Otherwise, the destination register is set to zero.


Compare Unsigned Quadword Less Than or Equal (cmpule)

Syntax

cmpule	$s_reg1, $s_reg2, $d_reg
cmpule	$d_reg/$s_reg1, $s_reg2
cmpule	$s_reg1, val_immed, $d_reg
cmpule	$d_reg/$s_reg1, val_immed
Description

Compare Unsigned Quadword Less Than or Equal compares two unsigned 64-bit values. If the contents of $s_reg1 is less than or equal to the contents of $s_reg2 or the immediate value, this instruction sets the destination register to 1. Otherwise, the destination register is set to zero.


Move (mov)

Syntax

mov	$s_reg, $d_reg
mov	val_immed, d_reg2
Description

Move moves the contents of the source register or the immediate value to the destination register.


Move if Equal to Zero (cmoveq)

Syntax

cmoveq	$s_reg1, $s_reg2, $d_reg
cmoveq	$d_reg/$s_reg1, $s_reg2
cmoveq	$s_reg1, val_immed, $d_reg
cmoveq	$d_reg/$s_reg1, val_immed
Description

Move if Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is equal to zero.


Move if Not Equal to Zero (cmovne)

Syntax

cmovne	$s_reg1, $s_reg2, $d_reg
cmovne	$d_reg/$s_reg1, $s_reg2
cmovne	$s_reg1, val_immed, $d_reg
cmovne	$d_reg/$s_reg1, val_immed
Description

Move if Not Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is not equal to zero.


Move if Less Than Zero (cmovlt)

Syntax

cmovlt	$s_reg1, $s_reg2, $d_reg
cmovlt	$d_reg/$s_reg1, $s_reg2
cmovlt	$s_reg1, val_immed, $d_reg
cmovlt	$d_reg/$s_reg1, val_immed
Description

Move if Less Than Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is less than zero.


Move if Less Than or Equal to Zero (cmovle)

Syntax

cmovle	$s_reg1, $s_reg2, $d_reg
cmovle	$d_reg/$s_reg1, $s_reg2
cmovle	$s_reg1, val_immed, $d_reg
cmovle	$d_reg/$s_reg1, val_immed
Description

Move if Less Than or Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is less than or equal to zero.


Move if Greater Than Zero (cmovgt)

Syntax

cmovgt	$s_reg1, $s_reg2, $d_reg
cmovgt	$d_reg/$s_reg1, $s_reg2
cmovgt	$s_reg1, val_immed, $d_reg
cmovgt	$d_reg/$s_reg1, val_immed
Description

Move if Greater Than Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is greater than zero.


Move if Greater Than or Equal to Zero (cmovge)

Syntax

cmovge	$s_reg1, $s_reg2, $d_reg
cmovge	$d_reg/$s_reg1, $s_reg2
cmovge	$s_reg1, val_immed, $d_reg
cmovge	$d_reg/$s_reg1, val_immed
Description

Move if Greater Than or Equal to Zero moves the contents of $s_reg2 or the immediate value to the destination register if the contents of $s_reg1 is greater than or equal to zero.


Move if Low Bit Clear (cmovlbc)

Syntax

cmovlbc	$s_reg1, $s_reg2, $d_reg
cmovlbc	$d_reg/$s_reg1, $s_reg2
cmovlbc	$s_reg1, val_immed, $d_reg
cmovlbc	$d_reg/$s_reg1, val_immed
Description

Move if Low Bit Clear moves the contents of $s_reg2 or the immediate value to the destination register if the low-order bit of $s_reg1 is equal to zero.


Move if Low Bit Set (cmovlbs)

Syntax

cmovlbs	$s_reg1, $s_reg2, $d_reg
cmovlbs	$d_reg/$s_reg1, $s_reg2
cmovlbs	$s_reg1, val_immed, $d_reg
cmovlbs	$d_reg/$s_reg1, val_immed
Description

Move if Low Bit Set moves the contents of $s_reg2 or the immediate value to the destination register if the low-order bit of $s_reg1 is not equal to zero.


Branch if Equal to Zero (beq)

Syntax

beq	$s_reg, label
Description

Branch if Equal to Zero branches to the specified label if the contents of the source register is equal to zero.


Branch if Not Equal to Zero (bne)

Syntax

bne	$s_reg, label
Description

Branch if Not Equal to Zero branches to the specified label if the contents of the source register is not equal to zero.


Branch if Less Than Zero (blt)

Syntax

blt	$s_reg, label
Description

Branch if Less Than Zero branches to the specified label if the contents of the source register is less than zero. The comparison treats the source register as a signed 64-bit value.


Branch if Less Than or Equal to Zero (ble)

Syntax

ble	$s_reg, label
Description

Branch if Less Than or Equal to Zero branches to the specified label if the contents of the source register is less than or equal to zero. The comparison treats the source register as a signed 64-bit value.


Branch if Greater Than Zero (bgt)

Syntax

bgt	$s_reg, label
Description

Branch if Greater Than Zero branches to the specified label if the contents of the source register is greater than zero. The comparison treats the source register as a signed 64-bit value.


Branch if Greater Than or Equal to Zero (bge)

Syntax

bge	$s_reg, label
Description

Branch if Greater Than or Equal to Zero branches to the specified label if the contents of the source register is greater than or equal to zero. The comparison treats the source register as a signed 64-bit value.


Branch if Low Bit is Clear (blbc)

Syntax

blbc	$s_reg, label
Description

Branch if Low Bit is Clear branches to the specified label if the low-order bit of the source register is equal to zero.


Branch if Low Bit is Set (blbs)

Syntax

blbs	$s_reg, label
Description

Branch if Low Bit is Set branches to the specified label if the low-order bit of the source register is not equal to zero.


Branch (br)

Syntax

br	$s_reg, label
Description

Branch branches unconditionally to the specified label. If a destination register is specified, the address of the instruction following the br instruction is stored in that register.


Branch to Subroutine (bsr)

Syntax

bsr	$d_reg, label
bsr	label
Description

Branch to Subroutine branches unconditionally to the specified label and stores the return address in the destination register. If a destination register is not specified, register $ra ($26) is used.


Jump (jmp)

Syntax

jmp	$d_reg, ($s_reg), jhint
jmp	$d_reg, ($s_reg)
jmp	($s_reg), jhint
jmp	($s_reg)
jmp	($s_reg), jhint
jmp	$d_reg, address
jmp	address
Description

Jump unconditionally jumps to a specified location. A symbolic address or the source register specifies the target location. If a destination register is specified, the address of the instruction following the jmp instruction is stored in the specified register.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.

See Also

For information about branch prediction logic, see the Alpha AXP Architecture Reference Manual


Jump to Subroutine (jsr)

Syntax

jsr	$d_reg, ($s_reg), jhint
jsr	$d_reg, ($s_reg)
jsr	($s_reg), jhint
jsr	($s_reg)
jsr	($s_reg), jhint
jsr	$d_reg, address
jsr	address
Description

Jump to Subroutine unconditionally jumps to a specified location and stores the return address in the destination register. If a destination register is not specified, register $ra ($26) is used. A symbolic address or the source register specifies the target location. The instruction jsr procname transfers to procname and saves the return address in register $26.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.

See Also

For information about branch prediction logic, see the Alpha AXP Architecture Reference Manual


Return from Subroutine (ret)

Syntax

ret	$d_reg, ($s_reg), rhint
ret	$d_reg, ($s_reg)
ret	$d_reg, rhint
ret	$d_reg
ret	($s_reg), rhint
ret	rhint
ret
Description

Return from Subroutine unconditionally returns from a subroutine. If a destination register is specified, the address of the instruction following the ret instruction is stored in the specified register. The source register contains the return address. If the source register is not specified, register $ra ($26) is used. If a hint is not specified, a hint value of 1 is used.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.

See Also

For information about branch prediction logic, see the Alpha AXP Architecture Reference Manual


Jump to Subroutine Return (jsr_coroutine)

Syntax

jsr_coroutine	$d_reg, ($s_reg), rhint
jsr_coroutine	$d_reg, ($s_reg)
jsr_coroutine	$d_reg, rhint
jsr_coroutine	$d_reg
jsr_coroutine	($s_reg), rhint
jsr_coroutine	rhint
jsr_coroutine
Description

Jump to Subroutine Return unconditionally returns from a subroutine and stores the return address in the destination register. If a destination register is not specified, register $26 ( ra ) is used. The source register contains the target address. If the source register is not specified, register $26 (ra) is used.

All jump instructions (jmp, jsr, ret, jsr_coroutine) perform identical operations. They differ only in hints to possible branch-prediction logic.


Compare Byte Instruction

There is one compare byte instruction.

Compare Byte (cmpbge)

Syntax

cmpbge	$s_reg1, $s_reg2, d_reg
cmpbge	$d_reg/$s_reg1, $s_reg2
cmpbge	$s_reg1, val_immed, $d_reg
cmpbge	$d_reg/$s_reg1, val_immed
Description

Compare Byte performs eight parallel unsigned byte comparisons between corresponding bytes of register $s_reg1 and $s_reg2 or the immediate value. A bit is set in the destination register if a byte in$s_reg1 is greater than or equal to the corresponding byte in $s_reg2 or the immediate value.

The results of the comparisons are stored in the eight low-order bits of the destination register; bit 0 of the destination register corresponds to byte 0 and so forth. The 56 high-order bits of the destination register are cleared.


Extract Byte Low (extbl)

Syntax

extbl	$s_reg1, $s_reg2, $d_reg
extbl	$d_reg/$s_reg1, $s_reg2
extbl	$s_reg1, val_immed, $d_reg
extbl	$d_reg/$s_reg1, val_immed
Description

Extract Byte Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the low-order byte into the destination register. The seven high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Extract Word Low (extwl)

Syntax

extwl	$s_reg1, $s_reg2, $d_reg
extwl	$d_reg/$s_reg1, $s_reg2
extwl	$s_reg1, val_immed, $d_reg
extwl	$d_reg/$s_reg1, val_immed
Description

Extract Word Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the two low-order bytes and stores them in the destination register. The six high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Extract Longword Low (extll)

Syntax

extll	$s_reg1, $s_reg2, $d_reg
extll	$d_reg/$s_reg1, $s_reg2
extll	$s_reg1, val_immed, $d_reg
extll	$d_reg/$s_reg1, val_immed
Description

Extract Longword Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the four low-order bytes and stores them in the destination register. The four high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Extract Quadword Low (extql)

Syntax

extql	$s_reg1, $s_reg2, $d_reg
extql	$d_reg/$s_reg1, $s_reg2
extql	$s_reg1, val_immed, $d_reg
extql	$d_reg/$s_reg1, val_immed
Description

Extract Quadword Low shifts the register $s_reg1 right by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts all eight bytes and stores them in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the shift count.


Extract Word High (extwh)

Syntax

extwh	$s_reg1, $s_reg2, $d_reg
extwh	$d_reg/$s_reg1, $s_reg2
extwh	$s_reg1, val_immed, $d_reg
extwh	$d_reg/$s_reg1, val_immed
Description

Extract Word High shifts the register $s_reg1 left by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the two low-order bytes and stores them in the destination register. The six high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Extract Longword High (extlh)

Syntax

extlh	$s_reg1, $s_reg2, $d_reg
extlh	$d_reg/$s_reg1, $s_reg2
extlh	$s_reg1, val_immed, $d_reg
extlh	$d_reg/$s_reg1, val_immed
Description

Extract Longword High shifts the register $s_reg1 left by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts the four low-order bytes and stores them in the destination register. The four high-order bytes of the destination register are cleared to zeros. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Extract Quadword High (extqh)

Syntax

extqh	$s_reg1, $s_reg2, $d_reg
extqh	$d_reg/$s_reg1, $s_reg2
extqh	$s_reg1, val_immed, $d_reg
extqh	$d_reg/$s_reg1, val_immed
Description

Extract Quadword High shifts the register $s_reg1 left by 0-7 bytes, inserts zeros into the vacated bit positions, and then extracts all eight bytes and stores them in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the shift count.


Insert Byte Low (insbl)

Syntax

insbl	$s_reg1, $s_reg2, $d_reg
insbl	$d_reg/$s_reg1, $s_reg2
insbl	$s_reg1, val_immed, $d_reg
insbl	$d_reg/$s_reg1, val_immed
Description

Insert Byte Low shifts the register $s_reg1 left by 0-7 bytes, inserts the byte into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Insert Word Low (inswl)

Syntax

inswl	$s_reg1, $s_reg2, $d_reg
inswl	$d_reg/$s_reg1, $s_reg2
inswl	$s_reg1, val_immed, $d_reg
inswl	$d_reg/$s_reg1, val_immed
Description

Insert Word Low shifts the register $s_reg1 left by 0-7 bytes, inserts the word into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Insert Longword Low (insll)

Syntax

insll	$s_reg1, $s_reg2, $d_reg
insll	$d_reg/$s_reg1, $s_reg2
insll	$s_reg1, val_immed, $d_reg
insll	$d_reg/$s_reg1, val_immed
Description

Insert Longword Low shifts the register $s_reg1 left by 0-7 bytes, inserts the longword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Insert Quadword Low (insql)

Syntax

insql	$s_reg1, $s_reg2, $d_reg
insql	$d_reg/$s_reg1, $s_reg2
insql	$s_reg1, val_immed, $d_reg
insql	$d_reg/$s_reg1, val_immed
Description

Insert Quadword Low shifts the register $s_reg1 left by 0-7 bytes, inserts the quadword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Insert Word High (inswh)

Syntax

inswh	$s_reg1, $s_reg2, $d_reg
inswh	$d_reg/$s_reg1, $s_reg2
inswh	$s_reg1, val_immed, $d_reg
inswh	$d_reg/$s_reg1, val_immed
Description

Insert Word High shifts the register $s_reg1 right by 0-7 bytes, inserts the word into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Insert Longword High (inslh)

Syntax

inslh	$s_reg1, $s_reg2, $d_reg
inslh	$d_reg/$s_reg1, $s_reg2
inslh	$s_reg1, val_immed, $d_reg
inslh	$d_reg/$s_reg1, val_immed
Description

Insert Longword High shifts the register $s_reg1 right by 0-7 bytes, inserts the longword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Insert Quadword High (insqh)

Syntax

insqh	$s_reg1, $s_reg2, $d_reg
insqh	$d_reg/$s_reg1, $s_reg2
insqh	$s_reg1, val_immed, $d_reg
insqh	$d_reg/$s_reg1, val_immed
Description

Insert Quadword High shifts the register $s_reg1 right by 0-7 bytes, inserts the quadword into a field of zeros, and then puts the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the byte shift count.


Mask Byte Low (mskbl)

Syntax

mskbl	$s_reg1, $s_reg2, $d_reg
mskbl	$d_reg/$s_reg1, $s_reg2
mskbl	$s_reg1, val_immed, $d_reg
mskbl	$d_reg/$s_reg1, val_immed
Description

Mask Byte Low sets a byte in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the offset of the byte.


Mask Word Low (mskwl)

Syntax

mskwl	$s_reg1, $s_reg2, $d_reg
mskwl	$d_reg/$s_reg1, $s_reg2
mskwl	$s_reg1, val_immed, $d_reg
mskwl	$d_reg/$s_reg1, val_immed
Description

Mask Word Low sets a word in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the offset of the word.


Mask Longword Low (mskll)

Syntax

mskll	$s_reg1, $s_reg2, $d_reg
mskll	$d_reg/$s_reg1, $s_reg2
mskll	$s_reg1, val_immed, $d_reg
mskll	$d_reg/$s_reg1, val_immed
Description

Mask Longword Low sets a longword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the offset of the longword.


Mask Quadword Low (mskql)

Syntax

mskql	$s_reg1, $s_reg2, $d_reg
mskql	$d_reg/$s_reg1, $s_reg2
mskql	$s_reg1, val_immed, $d_reg
mskql	$d_reg/$s_reg1, val_immed
Description

Mask Quadword Low sets a quadword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the offset of the quadword.


Mask Word High (mskwh)

Syntax

mskwh	$s_reg1, $s_reg2, $d_reg
mskwh	$d_reg/$s_reg1, $s_reg2
mskwh	$s_reg1, val_immed, $d_reg
mskwh	$d_reg/$s_reg1, val_immed
Description

Mask Word High sets a word in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the offset of the word.


Mask Longword High (msklh)

Syntax

msklh	$s_reg1, $s_reg2, $d_reg
msklh	$d_reg/$s_reg1, $s_reg2
msklh	$s_reg1, val_immed, $d_reg
msklh	$d_reg/$s_reg1, val_immed
Description

Mask Longword High sets a longword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the offset of the longword.


Mask Quadword High (mskqh)

Syntax

mskqh	$s_reg1, $s_reg2, $d_reg
mskqh	$d_reg/$s_reg1, $s_reg2
mskqh	$s_reg1, val_immed, $d_reg
mskqh	$d_reg/$s_reg1, val_immed
Description

Mask Quadword High sets a quadword in register $s_reg1 to zero and stores the result in the destination register. Bits 0-2 of register $s_reg2 or the immediate value specify the offset of the quadword.


Zero Bytes (zap)

Syntax

zap	$s_reg1, $s_reg2, $d_reg
zap	$d_reg/$s_reg1, $s_reg2
zap	$s_reg1, val_immed, $d_reg
zap	$d_reg/$s_reg1, val_immed
Description

Zero Bytes sets selected bytes of register $s_reg1 to zero and puts the result in the destination register. Bits 0-7 of register $s_reg2 or an immediate value specify the bytes to be cleared to zeros. Each bit corresponds to one byte in register $s_reg1; for example, bit 0 corresponds to byte 0. A bit with a value of 1 indicates its corresponding byte should be cleared to zeros.


Zero Bytes NOT (zapnot)

Syntax

zapnot	$s_reg1, $s_reg2, $d_reg
zapnot	$d_reg/$s_reg1, $s_reg2
zapnot	$s_reg1, val_immed, $d_reg
zapnot	$d_reg/$s_reg1, val_immed
Description

Zero Bytes NOT sets selected bytes of register $s_reg1 to zero and puts the result in the destination register. Bits 0-7 of register $s_reg2 or an immediate value specify the bytes to be cleared to zeros. Each bit corresponds to one byte in register $s_reg1; for example, bit 0 corresponds to byte 0. A bit with a value of zero indicates its corresponding byte should be cleared to zeros.


Call Privileged Architecture Library (call_pal)

Syntax

call_pal	palcode
Description

Call Privileged Architecture Library unconditionally transfers control to the exception handler. The palcode operand is interpreted by software conventions.


Prefetch Data (fetch)

Syntax

fetch	address
Description

Prefetch Data indicates that the 512-byte block of data specified by the effective address should be moved to a faster-access part of the memory hierarchy.


Prefetch Data, Modify Intent (fetch_m)

Syntax

fetch_m	address
Description

Prefetch Data indicates that the 512-byte block of data specified by the effective address should be moved to a faster-access part of the memory hierarchy. In addition, this instruction is a hint that part or all of the data may be modified.


Read Process Cycle Counter (rpcc)

Syntax

rpcc	address
Description

Read Process Cycle Counter returns the contents of the process cycle counter in the destination register.


No Operation (nop)

Syntax

nop

Description

No Operation has no effect on the machine state.


Universal No Operation (unop)

Syntax

unop

Description

Universal No Operation has no effect on the machine state.


Trap Barrier (trapb)

Syntax

trapb

Description

Trap Barrier guarantees that all previous arithmetic instructions complete, without incurring any arithmetic traps, before any instructions after the trapb instruction are issued.


Exception Barrier (excb)

Syntax

excb

Description

Exception Barrier guarantees that all previous instructions complete any exception-related behavior or rounding-mode behavior before any instructions after the excb instruction are issued.


Memory Barrier (mb)

Syntax

mb

Description

Memory Barrier is used to serialize access to memory.

See Also

For information on memory barriers, see the Alpha AXP Architecture Reference Manual


Write Memory Barrier (wmb)

Syntax

wmb

Description

Write Memory Barrier guarantees that all previous store instructions access memory before any store instructions issued after the wmb instruction.