Version 7.2

The bootable version of the Intel® Processor Frequency ID Utility is available in .exe format. This download does not work in DOS-emulation windows, as found in operating systems such as Linux*. Since this version is bootable, it does not depend on any specific operating system (OS independent).

See the Installation Guide for detailed instructions on how to use this utility.

Which Utility Should I Use?
For Intel® Pentium® III processors, and processors manufactured before the Intel® Pentium® III processor, use the Intel® Processor Frequency ID Utility.

Version 7.2

The utility is available for download in a self-installing .msi file format.

• Supported Processors
• Supported Operating Systems

• Proper Intel® processor brand identification
• Processor and system bus expected frequencies
• Processor and system bus reported frequencies
• Accompanying this information is a message informing the user whether the processor is operating at its expected frequency
• Which processor was tested in a multiprocessor system, and total number of processors (Windows* XP, and Windows* 2000 only)

The CPUID Utility for Windows* is incorporated into the Intel® Processor Frequency ID Utility.

Use the CPUID Data Screen of the utility to identify Pentium® processors and higher.

• Windows 98* SE
• Windows 2000* Professional, Server, Advanced Server
• Windows Me*
• Windows XP*

Floating Point Unit (FPU) exception hander information for Intel® processors is available in the following documents:

Application note AP-578, Software and Hardware Considerations for FPU Exception Handlers for Intel® Architecture Processors, Intel® Document #243291. This application note provides information to help software engineers write the most robust Floating-Point Unit (FPU) exception handlers possible.

Also see the Intel® Pentium® Processor Family Developer's Manual, Volume 3, Intel® Document #241430, contains three chapters about programming the floating point unit, including one chapter dedicated to programming examples.

Also see the Intel® Architecture Software Developer's Manual, Volume 1: Basic Architecture, Intel® Document #243190, Chapter 7 and Appendix C.

Micro-FCPGA
The micro-FCPGA (Flip Chip Plastic Grid Array) package consists of a die placed face-down on an organic substrate. An epoxy material surrounds the die, forming a smooth, relatively clear fillet. The package uses 478 pins, which are 2.03 mm long and .32 mm in diameter. While there are several micro-FCPGA socket designs available, all of them are designed to allow zero-insertion force removal and insertion of the processor. Different from micro-PGA, the micro-FCPGA does not have an interposer and it includes capacitors on the bottom side.

Photo examples
(Front side) (Back side)

Micro-FCBGA
Micro-FCBGA (Flip Chip Ball Grid Array) package for surface mount boards consists of a die placed face-down on an organic substrate. An epoxy material surrounds the die, forming a smooth, relatively clear fillet. Instead of using pins, the packages use small balls which act as contacts for the processor. The advantage of using balls instead of pins is that there are no leads that bend. The package uses 479 balls, which are .78 mm in diameter. Different from Micro-PGA, the micro-FCPGA includes capacitors on the top side.

Photo examples
(Front side) (Back side)

Micro-BGA2 package
The BGA2 package consists of a die placed face-down on an organic substrate. An epoxy material surrounds the die, forming a smooth, relatively clear fillet. Instead of using pins, the packages use small balls which act as contacts for the processor. The advantage of using balls instead of pins is that there are no leads that bend. The Pentium® III processor uses the BGA2 package, which includes 495 balls.

Photo examples
(Front side) (Back side)

Micro-PGA2 package
The micro-PGA2 consists of a BGA package mounted to an interposer with small pins. The pins are 1.25 mm long and 0.30 mm in diameter. While there are several micro-PGA2 socket designs available, all of them are designed to allow zero-insertion force removal and insertion of the mobile Pentium III processor.

Photo examples
(Front side) (Back side)

MMC-2 package
The Mobile Module Cartridge 2 (MMC-2) package has a mobile Pentium® III processor and the host bridge system controller (consisting of the processor bus controller, memory controller, and PCI bus controller) on a small circuit. It connects to the system via a 400-pin connector. On the MMC-2 package, the thermal transfer plate (TTP) provides heat dissipation from the processor and host bridge system controller.

Photo examples
(Front side) (Back side)

Product order codes for the Mobile Intel® Pentium® III Processor can be found by searching the processor products database.

What is the Difference Between:

• Micro-PGA2 and Micro-FCPGA packages?
• BGA-2 and other package types for Mobile Intel® Processors?

1. There are no multi-packs for the BGA2 and micro-PGA2
2. The part number for the MMC-2 packages are for stepping B. Stepping A would have MPM22CGAxxxX instead of MPM22CGBxxxX and MPM22CUAxxxX instead of MPM22CUAxxxX.
3. Low-voltage (1.35 V/1.10 V)
4. Ultra-low voltage (1.1 V/0.975 V)
5. Low-voltage (1.15 V/1.05 V) based on .13µ process technology.
6. Ultra-Low voltage (1.1V/0.95 V) based on .13µ process technology
7. This processor features a 100 MHz system bus

The Low Voltage Mobile Intel Pentium Processor will support both a 133-MHz and a 100-MHz bus speed. The Ultra Low Voltage Mobile Intel Pentium Processor will support both 133-MHz and 100-MHz (see product features section for specific supported frequencies) bus speed. The Low Voltage and Ultra Low Voltage notebook processors will be available only in the Micro-FCBGA package. All of these technologies make outstanding performance possible for mobile PCs in a variety of shapes and sizes.

The processor, when used in conjunction with the Intel SpeedStep® technology applet, supports Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes based on CPU demand. This occurs by switching the bus ratios, core operating voltage, and core processor speeds without resetting the system. The processor also features a new ultra low power state called Deeper Sleep.

The 512-kB integrated L2 cache based on the Advanced Transfer Cache architecture runs at full speed and is designed to help improve performance. It complements the system bus by providing critical data faster and reducing total system power consumption. The processor also features Data Prefetch Logic that speculatively fetches data to the L2 cache, resulting in improved performance. The Mobile Intel® Pentium® Processor's 64-bit wide Assisted Gunning Transceiver Logic (AGTL) system bus provides a glue-less, point-to-point interface for a memory controller hub.

This document covers the electrical, mechanical, and thermal specifications for the following:

• The Mobile Intel Pentium Processor is offered at the following frequencies and voltages (Maximum Performance mode/Battery Optimized mode): 1.333 GHz/800 MHz, 1.266 GHz/800 MHz, 1.200 GHz/800 MHz, 1.133 GHz/733 MHz, 1.066 GHz/733 MHz, and 1.000 GHz/733 MHz at 1.40 V/1.15 V.
• The Low Voltage Mobile Intel Pentium Processor is offered at the following frequencies and voltages (Maximum Performance mode/Battery Optimized mode): 1.00 GHz/533 MHz, 933/533 MHz, 866/533 MHz, 800/533 MHz, 850/500 MHz, and 800A/500 MHz at 1.15 V/1.05 V.
• The Ultra Low Voltage Mobile Intel Pentium Processor is offered at the following frequency and voltage (Maximum Performance mode/Battery Optimized mode): 933/400 MHz, 900/400 MHz, 866/400 MHz, 850/400 MHz, 800/400 MHz at 1.10 V/0.95 V.

Unless explicitly stated, all references to the Mobile Intel Pentium Processor in this document also apply to the Low Voltage and Ultra Low Voltage Mobile Intel Pentium Processor.

	Mobile Intel Pentium Processor Datasheet
	File Name: 29834006.pdf Size: 1981079 bytes

• Mobile Intel® Pentium® III Processor-M datasheet (298340-002)
• Mobile Pentium® III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz, 900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low Voltage 750 MHz, Low Voltage 700 MHz, Low voltage 600 MHz, Ultra Low Voltage 600 MHz and Ultra Low Voltage 500 MHz datasheet (Order Number 283653-002)
• Pentium® III Processor Mobile Module Connector 2 (MMC2) datasheet (Order Number 245304)
• Pentium® III Processor Mobile Module: Mobile Module Connector 2 (MMC2) Featuring Intel® SpeedStep™ Technology datasheet (Order Number 243356-06)
• Intel Architecture Software Developer's Manual, Volumes 1, 2, and 3 (Order Numbers 243190, 243191, and 243192, respectively).
• P6 Family of Processors Hardware Developer's Manual (Order Number 244001)
• Intel® Pentium® III Processor - Low Power Datasheet (Order Number 273500-02)

This document is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. It contains Errata, Documentation Changes, Specification Clarifications, and Specification Changes.

	Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update
	File Name: 24530659.pdf Size: 543514 bytes

The following older processor families are no longer supported through interactive support such as phone, e-mail, or chat.

Intel will maintain information for these processors on our web site. You can access these processor family Web sites by clicking on the links under the processor column.

Intel® processors since the Intel386™ processor can run one of three modes. They are the Real mode, Protected mode and SMM mode. You can also add a fourth mode called Virtual 8088 mode, which is considered a pseudo mode of the protected mode.

When the processor starts booting the computer, the processor starts in real mode where it operates like a 8086 processor that can see up to 1 MB of RAM.

The native mode for the processor is the Protected mode which it will switch into while it loads Windows* or some other advanced operating system. While in protected mode, the processor uses segmented (non-linear) addressing, as opposed to linear addressing.

Segmented addressing means that memory (physical memory and virtual memory) is divided into 64K blocks. This is the maximum value for the Instruction Pointer (IP) register. The IP register works with the Code Segment (CS) register to point to the memory location from where the microprocessor should fetch its next instruction. The IP uses 4 bytes for memory addressing, therefore making 0FFFFH the maximum memory location (0FFFFH = 64K).