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Part Checklist Rev:2
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Assigned LIB Owner:
Required Sections:


SE Requestor:
NEAL OUCHI
SE Phone:
(480) 554-3706
Date Requested:
6/13/2007
Date Required:
6/20/2007


Concept Name:
Library Folder:
Assigned CAD:
Alternate Contact:


Manufacture Name:
Manufacture P/N:
Intel P/N - RoHS:
Project Name:
Intel Silicon


Allegro Name:
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Allegro File:
Other Files:
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Previous Comments:
NKOUCHI (6/13/2007):
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CAD Last Updated:


 
Logic Part
LIB SE CAD  
  Verify All device pins are represented in the symbol(s), No Embedded PWR/GND/NC Pins
  Verify pin name/pin number against datasheet or CPD (double-click pin to view properties).
  Verify PART_NUMBER exists, and the value is NOT invisible.
  Verify $LOCATION (ref des) field exists, and that the Reference Designator is acceptable for this component and conforms to DFx Rule 1215 and the value is visible
  Verify 'PACK_TYPE' field exists and it is correct for this component
  Verify a ‘Value’ field exists in the component attribute window and Value and Units are correct (discretes only).
  Verify a ‘Rating’ field exists in the component attribute window and Rating and Units are correct (discretes only).
  Verify a ‘Tolerance’ field exists in the component attribute window and Tolerance is correct (discretes only).
  Verify pin mapping and pin/gate swapping (multi-device packages only) against datasheet or CPD.
  Verify there is an Empty and Stuff options created
  Verify symbol can be added to dummy schematic page, versioned, sectioned, and packaged.
 
Part Table
LIB SE CAD  
  Verify a component description is acceptable in the Description field (SPEED description if available).
  Verify Package Type is acceptable for this component.
  Verify Values, Tolerances, etc. is acceptable for this component.
  Verify JEDEC_Type is assigned and acceptable for this component.
 
Physical Part
LIB SE CAD  
  Verify a component Height properties field exists and value represents maximum height for this component.
  Verify component rotation conforms to DFx (DFx land pattern always shown in 0 degrees rotation).
    Verify Component/Padstack names conform to the appropriate SPS/HAD naming convention BKM.
Verify Pin number sequence, (consult DE if there is ambiguity).
  Verify pin-to-pin spacing (X-axis) per DFx/datasheet.
  Verify pin-to-pin spacing (Y-axis) per DFx/datasheet.
  Verify Assembly Outline reflects the maximum component dimensions.
  Verify Silkscreen Outline(s) and Cosmetic Graphics conform to DFx shape and graphics requirements.
  Verify Silkscreen and Assembly Reference Designator fields exist and conform to DFx Rule 1212. (REFDES may be denoted as "*" only).
    Verify part may be packaged with the logic symbol and placed in dummy .brd file.
  Verify Placement Outline (Place_bound_top) extends to outer edges of Assembly Outline, mounting holes, and/or pads (rule of thumb is 12.5 mils past the component edge)
  Verify that the origin of the part (0,0) is in the geometric center for SMT and TH parts except connectors where pin 1 is the orgin
  Verify that a route keepout exists around all non-plated holes. This should be a minimum of 10 mils greater than the hole on each side.
Name: MYERS, GARY C Phone #: 480-554-0449 WWID: 10077065