Part Request
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Part Checklist Rev:2
Update Part Request
Assigned LIB Owner:
[Choose:]
MYERS, GARY
NGUYEN, HOI
Required Sections:
Logic Part
Part Table
Physical Part
CAD
SE Requestor:
NEAL OUCHI
SE Phone:
(480) 554-3706
Date Requested:
6/13/2007
Date Required:
6/20/2007
Concept Name:
Library Folder:
[Choose:]
74xx
analog
conn
digital
discrete
dwg_sym
for_review_only
memory
socket
Assigned CAD:
[Choose:]
APONOWICH, WALLACE
ASPNES, BRIAN
AVERY, DAN
BERG, DANIEL
BLAKE, MARK
BRIGHT, VINCENT
BRUSS, ELIZABETH
CARLSON, CHRISTOPHER
CHAN, SWEE TAT
CHU, LINDA
CRAVATTA, SAMUEL
DALEY, BRIAN
DALY, JEFFREY
DRAUT, JOHN
DU, MIN
DURAZO, PAUL
EDWARDS, KEVIN
EDWARDS, KEITH
EDWARDS, ERIC
ELAYDA, JAY
EW, CHEE YONG
GLEY, MICHAEL
GOH, KEAT HOE
GOSAR, MATTHEW
GRIFFIN, SEAN
HANDLEY, WILLIAM
HASWAREY, MUSTAFA
HASWAREY, ASLAM
HERD, KENT
HEYER, CARLTON
IWAMOTO, JOHN
JEE, USHA
JENSEN, BRIAN
JIMENEZ, LOMBERTO
JOHNSON, STEVEN
KANN, JAMES
KASPER, MICHAEL
KATIRCIOGLU, HALUK
KHOO, YEN YEN
KONGKITISUPCHAI, PITI
KRUG JR, DONALD
LAMOREAUX, RAY
LANGLEY, TODD
LAU, WAI SHIN
LEE, CHEE HOW
LIAW, WAI KIT
LIM, JIN CHONG
LIM, LIONG-HUAT
LLOYD, STEVEN
LOCK, KING HENG
LOH, YUEN FATT
LOW, JERRY WENG HAI
MADHIRA, SATYANARAYANA
MCANDREW, JOHN
MCBRIDE, MELANIE
MCMATH, SCOTT
MEHR JR, LLOYD
MERCADO, EDWIN
MILLER, CAROL
MOGALI, MADHU
MORALES, LYNN
MORRISON, MICHAEL
MYERS, GARY
NGUYEN, HOI
NGUYEN, HOAIBAO
OOI, BAN KEOW
OUCHI, NEAL
PANCHANATHAN, BALASUBRAMANIAN
PASQUINO, ANTHONY
PULKOWSKI, THOMAS
RAHMATULLAH, NAVEID
RAJA GOPAL, R SELVAKUMAR
SANDGATHE, JOEL
SAPRA, ASHISH
SARUWATARI, STAN
SEIFERT, BRIAN
SISOMMOUT, THONGONE
SONG, WIL CHOON
STANDRIDGE, MYLES
STEIGERWALD, SARA
SZWAGLIS, STANISLAW
TANG, MIN KEEN
THARMARAJAH, KANAGARATNAM
TSAO, JEFFREY
VARNUM, ROBERT
VORA, CHANDRA
WROBEL, JOSEPH
XIONG, YE
YOUSUF, MUSTAFA
YU, BO
YU, TEIK BENG
Alternate Contact:
[Choose:]
APONOWICH, WALLACE
ASPNES, BRIAN
AVERY, DAN
BERG, DANIEL
BLAKE, MARK
BRIGHT, VINCENT
BRUSS, ELIZABETH
CARLSON, CHRISTOPHER
CHAN, SWEE TAT
CHU, LINDA
CRAVATTA, SAMUEL
DALEY, BRIAN
DALY, JEFFREY
DRAUT, JOHN
DU, MIN
DURAZO, PAUL
EDWARDS, KEVIN
EDWARDS, KEITH
EDWARDS, ERIC
ELAYDA, JAY
EW, CHEE YONG
GLEY, MICHAEL
GOH, KEAT HOE
GOSAR, MATTHEW
GRIFFIN, SEAN
HANDLEY, WILLIAM
HASWAREY, MUSTAFA
HASWAREY, ASLAM
HERD, KENT
HEYER, CARLTON
IWAMOTO, JOHN
JEE, USHA
JENSEN, BRIAN
JIMENEZ, LOMBERTO
JOHNSON, STEVEN
KANN, JAMES
KASPER, MICHAEL
KATIRCIOGLU, HALUK
KHOO, YEN YEN
KONGKITISUPCHAI, PITI
KRUG JR, DONALD
LAMOREAUX, RAY
LANGLEY, TODD
LAU, WAI SHIN
LEE, CHEE HOW
LIAW, WAI KIT
LIM, JIN CHONG
LIM, LIONG-HUAT
LLOYD, STEVEN
LOCK, KING HENG
LOH, YUEN FATT
LOW, JERRY WENG HAI
MADHIRA, SATYANARAYANA
MCANDREW, JOHN
MCBRIDE, MELANIE
MCMATH, SCOTT
MEHR JR, LLOYD
MERCADO, EDWIN
MILLER, CAROL
MOGALI, MADHU
MORALES, LYNN
MORRISON, MICHAEL
MYERS, GARY
NGUYEN, HOI
NGUYEN, HOAIBAO
OOI, BAN KEOW
OUCHI, NEAL
PANCHANATHAN, BALASUBRAMANIAN
PASQUINO, ANTHONY
PULKOWSKI, THOMAS
RAHMATULLAH, NAVEID
RAJA GOPAL, R SELVAKUMAR
SANDGATHE, JOEL
SAPRA, ASHISH
SARUWATARI, STAN
SEIFERT, BRIAN
SISOMMOUT, THONGONE
SONG, WIL CHOON
STANDRIDGE, MYLES
STEIGERWALD, SARA
SZWAGLIS, STANISLAW
TANG, MIN KEEN
THARMARAJAH, KANAGARATNAM
TSAO, JEFFREY
VARNUM, ROBERT
VORA, CHANDRA
WROBEL, JOSEPH
XIONG, YE
YOUSUF, MUSTAFA
YU, BO
YU, TEIK BENG
Manufacture Name:
Manufacture P/N:
Intel P/N - RoHS:
Project Name:
AGATE_BRIDGE
CAPE MEARS
COOK FOREST
HAXTON
HERMOSA CREEK
OSAGE
TIONESTA
TRUXTON
UNION TOWN
WILLIAMSPORT
Intel Silicon
No
Yes
Allegro Name:
Edit Allegro Link:
[Choose:]
30BQ015PBF.pdf
59PR9873.pdf
602433-075_jdjmkc1.pdf
656554-043_jebk1c1.pdf
9DB803.pdf
9FGP202.pdf
A91829-027_G2100C888-XXXX-B4.pdf
A93548-498_dcrcwe3.pdf
A93549-008_dcrcwe3.pdf
C1005C0G1H1.pdf
C1005C0G1H3.pdf
C35295-003_ENG_CD_1612163_J[1].pdf
C35295-003_ENG_DS_4-1773442-7_1205[1].pdf
C35295-004_ENG_CD_1612163_J[2].pdf
C74115-002_ds11303.pdf
C88705-001_BA%2FBAV99.pdf
C89648-001_DS1818.pdf
C92306-001_71317.pdf
C97278-001_1112h_e[1].pdf
C978278-002_1112h_e[2].pdf
ccog.pdf
Connector_HM3504E-P1.pdf
cra04s.pdf
cx7r_1.pdf
D400101C.pdf
D55839-001_1N5819HW.pdf
D55839-001_CQC for IC D55839-001 Elaina.doc
D55839-001_Diodes 03232006 Ret'd.xls
D78251-002_sn74gtl2107.pdf
D86956-001_MAX5954.pdf
D88783-001_PCA9555BS.pdf
D92964-001_AAA-DDR-100-T02.pdf
dcrcw.pdf
DS1002_machxo.pdf
EEFSX0D331XE .pdf
ENG_CD_1734341_O1[1].pdf
ENG_CD_767171_B2[1].pdf
FDS7296N3.pdf
G2100C888-XXXX.PDF
G3PO.pdf
G3PO_Drawing_OL_SK_2914.pdf
GRM1555C1H121JA01.pdf
GRM1555C1H331JA01.pdf
GRM1555C1H470JZ01.pdf
GRM155R71C104KA88.pdf
GRM155R71H221KA01.pdf
GRM1885C1H221JA01.pdf
GRM188R71C105KA12.pdf
GRM188R71H223KA01.pdf
GRM31CR60J476ME19.pdf
GRM31CR71C106KAC7.pdf
GRM32ER61C226KE20.pdf
HB9603E-K.pdf
Header_Conn_705459039_sd.pdf
INTEL-DHCB1350B-R20-R.pdf
IP4220CZ6_4.pdf
IPN D90404-001_sn74lvc08a.pdf
IPN D90453-001_sn74lvc07a.pdf
IPN D90461-001_sn74lvc14a.pdf
irf7425.pdf
ISL6308.pdf
ISL6314.pdf
isl6327.pdf
ISL6612.pdf
Jasper Ballmap rev -99 latest_052507.xls
jelb2c1.pdf
L0110S0100BLM18B.pdf
L0110S0100BLM21P.pdf
Littelfuse_1206L.pdf
MAX1951-MAX1952.pdf
mic5162.pdf
MMBZ5221BLT1-D.pdf
NC%2FNC7SB3157.pdf
NC%2FNC7SZ66.pdf
NT73.pdf
N_channel_FET_ds30120.pdf
pkg.pdf
PNP_XSTER_MMBT3906.pdf
QH25F64.pdf
QS3VH16233_Datasheet.pdf
QS3VH257_datasheet.pdf
res1.pdf
res23.pdf
res27.pdf
res5.pdf
res7.pdf
RK73B_res1_KOA.pdf
RK73H.pdf
RK73H_res5_KOA.pdf
RT9199.pdf
sc2612e.pdf
SC40XX_SERIES.pdf
sc4215a.pdf
SI4511DY.pdf
si7958dp.pdf
sn74lvc1g07.pdf
sn74lvc1g125.pdf
sn74lvc1g97.pdf
sn74lvc244a.pdf
sn74lvc2g125.pdf
stk800.pdf
stk850.pdf
sts8dnh3ll.pdf
svpc_series.pdf
TI_SN74LV4066A.pdf
tps74801.pdf
TSW_TH.pdf
Voltage_Monitor_ADM803_809_810.pdf
Datasheet:
Click For Datasheet
Allegro File:
Other Files:
Click For Other Files
Previous Comments:
NKOUCHI
(6/13/2007):
Add New Comments:
Part Actions
Choose Action:
[Choose:]
Notify SE
Notify CAD
Reject
Inactivate
Logic Symbol Created
Complete
Reject Reason:
Update Checklist
LIB Last Updated:
SE Last Updated:
CAD Last Updated:
Logic Part
LIB
SE
CAD
Verify All device pins are represented in the symbol(s), No Embedded PWR/GND/NC Pins
Verify pin name/pin number against datasheet or CPD (double-click pin to view properties).
Verify PART_NUMBER exists, and the value is NOT invisible.
Verify $LOCATION (ref des) field exists, and that the Reference Designator is acceptable for this component and conforms to DFx Rule 1215 and the value is visible
Verify 'PACK_TYPE' field exists and it is correct for this component
Verify a ‘Value’ field exists in the component attribute window and Value and Units are correct (discretes only).
Verify a ‘Rating’ field exists in the component attribute window and Rating and Units are correct (discretes only).
Verify a ‘Tolerance’ field exists in the component attribute window and Tolerance is correct (discretes only).
Verify pin mapping and pin/gate swapping (multi-device packages only) against datasheet or CPD.
Verify there is an Empty and Stuff options created
Verify symbol can be added to dummy schematic page, versioned, sectioned, and packaged.
Part Table
LIB
SE
CAD
Verify a component description is acceptable in the Description field (SPEED description if available).
Verify Package Type is acceptable for this component.
Verify Values, Tolerances, etc. is acceptable for this component.
Verify JEDEC_Type is assigned and acceptable for this component.
Physical Part
LIB
SE
CAD
Verify a component Height properties field exists and value represents maximum height for this component.
Verify component rotation conforms to DFx (DFx land pattern always shown in 0 degrees rotation).
Verify Component/Padstack names conform to the appropriate SPS/HAD naming convention BKM.
Verify Pin number sequence, (consult DE if there is ambiguity).
Verify pin-to-pin spacing (X-axis) per DFx/datasheet.
Verify pin-to-pin spacing (Y-axis) per DFx/datasheet.
Verify Assembly Outline reflects the maximum component dimensions.
Verify Silkscreen Outline(s) and Cosmetic Graphics conform to DFx shape and graphics requirements.
Verify Silkscreen and Assembly Reference Designator fields exist and conform to DFx Rule 1212. (REFDES may be denoted as "*" only).
Verify part may be packaged with the logic symbol and placed in dummy .brd file.
Verify Placement Outline (Place_bound_top) extends to outer edges of Assembly Outline, mounting holes, and/or pads (rule of thumb is 12.5 mils past the component edge)
Verify that the origin of the part (0,0) is in the geometric center for SMT and TH parts except connectors where pin 1 is the orgin
Verify that a route keepout exists around all non-plated holes. This should be a minimum of 10 mils greater than the hole on each side.
Name:
MYERS, GARY C
Phone #:
480-554-0449
WWID:
10077065