Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

- Main Page
- Modules
- Data Structures
- Files

- File List

qm_interrupt_router_regs.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __QM_INTERRUPT_ROUTER_REGS_H__
6 #define __QM_INTERRUPT_ROUTER_REGS_H__
7
8 /**
9 * Quark SE SoC Interrupt Router registers.
10 *
11 * @defgroup groupQUARKSEINTERRUPTROUTER SoC Interrupt Router (SE)
12 * @{
13 */
14
15 /**
16 * Masks for single source interrupts in the Interrupt Router.
17 * To enable: reg &= ~(MASK)
18 * To disable: reg |= MASK;
19 */
20 #define QM_IR_INT_LMT_MASK BIT(0)
21 #define QM_IR_INT_SS_MASK BIT(8)
22
23 /* Masks for single source halts in the Interrupt Router. */
24 #define QM_IR_INT_LMT_HALT_MASK BIT(16)
25 #define QM_IR_INT_SS_HALT_MASK BIT(24)
26
27 /**
28 * Interrupt Router macros to determine if the specified peripheral interrupt
29 * mask has been locked.
30 */
31 #define QM_IR_SS_INT_LOCK_HALT_MASK(_peripheral_) \
32 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(3))
33 #define QM_IR_LMT_INT_LOCK_HALT_MASK(_peripheral_) \
34 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(2))
35 #define QM_IR_SS_INT_LOCK_MASK(_peripheral_) \
36 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(1))
37 #define QM_IR_LMT_INT_LOCK_MASK(_peripheral_) \
38 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(0))
39
40 /* Interrupt Router Unmask interrupts for a peripheral. */
41 #define QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_) \
42 (_peripheral_ &= ~(QM_IR_INT_LMT_MASK))
43 #define QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_) \
44 (_peripheral_ &= ~(QM_IR_INT_SS_MASK))
45
46 /* Mask interrupts for a peripheral. */
47 #define QM_IR_MASK_LMT_INTERRUPTS(_peripheral_) \
48 (_peripheral_ |= QM_IR_INT_LMT_MASK)
49 #define QM_IR_MASK_SS_INTERRUPTS(_peripheral_) \
50 (_peripheral_ |= QM_IR_INT_SS_MASK)
51
52 /* Unmask halt for a peripheral. */
53 #define QM_IR_UNMASK_LMT_HALTS(_peripheral_) \
54 (_peripheral_ &= ~(QM_IR_INT_LMT_HALT_MASK))
55 #define QM_IR_UNMASK_SS_HALTS(_peripheral_) \
56 (_peripheral_ &= ~(QM_IR_INT_SS_HALT_MASK))
57
58 /* Mask halt for a peripheral. */
59 #define QM_IR_MASK_LMT_HALTS(_peripheral_) \
60 (_peripheral_ |= QM_IR_INT_LMT_HALT_MASK)
61 #define QM_IR_MASK_SS_HALTS(_peripheral_) \
62 (_peripheral_ |= QM_IR_INT_SS_HALT_MASK)
63
64 #define QM_IR_GET_LMT_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_LMT_MASK)
65 #define QM_IR_GET_LMT_HALT_MASK(_peripheral_) \
66 (_peripheral_ & QM_IR_INT_LMT_HALT_MASK)
67
68 #define QM_IR_GET_SS_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_SS_MASK)
69 #define QM_IR_GET_SS_HALT_MASK(_peripheral_) \
70 (_peripheral_ & QM_IR_INT_SS_HALT_MASK)
71
72 /**
73 * Mailbox Interrupt Mask enable/disable definitions
74 *
75 * \#defines use the channel number to determine the register and bit shift to
76 * use.
77 * The interrupt destination adds an offset to the bit shift.
78 */
79 #define QM_IR_MBOX_ENABLE_LMT_INT_MASK(N) \
80 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
81 ~(BIT(N + QM_MBOX_HOST_MASK_OFFSET))
82 #define QM_IR_MBOX_DISABLE_LMT_INT_MASK(N) \
83 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
84 (BIT(N + QM_MBOX_HOST_MASK_OFFSET))
85 #define QM_IR_MBOX_ENABLE_SS_INT_MASK(N) \
86 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
87 ~(BIT(N + QM_MBOX_SS_MASK_OFFSET))
88 #define QM_IR_MBOX_DISABLE_SS_INT_MASK(N) \
89 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
90 (BIT(N + QM_MBOX_SS_MASK_OFFSET))
91
92 /**
93 * Mailbox Interrupt Halt Mask enable/disable definitions
94 *
95 * \#defines use the channel number to determine the register and bit shift to
96 * use.
97 * The interrupt destination adds an offset to the bit shift,
98 * see above for the bit position layout
99 */
100 #define QM_IR_MBOX_ENABLE_LMT_INT_HALT_MASK(N) \
101 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
102 ~(BIT(N + QM_MBOX_HOST_HALT_MASK_OFFSET))
103 #define QM_IR_MBOX_DISABLE_LMT_INT_HALT_MASK(N) \
104 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
105 (BIT(N + QM_MBOX_HOST_HALT_MASK_OFFSET))
106 #define QM_IR_MBOX_ENABLE_SS_INT_HALT_MASK(N) \
107 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
108 ~(BIT(N + QM_MBOX_SS_HALT_MASK_OFFSET))
109 #define QM_IR_MBOX_DISABLE_SS_INT_HALT_MASK(N) \
110 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
111 (BIT(N + QM_MBOX_SS_HALT_MASK_OFFSET))
112
113 /**
114 * Mailbox interrupt mask definitions to return the current mask values
115 */
116 #define QM_IR_MBOX_SS_INT_HALT_MASK \
117 ((QM_MBOX_SS_HALT_MASK_MASK & \
118 QM_INTERRUPT_ROUTER->mailbox_0_int_mask) >> \
119 QM_MBOX_SS_HALT_MASK_OFFSET)
120 #define QM_IR_MBOX_LMT_INT_HALT_MASK \
121 ((QM_MBOX_HOST_HALT_MASK_MASK & \
122 QM_INTERRUPT_ROUTER->mailbox_0_int_mask) >> \
123 QM_MBOX_SS_HALT_MASK_OFFSET)
124 #define QM_IR_MBOX_SS_ALL_INT_MASK \
125 ((QM_MBOX_SS_MASK_MASK & QM_INTERRUPT_ROUTER->mailbox_0_int_mask) >> \
126 QM_MBOX_SS_MASK_OFFSET)
127 #define QM_IR_MBOX_LMT_ALL_INT_MASK \
128 (QM_MBOX_HOST_MASK_MASK & QM_INTERRUPT_ROUTER->mailbox_0_int_mask)
129
130 /**
131 * Mailbox interrupt macros to determine if the specified mailbox interrupt mask
132 * has been locked.
133 */
134 #define QM_IR_MBOX_SS_INT_LOCK_HALT_MASK(N) \
135 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(3))
136 #define QM_IR_MBOX_LMT_INT_LOCK_HALT_MASK(N) \
137 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(2))
138 #define QM_IR_MBOX_SS_INT_LOCK_MASK(N) \
139 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(1))
140 #define QM_IR_MBOX_LMT_INT_LOCK_MASK(N) \
141 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(0))
142
143 /**
144 * Mailbox macros to check if a particular mailbox has been routed to a core.
145 */
146 #define QM_IR_MBOX_IS_LMT_INT_MASK_EN(N) \
147 ~(QM_IR_MBOX_LMT_ALL_INT_MASK & ((1 << (N))))
148 #define QM_IR_MBOX_IS_SS_INT_MASK_EN(N) \
149 ~(QM_IR_MBOX_SS_ALL_INT_MASK & ((1 << (QM_MBOX_SS_MASK_OFFSET + (N)))))
150
151 #define QM_IR_UNMASK_COMPARATOR_LMT_INTERRUPTS(n) \
152 (QM_INTERRUPT_ROUTER->comparator_0_host_int_mask &= ~(BIT(n)))
153 #define QM_IR_MASK_COMPARATOR_LMT_INTERRUPTS(n) \
154 (QM_INTERRUPT_ROUTER->comparator_0_host_int_mask |= BIT(n))
155 #define QM_IR_UNMASK_COMPARATOR_LMT_HALTS(n) \
156 (QM_INTERRUPT_ROUTER->comparator_0_host_halt_int_mask &= ~(BIT(n)))
157 #define QM_IR_MASK_COMPARATOR_LMT_HALTS(n) \
158 (QM_INTERRUPT_ROUTER->comparator_0_host_halt_int_mask |= BIT(n))
159
160 #define QM_IR_UNMASK_COMPARATOR_SS_INTERRUPTS(n) \
161 (QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask &= ~(BIT(n)))
162 #define QM_IR_MASK_COMPARATOR_SS_INTERRUPTS(n) \
163 (QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask |= BIT(n))
164 #define QM_IR_UNMASK_COMPARATOR_SS_HALTS(n) \
165 (QM_INTERRUPT_ROUTER->comparator_0_ss_halt_int_mask &= ~(BIT(n)))
166 #define QM_IR_MASK_COMPARATOR_SS_HALTS(n) \
167 (QM_INTERRUPT_ROUTER->comparator_0_ss_halt_int_mask |= BIT(n))
168
169 /* Define macros for use by the active core. */
170 #if (QM_LAKEMONT)
171 #define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
172 QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_)
173 #define QM_IR_MASK_INTERRUPTS(_peripheral_) \
174 QM_IR_MASK_LMT_INTERRUPTS(_peripheral_)
175 #define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_LMT_HALTS(_peripheral_)
176 #define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_LMT_HALTS(_peripheral_)
177
178 #define QM_IR_INT_LOCK_MASK(_peripheral_) QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
179 #define QM_IR_INT_LOCK_HALT_MASK(_peripheral_) \
180 QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
181
182 #define QM_IR_INT_MASK QM_IR_INT_LMT_MASK
183 #define QM_IR_INT_HALT_MASK QM_IR_INT_LMT_HALT_MASK
184 #define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_LMT_MASK(_peripheral_)
185 #define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_LMT_HALT_MASK(_peripheral_)
186
187 #define QM_IR_UNMASK_COMPARATOR_INTERRUPTS(n) \
188 QM_IR_UNMASK_COMPARATOR_LMT_INTERRUPTS(n)
189 #define QM_IR_MASK_COMPARATOR_INTERRUPTS(n) \
190 QM_IR_MASK_COMPARATOR_LMT_INTERRUPTS(n)
191 #define QM_IR_UNMASK_COMPARATOR_HALTS(n) QM_IR_UNMASK_COMPARATOR_LMT_HALTS(n)
192 #define QM_IR_MASK_COMPARATOR_HALTS(n) QM_IR_MASK_COMPARATOR_LMT_HALTS(n)
193
194 #elif(QM_SENSOR)
195 #define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
196 QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_)
197 #define QM_IR_MASK_INTERRUPTS(_peripheral_) \
198 QM_IR_MASK_SS_INTERRUPTS(_peripheral_)
199 #define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_SS_HALTS(_peripheral_)
200 #define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_SS_HALTS(_peripheral_)
201
202 #define QM_IR_INT_LOCK_MASK(_peripheral_) QM_IR_SS_INT_LOCK_MASK(_peripheral_)
203 #define QM_IR_INT_LOCK_HALT_MASK(_peripheral_) \
204 QM_IR_SS_INT_LOCK_MASK(_peripheral_)
205
206 #define QM_IR_INT_MASK QM_IR_INT_SS_MASK
207 #define QM_IR_INT_HALT_MASK QM_IR_INT_SS_HALT_MASK
208 #define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_SS_MASK(_peripheral_)
209 #define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_SS_HALT_MASK(_peripheral_)
210
211 #define QM_IR_UNMASK_COMPARATOR_INTERRUPTS(n) \
212 QM_IR_UNMASK_COMPARATOR_SS_INTERRUPTS(n)
213 #define QM_IR_MASK_COMPARATOR_INTERRUPTS(n) \
214 QM_IR_MASK_COMPARATOR_SS_INTERRUPTS(n)
215 #define QM_IR_UNMASK_COMPARATOR_HALTS(n) QM_IR_UNMASK_COMPARATOR_SS_HALTS(n)
216 #define QM_IR_MASK_COMPARATOR_HALTS(n) QM_IR_MASK_COMPARATOR_SS_HALTS(n)
217
218 #else
219 #error "No active core selected."
220 #endif
221
222 /** SS I2C Interrupt register map. */
223 typedef struct {
224 QM_RW uint32_t err_mask;
225 QM_RW uint32_t rx_avail_mask;
226 QM_RW uint32_t tx_req_mask;
227 QM_RW uint32_t stop_det_mask;
228 } int_ss_i2c_reg_t;
229
230 /** SS SPI Interrupt register map. */
231 typedef struct {
232 QM_RW uint32_t err_int_mask;
233 QM_RW uint32_t rx_avail_mask;
234 QM_RW uint32_t tx_req_mask;
235 } int_ss_spi_reg_t;
236
237 /** Interrupt register map. */
238 typedef struct {
239 QM_RW uint32_t ss_adc_0_error_int_mask; /**< Sensor ADC 0 Error. */
240 QM_RW uint32_t ss_adc_0_int_mask; /**< Sensor ADC 0. */
241 QM_RW uint32_t ss_gpio_0_int_mask; /**< Sensor GPIO 0. */
242 QM_RW uint32_t ss_gpio_1_int_mask; /**< Sensor GPIO 1. */
243 int_ss_i2c_reg_t ss_i2c_0_int; /**< Sensor I2C 0 Masks. */
244 int_ss_i2c_reg_t ss_i2c_1_int; /**< Sensor I2C 1 Masks. */
245 int_ss_spi_reg_t ss_spi_0_int; /**< Sensor SPI 0 Masks. */
246 int_ss_spi_reg_t ss_spi_1_int; /**< Sensor SPI 1 Masks. */
247 QM_RW uint32_t i2c_master_0_int_mask; /**< I2C Master 0. */
248 QM_RW uint32_t i2c_master_1_int_mask; /**< I2C Master 1. */
249 QM_R uint32_t reserved;
250 QM_RW uint32_t spi_master_0_int_mask; /**< SPI Master 0. */
251 QM_RW uint32_t spi_master_1_int_mask; /**< SPI Master 1. */
252 QM_RW uint32_t spi_slave_0_int_mask; /**< SPI Slave 0. */
253 QM_RW uint32_t uart_0_int_mask; /**< UART 0. */
254 QM_RW uint32_t uart_1_int_mask; /**< UART 1. */
255 QM_RW uint32_t i2s_0_int_mask; /**< I2S 0. */
256 QM_RW uint32_t gpio_0_int_mask; /**< GPIO 0. */
257 QM_RW uint32_t pwm_0_int_mask; /**< PWM 0. */
258 QM_RW uint32_t usb_0_int_mask; /**< USB 0. */
259 QM_RW uint32_t rtc_0_int_mask; /**< RTC 0. */
260 QM_RW uint32_t wdt_0_int_mask; /**< WDT 0. */
261 QM_RW uint32_t dma_0_int_0_mask; /**< DMA 0 Ch 0. */
262 QM_RW uint32_t dma_0_int_1_mask; /**< DMA 0 Ch 1. */
263 QM_RW uint32_t dma_0_int_2_mask; /**< DMA 0 Ch 2. */
264 QM_RW uint32_t dma_0_int_3_mask; /**< DMA 0 Ch 3. */
265 QM_RW uint32_t dma_0_int_4_mask; /**< DMA 0 Ch 4. */
266 QM_RW uint32_t dma_0_int_5_mask; /**< DMA 0 Ch 5. */
267 QM_RW uint32_t dma_0_int_6_mask; /**< DMA 0 Ch 6. */
268 QM_RW uint32_t dma_0_int_7_mask; /**< DMA 0 Ch 7. */
269 /** Mailbox 0 Combined 8 Channel Host and Sensor Masks. */
270 QM_RW uint32_t mailbox_0_int_mask;
271 /** Comparator Sensor Halt Mask. */
272 QM_RW uint32_t comparator_0_ss_halt_int_mask;
273 /** Comparator Host Halt Mask. */
274 QM_RW uint32_t comparator_0_host_halt_int_mask;
275 /** Comparator Sensor Mask. */
276 QM_RW uint32_t comparator_0_ss_int_mask;
277 /** Comparator Host Mask. */
278 QM_RW uint32_t comparator_0_host_int_mask;
279 QM_RW uint32_t host_bus_error_int_mask; /**< Host bus error. */
280 QM_RW uint32_t dma_0_error_int_mask; /**< DMA 0 Error. */
281 QM_RW uint32_t sram_mpr_0_int_mask; /**< SRAM MPR 0. */
282 QM_RW uint32_t flash_mpr_0_int_mask; /**< Flash MPR 0. */
283 QM_RW uint32_t flash_mpr_1_int_mask; /**< Flash MPR 1. */
284 QM_RW uint32_t aonpt_0_int_mask; /**< AONPT 0. */
285 QM_RW uint32_t adc_0_pwr_int_mask; /**< ADC 0 PWR. */
286 QM_RW uint32_t adc_0_cal_int_mask; /**< ADC 0 CAL. */
287 QM_RW uint32_t aon_gpio_0_int_mask; /**< AON GPIO 0. */
288 QM_RW uint32_t lock_int_mask_reg; /**< Interrupt Mask Lock Register. */
289 } qm_interrupt_router_reg_t;
290
291 /* Number of SCSS interrupt mask registers (excluding mask lock register). */
292 #define QM_INTERRUPT_ROUTER_MASK_NUMREG \
293 ((sizeof(qm_interrupt_router_reg_t) / sizeof(uint32_t)) - 1)
294
295 /* Default POR SCSS interrupt mask (all interrupts masked). */
296 #define QM_INTERRUPT_ROUTER_MASK_DEFAULT (0xFFFFFFFF)
297
298 #if (UNIT_TEST)
299 qm_interrupt_router_reg_t test_interrupt_router;
300 #define QM_INTERRUPT_ROUTER \
301 ((qm_interrupt_router_reg_t *)(&test_interrupt_router))
302
303 #else
304 /* System control subsystem interrupt masking register block. */
305 #define QM_INTERRUPT_ROUTER_BASE (0xB0800400)
306 #define QM_INTERRUPT_ROUTER \
307 ((qm_interrupt_router_reg_t *)QM_INTERRUPT_ROUTER_BASE)
308 #endif
309
310 #define QM_IR_DMA_ERROR_HOST_MASK (0x000000FF)
311 #define QM_IR_DMA_ERROR_SS_MASK (0x0000FF00)
312
313 #if (QM_LAKEMONT)
314 #define QM_IR_DMA_ERROR_MASK QM_IR_DMA_ERROR_HOST_MASK
315 #elif(QM_SENSOR)
316 #define QM_IR_DMA_ERROR_MASK QM_IR_DMA_ERROR_SS_MASK
317 #endif
318
319 /** @} */
320
321 #endif /* __QM_INTERRUPT_ROUTER_REGS_H__ */
qm_interrupt_router_reg_t::i2c_master_1_int_mask
QM_RW uint32_t i2c_master_1_int_mask
I2C Master 1.
Definition: qm_interrupt_router_regs.h:248
qm_interrupt_router_reg_t::aon_gpio_0_int_mask
QM_RW uint32_t aon_gpio_0_int_mask
AON GPIO 0.
Definition: qm_interrupt_router_regs.h:287
qm_interrupt_router_reg_t::i2s_0_int_mask
QM_RW uint32_t i2s_0_int_mask
I2S 0.
Definition: qm_interrupt_router_regs.h:255
qm_interrupt_router_reg_t::ss_gpio_1_int_mask
QM_RW uint32_t ss_gpio_1_int_mask
Sensor GPIO 1.
Definition: qm_interrupt_router_regs.h:242
int_ss_i2c_reg_t
SS I2C Interrupt register map.
Definition: qm_interrupt_router_regs.h:223
qm_interrupt_router_reg_t::dma_0_int_5_mask
QM_RW uint32_t dma_0_int_5_mask
DMA 0 Ch 5.
Definition: qm_interrupt_router_regs.h:266
qm_interrupt_router_reg_t::dma_0_int_3_mask
QM_RW uint32_t dma_0_int_3_mask
DMA 0 Ch 3.
Definition: qm_interrupt_router_regs.h:264
qm_interrupt_router_reg_t::dma_0_int_2_mask
QM_RW uint32_t dma_0_int_2_mask
DMA 0 Ch 2.
Definition: qm_interrupt_router_regs.h:263
qm_interrupt_router_reg_t::ss_adc_0_error_int_mask
QM_RW uint32_t ss_adc_0_error_int_mask
Sensor ADC 0 Error.
Definition: qm_interrupt_router_regs.h:239
qm_interrupt_router_reg_t
Interrupt register map.
Definition: qm_interrupt_router_regs.h:77
qm_interrupt_router_reg_t::dma_0_int_7_mask
QM_RW uint32_t dma_0_int_7_mask
DMA 0 Ch 7.
Definition: qm_interrupt_router_regs.h:268
qm_interrupt_router_reg_t::flash_mpr_1_int_mask
QM_RW uint32_t flash_mpr_1_int_mask
Flash MPR 1.
Definition: qm_interrupt_router_regs.h:283
int_ss_spi_reg_t
SS SPI Interrupt register map.
Definition: qm_interrupt_router_regs.h:231
qm_interrupt_router_reg_t::ss_i2c_1_int
int_ss_i2c_reg_t ss_i2c_1_int
Sensor I2C 1 Masks.
Definition: qm_interrupt_router_regs.h:244
qm_interrupt_router_reg_t::ss_adc_0_int_mask
QM_RW uint32_t ss_adc_0_int_mask
Sensor ADC 0.
Definition: qm_interrupt_router_regs.h:240
qm_interrupt_router_reg_t::ss_gpio_0_int_mask
QM_RW uint32_t ss_gpio_0_int_mask
Sensor GPIO 0.
Definition: qm_interrupt_router_regs.h:241
qm_interrupt_router_reg_t::ss_spi_0_int
int_ss_spi_reg_t ss_spi_0_int
Sensor SPI 0 Masks.
Definition: qm_interrupt_router_regs.h:245
qm_interrupt_router_reg_t::usb_0_int_mask
QM_RW uint32_t usb_0_int_mask
USB 0.
Definition: qm_interrupt_router_regs.h:258
qm_interrupt_router_reg_t::dma_0_int_6_mask
QM_RW uint32_t dma_0_int_6_mask
DMA 0 Ch 6.
Definition: qm_interrupt_router_regs.h:267
qm_interrupt_router_reg_t::pwm_0_int_mask
QM_RW uint32_t pwm_0_int_mask
PWM 0.
Definition: qm_interrupt_router_regs.h:257
qm_interrupt_router_reg_t::spi_master_1_int_mask
QM_RW uint32_t spi_master_1_int_mask
SPI Master 1.
Definition: qm_interrupt_router_regs.h:251
qm_interrupt_router_reg_t::comparator_0_ss_halt_int_mask
QM_RW uint32_t comparator_0_ss_halt_int_mask
Comparator Sensor Halt Mask.
Definition: qm_interrupt_router_regs.h:272
qm_interrupt_router_reg_t::ss_i2c_0_int
int_ss_i2c_reg_t ss_i2c_0_int
Sensor I2C 0 Masks.
Definition: qm_interrupt_router_regs.h:243
qm_interrupt_router_reg_t::ss_spi_1_int
int_ss_spi_reg_t ss_spi_1_int
Sensor SPI 1 Masks.
Definition: qm_interrupt_router_regs.h:246
qm_interrupt_router_reg_t::dma_0_int_4_mask
QM_RW uint32_t dma_0_int_4_mask
DMA 0 Ch 4.
Definition: qm_interrupt_router_regs.h:265
qm_interrupt_router_reg_t::mailbox_0_int_mask
QM_RW uint32_t mailbox_0_int_mask
Mailbox 0 Combined 8 Channel Host and Sensor Masks.
Definition: qm_interrupt_router_regs.h:270
qm_interrupt_router_reg_t::comparator_0_ss_int_mask
QM_RW uint32_t comparator_0_ss_int_mask
Comparator Sensor Mask.
Definition: qm_interrupt_router_regs.h:276