Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

- Main Page
- Modules
- Data Structures
- Files

- File List

ss_power_states.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __QM_SS_POWER_STATES_H__
6 #define __QM_SS_POWER_STATES_H__
7
8 #include "qm_common.h"
9 #include "qm_sensor_regs.h"
10
11 /**
12 * SS Power mode control for Quark SE Microcontrollers.
13 *
14 * @defgroup groupSSPower SS Power states
15 * @{
16 */
17
18 /**
19 * Sensor Subsystem SS1 Timers mode type.
20 */
21 typedef enum {
22 QM_SS_POWER_CPU_SS1_TIMER_OFF = 0, /**< Disable SS Timers in SS1. */
23 QM_SS_POWER_CPU_SS1_TIMER_ON /**< Keep SS Timers enabled in SS1. */
24 } qm_ss_power_cpu_ss1_mode_t;
25
26 /**
27 * Enable LPSS state entry.
28 *
29 * Put the SoC into LPSS on next C2/C2LP and SS2 state combination.<BR>
30 * This function needs to be called on the Sensor Core to
31 * Clock Gate ADC, I2C0, I2C1, SPI0 and SPI1 sensor peripherals.<BR>
32 * Clock Gating sensor peripherals is a requirement to enter LPSS state.<BR>
33 * After LPSS, qm_ss_power_soc_lpss_disable needs to be called to
34 * restore clock gating.<BR>
35 *
36 * This needs to be called before any transition to C2/C2LP and SS2
37 * in order to enter LPSS.<BR>
38 * SoC Hybrid Clock is gated in this state.<BR>
39 * Core Well Clocks are gated.<BR>
40 * RTC is the only clock running.
41 *
42 * Possible SoC wake events are:
43 * - Low Power Comparator Interrupt
44 * - AON GPIO Interrupt
45 * - AON Timer Interrupt
46 * - RTC Interrupt
47 */
48 void qm_ss_power_soc_lpss_enable(void);
49
50 #if (ENABLE_RESTORE_CONTEXT)
51 /**
52 * Enter SoC sleep state and restore after wake up.
53 *
54 * Put the ARC core into sleep state until next SoC wake event
55 * and continue execution after wake up where the application stopped.
56 *
57 * If the library is built with ENABLE_RESTORE_CONTEXT=1, then this function
58 * will use the arc_restore_addr to save restore trap address which brings back
59 * the ARC CPU to the point where this function was called.
60 * This means that applications should refrain from using them.
61 *
62 * This function calls qm_ss_save_context and qm_ss_restore_context
63 * in order to restore execution where it stopped.
64 * All power management transitions are done by qm_power_soc_sleep().
65 */
66 void qm_ss_power_soc_sleep_restore(void);
67 /**
68 * Enter SoC sleep state and restore after wake up.
69 *
70 * Put the ARC core into sleep state until next SoC wake event
71 * and continue execution after wake up where the application stopped.
72 *
73 * If the library is built with ENABLE_RESTORE_CONTEXT=1, then this function
74 * will use the arc_restore_addr to save restore trap address which brings back
75 * the ARC CPU to the point where this function was called.
76 * This means that applications should refrain from using them.
77 *
78 * This function calls qm_ss_save_context and qm_ss_restore_context
79 * in order to restore execution where it stopped.
80 * All power management transitions are done by power_qm_soc_deep_sleep().
81 */
82 void qm_ss_power_soc_deep_sleep_restore(void);
83
84 /**
85 * Save context, enter ARC SS1 power save state and restore after wake up.
86 *
87 * This routine is same as qm_ss_power_soc_sleep_restore(), just instead of
88 * going to sleep it will go to SS1 power save state.
89 * Note: this function has a while(1) which will spin until we enter
90 * (and exit) sleep and the power state change will be managed by the other
91 * core.
92 */
93 void qm_ss_power_sleep_wait(void);
94
95 /**
96 * Enable the SENSOR startup restore flag.
97 */
98 void qm_power_soc_set_ss_restore_flag(void);
99
100 #endif /* ENABLE_RESTORE_CONTEXT */
101
102 /**
103 * Disable LPSS state entry.
104 *
105 * Clear LPSS enable flag.<BR>
106 * Disable Clock Gating of ADC, I2C0, I2C1, SPI0 and SPI1 sensor
107 * peripherals.<BR>
108 * This will prevent entry in LPSS when cores are in C2/C2LP and SS2 states.
109 */
110 void qm_ss_power_soc_lpss_disable(void);
111
112 /**
113 * Enter Sensor SS1 state.
114 *
115 * Put the Sensor Subsystem into SS1.<BR>
116 * Processor Clock is gated in this state.
117 *
118 * A wake event causes the Sensor Subsystem to transition to SS0.<BR>
119 * A wake event is a sensor subsystem interrupt.
120 *
121 * According to the mode selected, Sensor Subsystem Timers can be disabled.
122 *
123 * @param[in] mode Mode selection for SS1 state.
124 */
125 void qm_ss_power_cpu_ss1(const qm_ss_power_cpu_ss1_mode_t mode);
126
127 /**
128 * Enter Sensor SS2 state or SoC LPSS state.
129 *
130 * Put the Sensor Subsystem into SS2.<BR>
131 * Sensor Complex Clock is gated in this state.<BR>
132 * Sensor Peripherals are gated in this state.<BR>
133 *
134 * This enables entry in LPSS if:
135 * - Sensor Subsystem is in SS2
136 * - Lakemont is in C2 or C2LP
137 * - LPSS entry is enabled
138 *
139 * A wake event causes the Sensor Subsystem to transition to SS0.<BR>
140 * There are two kinds of wake event depending on the Sensor Subsystem
141 * and SoC state:
142 * - SS2: a wake event is a Sensor Subsystem interrupt
143 * - LPSS: a wake event is a Sensor Subsystem interrupt or a Lakemont interrupt
144 *
145 * LPSS wake events apply if LPSS is entered.
146 * If Host wakes the SoC from LPSS,
147 * Sensor also transitions back to SS0.
148 */
149 void qm_ss_power_cpu_ss2(void);
150
151 #if (ENABLE_RESTORE_CONTEXT) && (!UNIT_TEST)
152 /**
153 * Save resume vector.
154 *
155 * Saves the resume vector in the global "arc_restore_addr" location.
156 * The ARC will jump to the resume vector once a wake up event is
157 * triggered and x86 resumes the ARC.
158 */
159 #define qm_ss_set_resume_vector(_restore_label, arc_restore_addr) \
160 __asm__ __volatile__("mov r0, @arc_restore_addr\n\t" \
161 "st " #_restore_label ", [r0]\n\t" \
162 : /* Output operands. */ \
163 : /* Input operands. */ \
164 : /* Clobbered registers list. */ \
165 "r0")
166
167 /* Save execution context.
168 *
169 * This routine saves CPU registers onto cpu_context,
170 * array.
171 *
172 */
173 #define qm_ss_save_context(cpu_context) \
174 __asm__ __volatile__("push_s r0\n\t" \
175 "mov r0, @cpu_context\n\t" \
176 "st r1, [r0, 4]\n\t" \
177 "st r2, [r0, 8]\n\t" \
178 "st r3, [r0, 12]\n\t" \
179 "st r4, [r0, 16]\n\t" \
180 "st r5, [r0, 20]\n\t" \
181 "st r6, [r0, 24]\n\t" \
182 "st r7, [r0, 28]\n\t" \
183 "st r8, [r0, 32]\n\t" \
184 "st r9, [r0, 36]\n\t" \
185 "st r10, [r0, 40]\n\t" \
186 "st r11, [r0, 44]\n\t" \
187 "st r12, [r0, 48]\n\t" \
188 "st r13, [r0, 52]\n\t" \
189 "st r14, [r0, 56]\n\t" \
190 "st r15, [r0, 60]\n\t" \
191 "st r16, [r0, 64]\n\t" \
192 "st r17, [r0, 68]\n\t" \
193 "st r18, [r0, 72]\n\t" \
194 "st r19, [r0, 76]\n\t" \
195 "st r20, [r0, 80]\n\t" \
196 "st r21, [r0, 84]\n\t" \
197 "st r22, [r0, 88]\n\t" \
198 "st r23, [r0, 92]\n\t" \
199 "st r24, [r0, 96]\n\t" \
200 "st r25, [r0, 100]\n\t" \
201 "st r26, [r0, 104]\n\t" \
202 "st r27, [r0, 108]\n\t" \
203 "st r28, [r0, 112]\n\t" \
204 "st r29, [r0, 116]\n\t" \
205 "st r30, [r0, 120]\n\t" \
206 "st r31, [r0, 124]\n\t" \
207 "lr r31, [ic_ctrl]\n\t" \
208 "st r31, [r0, 128]\n\t" \
209 : /* Output operands. */ \
210 : /* Input operands. */ \
211 [ic_ctrl] "i"(QM_SS_AUX_IC_CTRL) \
212 : /* Clobbered registers list. */ \
213 "r0")
214
215 /* Restore execution context.
216 *
217 * This routine restores CPU registers from cpu_context,
218 * array.
219 *
220 * This routine is called from the bootloader to restore the execution context
221 * from before entering in sleep mode.
222 */
223 #define qm_ss_restore_context(_restore_label, cpu_context) \
224 __asm__ __volatile__( \
225 #_restore_label \
226 ":\n\t" \
227 "mov r0, @cpu_context\n\t" \
228 "ld r1, [r0, 4]\n\t" \
229 "ld r2, [r0, 8]\n\t" \
230 "ld r3, [r0, 12]\n\t" \
231 "ld r4, [r0, 16]\n\t" \
232 "ld r5, [r0, 20]\n\t" \
233 "ld r6, [r0, 24]\n\t" \
234 "ld r7, [r0, 28]\n\t" \
235 "ld r8, [r0, 32]\n\t" \
236 "ld r9, [r0, 36]\n\t" \
237 "ld r10, [r0, 40]\n\t" \
238 "ld r11, [r0, 44]\n\t" \
239 "ld r12, [r0, 48]\n\t" \
240 "ld r13, [r0, 52]\n\t" \
241 "ld r14, [r0, 56]\n\t" \
242 "ld r15, [r0, 60]\n\t" \
243 "ld r16, [r0, 64]\n\t" \
244 "ld r17, [r0, 68]\n\t" \
245 "ld r18, [r0, 72]\n\t" \
246 "ld r19, [r0, 76]\n\t" \
247 "ld r20, [r0, 80]\n\t" \
248 "ld r21, [r0, 84]\n\t" \
249 "ld r22, [r0, 88]\n\t" \
250 "ld r23, [r0, 92]\n\t" \
251 "ld r24, [r0, 96]\n\t" \
252 "ld r25, [r0, 100]\n\t" \
253 "ld r26, [r0, 104]\n\t" \
254 "ld r27, [r0, 108]\n\t" \
255 "ld r28, [r0, 112]\n\t" \
256 "ld r29, [r0, 116]\n\t" \
257 "ld r30, [r0, 120]\n\t" \
258 "ld r31, [r0, 124]\n\t" \
259 "ld r0, [r0, 128]\n\t" \
260 "sr r0, [ic_ctrl]\n\t" \
261 "pop_s r0\n\t" \
262 "sr 0,[0x101]\n\t" /* Setup Sensor Subsystem TimeStamp Counter */ \
263 "sr 0,[0x100]\n\t" \
264 "sr -1,[0x102]\n\t" \
265 : /* Output operands. */ \
266 : /* Input operands. */ \
267 [ic_ctrl] "i"(QM_SS_AUX_IC_CTRL) \
268 : /* Clobbered registers list. */ \
269 "r0")
270 #else
271 #define qm_ss_set_resume_vector(_restore_label, arc_restore_addr)
272 #define qm_ss_save_context(cpu_context)
273 #define qm_ss_restore_context(_restore_label, cpu_context)
274 #endif
275
276 /**
277 * @}
278 */
279
280 #endif /* __QM_SS_POWER_STATES_H__ */
qm_ss_power_cpu_ss1
void qm_ss_power_cpu_ss1(const qm_ss_power_cpu_ss1_mode_t mode)
Enter Sensor SS1 state.
Definition: ss_power_states.c:91
qm_ss_power_cpu_ss2
void qm_ss_power_cpu_ss2(void)
Enter Sensor SS2 state or SoC LPSS state.
Definition: ss_power_states.c:122
qm_ss_power_sleep_wait
void qm_ss_power_sleep_wait(void)
Save context, enter ARC SS1 power save state and restore after wake up.
Definition: ss_power_states.c:196
qm_power_soc_set_ss_restore_flag
void qm_power_soc_set_ss_restore_flag(void)
Enable the SENSOR startup restore flag.
Definition: ss_power_states.c:226
QM_SS_POWER_CPU_SS1_TIMER_OFF
Disable SS Timers in SS1.
Definition: ss_power_states.h:22
qm_ss_power_soc_sleep_restore
void qm_ss_power_soc_sleep_restore(void)
Enter SoC sleep state and restore after wake up.
Definition: ss_power_states.c:141
qm_ss_power_soc_lpss_disable
void qm_ss_power_soc_lpss_disable(void)
Disable LPSS state entry.
Definition: ss_power_states.c:64
qm_ss_power_cpu_ss1_mode_t
qm_ss_power_cpu_ss1_mode_t
Sensor Subsystem SS1 Timers mode type.
Definition: ss_power_states.h:21
QM_SS_POWER_CPU_SS1_TIMER_ON
Keep SS Timers enabled in SS1.
Definition: ss_power_states.h:23
qm_ss_power_soc_lpss_enable
void qm_ss_power_soc_lpss_enable(void)
Enable LPSS state entry.
Definition: ss_power_states.c:41
qm_ss_power_soc_deep_sleep_restore
void qm_ss_power_soc_deep_sleep_restore(void)
Enter SoC sleep state and restore after wake up.
Definition: ss_power_states.c:168