Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_i2c.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __QM_I2C_H__
6 #define __QM_I2C_H__
7
8 #include "qm_common.h"
9 #include "qm_dma.h"
10 #include "qm_soc_regs.h"
11
12 /**
13 * I2C.
14 *
15 * @defgroup groupI2C I2C
16 * @{
17 */
18
19 /* High/low period for 50% duty cycle bus clock (in nanoseconds). */
20 #define QM_I2C_SS_50_DC_NS (5000)
21 #define QM_I2C_FS_50_DC_NS (1250)
22 #define QM_I2C_FSP_50_DC_NS (500)
23
24 /* Minimum low period to meet timing requirements (in nanoseconds). */
25 #define QM_I2C_MIN_SS_NS (4700)
26 #define QM_I2C_MIN_FS_NS (1300)
27 #define QM_I2C_MIN_FSP_NS (500)
28
29 /* Data command register masks and values. */
30 #define DATA_COMMAND_READ_COMMAND_BYTE (QM_I2C_IC_DATA_CMD_READ >> 8)
31 #define DATA_COMMAND_STOP_BIT_BYTE (QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL >> 8)
32
33 /**
34 * QM I2C addressing type.
35 */
36 typedef enum {
37 QM_I2C_7_BIT = 0, /**< 7-bit mode. */
38 QM_I2C_10_BIT /**< 10-bit mode. */
39 } qm_i2c_addr_t;
40
41 /**
42 * QM I2C master / slave mode type.
43 */
44 typedef enum {
45 QM_I2C_MASTER = 0, /**< Master mode. */
46 QM_I2C_SLAVE /**< Slave mode. */
47 } qm_i2c_mode_t;
48
49 /**
50 * QM I2C speed type.
51 */
52 typedef enum {
53 QM_I2C_SPEED_STD = 1, /**< Standard mode (100 Kbps). */
54 QM_I2C_SPEED_FAST = 2, /**< Fast mode (400 Kbps). */
55 QM_I2C_SPEED_FAST_PLUS = 3 /**< Fast plus mode (1 Mbps). */
56 } qm_i2c_speed_t;
57
58 /**
59 * I2C status type.
60 */
61 typedef enum {
62 QM_I2C_IDLE = 0, /**< Controller idle. */
63 QM_I2C_TX_ABRT_7B_ADDR_NOACK = BIT(0), /**< 7-bit address noack. */
64 QM_I2C_TX_ABRT_10ADDR1_NOACK = BIT(1), /**< 10-bit address noack. */
65
66 /** 10-bit second address byte address noack. */
67 QM_I2C_TX_ABRT_10ADDR2_NOACK = BIT(2),
68 QM_I2C_TX_ABRT_TXDATA_NOACK = BIT(3), /**< Tx data noack. */
69 QM_I2C_TX_ABRT_GCALL_NOACK = BIT(4), /**< General call noack. */
70 QM_I2C_TX_ABRT_GCALL_READ = BIT(5), /**< Read after general call. */
71 QM_I2C_TX_ABRT_HS_ACKDET = BIT(6), /**< High Speed master ID ACK. */
72 QM_I2C_TX_ABRT_SBYTE_ACKDET = BIT(7), /**< Start ACK. */
73
74 /** High Speed with restart disabled. */
75 QM_I2C_TX_ABRT_HS_NORSTRT = BIT(8),
76
77 /** 10-bit address read and restart disabled. */
78 QM_I2C_TX_ABRT_10B_RD_NORSTRT = BIT(10),
79 QM_I2C_TX_ABRT_MASTER_DIS = BIT(11), /**< Master disabled. */
80 QM_I2C_TX_ARB_LOST = BIT(12), /**< Master lost arbitration. */
81 QM_I2C_TX_ABRT_SLVFLUSH_TXFIFO = BIT(13), /**< Slave flush tx FIFO. */
82 QM_I2C_TX_ABRT_SLV_ARBLOST = BIT(14), /**< Slave lost bus. */
83 QM_I2C_TX_ABRT_SLVRD_INTX = BIT(15), /**< Slave read completion. */
84 QM_I2C_TX_ABRT_USER_ABRT = BIT(16), /**< User abort. */
85 QM_I2C_BUSY = BIT(17), /**< Controller busy. */
86 QM_I2C_TX_ABORT = BIT(18), /**< Tx abort. */
87 QM_I2C_TX_OVER = BIT(19), /**< Tx overflow. */
88 QM_I2C_RX_OVER = BIT(20), /**< Rx overflow. */
89 QM_I2C_RX_UNDER = BIT(21), /**< Rx underflow. */
90 QM_I2C_START_DETECTED = BIT(22), /**< Start or restart detected. */
91 QM_I2C_TX_EMPTY = BIT(23), /**< TX buffer empty. */
92 QM_I2C_RX_FULL = BIT(24), /**< RX buffer full. */
93 QM_I2C_STOP_DETECTED = BIT(25), /** Stop detected. */
94 QM_I2C_GEN_CALL_DETECTED = BIT(26) /**< General call detected. */
95 } qm_i2c_status_t;
96
97 /**
98 * QM I2C slave stop detect behaviour
99 */
100 typedef enum {
101 /** Interrupt regardless of whether this slave is addressed or not. */
102 QM_I2C_SLAVE_INTERRUPT_ALWAYS = 0x0,
103
104 /** Trigger interrupt only if this slave is being addressed. */
105 QM_I2C_SLAVE_INTERRUPT_WHEN_ADDRESSED = 0x1
106 } qm_i2c_slave_stop_t;
107
108 /**
109 * I2C configuration type.
110 */
111 typedef struct {
112 qm_i2c_speed_t speed; /**< Standard, fast or fast plus mode. */
113 qm_i2c_addr_t address_mode; /**< 7 bit or 10 bit addressing. */
114 qm_i2c_mode_t mode; /**< Master or slave mode. */
115 uint16_t slave_addr; /**< I2C address when in slave mode. */
116
117 /** Slave stop detect behaviour */
118 qm_i2c_slave_stop_t stop_detect_behaviour;
119
120 } qm_i2c_config_t;
121
122 /**
123 * I2C transfer type.
124 * Master mode:
125 * - If tx len is 0: perform receive-only transaction.
126 * - If rx len is 0: perform transmit-only transaction.
127 * - Both tx and rx len not 0: perform a transmit-then-receive
128 * combined transaction.
129 */
130 typedef struct {
131 uint8_t *tx; /**< Write data. */
132 uint32_t tx_len; /**< Write data length. */
133 uint8_t *rx; /**< Read data. */
134 uint32_t rx_len; /**< Read buffer length. */
135
136 /**
137 * Master: Generate STOP.
138 * Slave: stop at the end of transaction.
139 */
140 bool stop;
141
142 /**
143 * Transfer callback.
144 *
145 * Called after all data is transmitted/received or if the driver
146 * detects an error during the I2C transfer.
147 *
148 * In slave mode, qm_i2c_slave_irq_transfer_update shall be called from
149 * this callback to update transfer buffers when receiving a
150 * QM_I2C_RX_FULL or QM_I2C_TX_EMPTY status. If the update function is
151 * not called with these statuses, the driver will drop every new data
152 * received or send dummy data (0x00) for each byte until next bus
153 * start.
154 *
155 * @param[in] data User defined data.
156 * @param[in] rc 0 on success.
157 * Negative @ref errno for possible error codes.
158 * @param[in] status I2C status.
159 * @param[in] len Length of the transfer if successful, 0 otherwise.
160 */
161 void (*callback)(void *data, int rc, qm_i2c_status_t status,
162 uint32_t len);
163 void *callback_data; /**< User callback data. */
164 } qm_i2c_transfer_t;
165
166 /**
167 * Set I2C configuration.
168 *
169 * @param[in] i2c Which I2C to set the configuration of.
170 * @param[out] cfg I2C configuration. This must not be NULL.
171 *
172 * @return Standard errno return type for QMSI.
173 * @retval 0 on success.
174 * @retval Negative @ref errno for possible error codes.
175 */
176 int qm_i2c_set_config(const qm_i2c_t i2c, const qm_i2c_config_t *const cfg);
177
178 /**
179 * Set I2C speed.
180 *
181 * Fine tune I2C clock speed. This will set the SCL low count
182 * and the SCL hi count cycles. To achieve any required speed.
183 *
184 * @param[in] i2c I2C index.
185 * @param[in] speed Bus speed (Standard or Fast. Fast includes Fast+ mode).
186 * @param[in] lo_cnt SCL low count.
187 * @param[in] hi_cnt SCL high count.
188 *
189 * @return Standard errno return type for QMSI.
190 * @retval 0 on success.
191 * @retval Negative @ref errno for possible error codes.
192 */
193 int qm_i2c_set_speed(const qm_i2c_t i2c, const qm_i2c_speed_t speed,
194 const uint16_t lo_cnt, const uint16_t hi_cnt);
195
196 /**
197 * Retrieve I2C bus status.
198 *
199 * @param[in] i2c Which I2C to read the status of.
200 * @param[out] status Current I2C status. This must not be NULL.
201 *
202 * The user may call this function before performing an I2C transfer in order to
203 * guarantee that the I2C interface is available.
204 *
205 * @return Standard errno return type for QMSI.
206 * @retval 0 on success.
207 * @retval Negative @ref errno for possible error codes.
208 */
209 int qm_i2c_get_status(const qm_i2c_t i2c, qm_i2c_status_t *const status);
210
211 /**
212 * Master write on I2C.
213 *
214 * Perform a master write on the I2C bus. This is a blocking synchronous call.
215 *
216 * @param[in] i2c Which I2C to write to.
217 * @param[in] slave_addr Address of slave to write to.
218 * @param[in] data Pre-allocated buffer of data to write. This must not be NULL.
219 * @param[in] len Length of data to write.
220 * @param[in] stop Generate a STOP condition at the end of tx.
221 * @param[out] status Get I2C status.
222 *
223 * @return Standard errno return type for QMSI.
224 * @retval 0 on success.
225 * @retval Negative @ref errno for possible error codes.
226 */
227 int qm_i2c_master_write(const qm_i2c_t i2c, const uint16_t slave_addr,
228 const uint8_t *const data, uint32_t len,
229 const bool stop, qm_i2c_status_t *const status);
230
231 /**
232 * Master read of I2C.
233 *
234 * Perform a single byte master read from the I2C. This is a blocking call.
235 *
236 * @param[in] i2c Which I2C to read from.
237 * @param[in] slave_addr Address of slave device to read from.
238 * @param[out] data Pre-allocated buffer to populate with data. This must not be
239 * NULL.
240 * @param[in] len Length of data to read from slave.
241 * @param[in] stop Generate a STOP condition at the end of rx.
242 * @param[out] status Get I2C status.
243 *
244 * @return Standard errno return type for QMSI.
245 * @retval 0 on success.
246 * @retval Negative @ref errno for possible error codes.
247 */
248 int qm_i2c_master_read(const qm_i2c_t i2c, const uint16_t slave_addr,
249 uint8_t *const data, uint32_t len, const bool stop,
250 qm_i2c_status_t *const status);
251
252 /**
253 * Interrupt based master transfer on I2C.
254 *
255 * Perform an interrupt based master transfer on the I2C bus. The function will
256 * replenish/empty TX/RX FIFOs on I2C empty/full interrupts.
257 *
258 * @param[in] i2c Which I2C to transfer from.
259 * @param[in] xfer Transfer structure includes write / read buffers, length,
260 * user callback function and the callback context.
261 * The structure must not be NULL and must be kept valid until
262 * the transfer is complete.
263 * @param[in] slave_addr Address of slave to transfer data with.
264 *
265 * @return Standard errno return type for QMSI.
266 * @retval 0 on success.
267 * @retval Negative @ref errno for possible error codes.
268 */
269 int qm_i2c_master_irq_transfer(const qm_i2c_t i2c,
270 const qm_i2c_transfer_t *const xfer,
271 const uint16_t slave_addr);
272
273 /**
274 * Interrupt based slave transfer on I2C.
275 *
276 * Perform an interrupt based slave transfer on the I2C bus. The function will
277 * replenish/empty TX/RX FIFOs on I2C empty/full interrupts.
278 *
279 * @param[in] i2c Which I2C to transfer from.
280 * @param[in] xfer Transfer structure includes write / read buffers, length,
281 * user callback function and the callback context. This must
282 * not be NULL.
283 *
284 * @return Standard errno return type for QMSI.
285 * @retval 0 on success.
286 * @retval Negative @ref errno for possible error codes.
287 */
288 int qm_i2c_slave_irq_transfer(const qm_i2c_t i2c,
289 volatile const qm_i2c_transfer_t *const xfer);
290
291 /**
292 * I2C interrupt based slave transfer buffer update.
293 *
294 * Update transfer buffers location and size. The function will
295 * replenish/empty TX/RX FIFOs on I2C empty/full interrupts.
296 * This function must be called from callback function to update transfer
297 * buffers when requested by ISR.
298 *
299 * It is strongly recommended to use this function for slave-based applications
300 * only, as slave controllers usually do not know how many frames an external
301 * master will send or request before starting the communication.
302 * Master controllers should not use this function as it will most likely
303 * corrupt the transaction.
304 *
305 * @param[in] i2c Which I2C to transfer from.
306 * @param[in] xfer Transfer structure includes write / read buffers, length,
307 * user callback function and the callback context. This must
308 * not be NULL.
309 *
310 * @return Standard errno return type for QMSI.
311 * @retval 0 on success.
312 * @retval Negative @ref errno for possible error codes.
313 */
314 int qm_i2c_slave_irq_transfer_update(
315 const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer);
316
317 /**
318 * Terminate I2C IRQ transfer.
319 *
320 * Terminate the current IRQ or DMA transfer on the I2C bus.
321 * This will cause the user callback to be called with status
322 * QM_I2C_TX_ABRT_USER_ABRT.
323 *
324 * @param[in] i2c I2C controller identifier.
325 *
326 * @return Standard errno return type for QMSI.
327 * @retval 0 on success.
328 * @retval Negative @ref errno for possible error codes.
329 */
330 int qm_i2c_irq_transfer_terminate(const qm_i2c_t i2c);
331
332 /**
333 * Configure a DMA channel with a specific transfer direction.
334 *
335 * Configure a DMA channel with a specific transfer direction. The user is
336 * responsible for managing the allocation of the pool of DMA channels provided
337 * by each DMA core to the different peripheral drivers that require them. Note
338 * that a I2C controller cannot use different DMA cores to manage transfers in
339 * different directions.
340 *
341 * This function configures DMA channel parameters that are unlikely to change
342 * between transfers, like transaction width, burst size, and handshake
343 * interface parameters. The user will likely only call this function once for
344 * the lifetime of an application unless the channel needs to be repurposed.
345 *
346 * Note that qm_dma_init() must first be called before configuring a channel.
347 *
348 * @param[in] i2c I2C controller identifier.
349 * @param[in] dma_controller_id DMA controller identifier.
350 * @param[in] channel_id DMA channel identifier.
351 * @param[in] direction DMA channel direction, either
352 * QM_DMA_MEMORY_TO_PERIPHERAL (TX transfer) or QM_DMA_PERIPHERAL_TO_MEMORY
353 * (RX transfer).
354 *
355 * @return Standard errno return type for QMSI.
356 * @retval 0 on success.
357 * @retval Negative @ref errno for possible error codes.
358 */
359 int qm_i2c_dma_channel_config(const qm_i2c_t i2c,
360 const qm_dma_t dma_controller_id,
361 const qm_dma_channel_id_t channel_id,
362 const qm_dma_channel_direction_t direction);
363
364 /**
365 * Perform a DMA based master transfer on the I2C bus.
366 *
367 * Perform a DMA based master transfer on the I2C bus. If the transfer is TX
368 * only, it will enable DMA operation for the controller and start the transfer.
369 *
370 * If it's an RX only transfer, it will require 2 channels, one for writing the
371 * READ commands and another one for reading the bytes from the bus. Both DMA
372 * operations will start in parallel.
373 *
374 * If this is a combined transaction, both TX and RX operations will be set up,
375 * but only TX will be started. On TX finish (callback), the TX channel will be
376 * used for writing the READ commands and the RX operation will start.
377 *
378 * Note that qm_i2c_dma_channel_config() must first be called in order to
379 * configure all DMA channels needed for a transfer.
380 *
381 * @param[in] i2c I2C controller identifier.
382 * @param[in] xfer Structure containing pre-allocated write and read data
383 * buffers and callback functions. This must not be NULL
384 * and must be kept valid until the transfer is complete.
385 * @param[in] slave_addr Address of slave to transfer data with.
386 *
387 * @return Standard errno return type for QMSI.
388 * @retval 0 on success.
389 * @retval Negative @ref errno for possible error codes.
390 */
391 int qm_i2c_master_dma_transfer(const qm_i2c_t i2c,
392 qm_i2c_transfer_t *const xfer,
393 const uint16_t slave_addr);
394
395 /**
396 * Perform a DMA based slave transfer on the I2C bus.
397 *
398 * Note that qm_i2c_dma_channel_config() must first be called in order to
399 * configure all DMA channels needed for a transfer.
400 *
401 * @param[in] i2c I2C controller identifier.
402 * @param[in] xfer Structure containing pre-allocated write and read data
403 * buffers and callback functions. This pointer must be kept
404 * valid until the transfer is complete.
405 *
406 * @return Standard errno return type for QMSI.
407 * @retval 0 on success.
408 * @retval Negative @ref errno for possible error codes.
409 */
410 int qm_i2c_slave_dma_transfer(const qm_i2c_t i2c,
411 const qm_i2c_transfer_t *const xfer);
412
413 /**
414 * Terminate any DMA transfer going on on the controller.
415 *
416 * Calls the DMA driver to stop any ongoing DMA transfer and calls
417 * qm_i2c_irq_transfer_terminate.
418 *
419 * @param[in] i2c Which I2C to terminate transfers from.
420 *
421 * @return Standard errno return type for QMSI.
422 * @retval 0 on success.
423 * @retval Negative @ref errno for possible error codes.
424 */
425 int qm_i2c_dma_transfer_terminate(const qm_i2c_t i2c);
426
427 /**
428 * Save I2C context.
429 *
430 * Saves the configuration of the specified I2C peripheral
431 * before entering sleep. The slave operations need to be disabled before
432 * being able to save the context as otherwise we could be interrupted by
433 * an I2C transfer while saving registers.
434 *
435 * @param[in] i2c I2C port index.
436 * @param[out] ctx I2C context structure. This must not be NULL.
437 *
438 * @return Standard errno return type for QMSI.
439 * @retval 0 on success.
440 * @retval Negative @ref errno for possible error codes.
441 */
442 int qm_i2c_save_context(const qm_i2c_t i2c, qm_i2c_context_t *const ctx);
443
444 /**
445 * Restore I2C context.
446 *
447 * Restore the configuration of the specified I2C peripheral
448 * after exiting sleep.
449 *
450 * @param[in] i2c I2C port index.
451 * @param[in] ctx I2C context structure. This must not be NULL.
452 *
453 * @return Standard errno return type for QMSI.
454 * @retval 0 on success.
455 * @retval Negative @ref errno for possible error codes.
456 */
457 int qm_i2c_restore_context(const qm_i2c_t i2c,
458 const qm_i2c_context_t *const ctx);
459
460 /**
461 * @}
462 */
463
464 #endif /* __QM_I2C_H__ */
QM_I2C_TX_ABRT_HS_NORSTRT
High Speed with restart disabled.
Definition: qm_i2c.h:75
QM_I2C_SLAVE
Slave mode.
Definition: qm_i2c.h:46
qm_i2c_master_dma_transfer
int qm_i2c_master_dma_transfer(const qm_i2c_t i2c, qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Perform a DMA based master transfer on the I2C bus.
Definition: qm_i2c.c:1542
QM_I2C_BUSY
Controller busy.
Definition: qm_i2c.h:85
qm_i2c_save_context
int qm_i2c_save_context(const qm_i2c_t i2c, qm_i2c_context_t *const ctx)
Save I2C context.
Definition: qm_i2c.c:1668
qm_i2c_transfer_t::tx_len
uint32_t tx_len
Write data length.
Definition: qm_i2c.h:132
qm_i2c_config_t::speed
qm_i2c_speed_t speed
Standard, fast or fast plus mode.
Definition: qm_i2c.h:112
QM_I2C_TX_ABRT_GCALL_NOACK
General call noack.
Definition: qm_i2c.h:69
qm_i2c_master_write
int qm_i2c_master_write(const qm_i2c_t i2c, const uint16_t slave_addr, const uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master write on I2C.
Definition: qm_i2c.c:924
qm_i2c_master_read
int qm_i2c_master_read(const qm_i2c_t i2c, const uint16_t slave_addr, uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master read of I2C.
Definition: qm_i2c.c:999
qm_i2c_set_config
int qm_i2c_set_config(const qm_i2c_t i2c, const qm_i2c_config_t *const cfg)
Set I2C configuration.
Definition: qm_i2c.c:749
QM_I2C_TX_ABRT_SLVFLUSH_TXFIFO
Slave flush tx FIFO.
Definition: qm_i2c.h:81
QM_I2C_TX_ABRT_10ADDR1_NOACK
10-bit address noack.
Definition: qm_i2c.h:64
qm_i2c_set_speed
int qm_i2c_set_speed(const qm_i2c_t i2c, const qm_i2c_speed_t speed, const uint16_t lo_cnt, const uint16_t hi_cnt)
Set I2C speed.
Definition: qm_i2c.c:867
qm_dma_t
qm_dma_t
DMA instances.
Definition: qm_soc_regs.h:1480
QM_I2C_RX_UNDER
Rx underflow.
Definition: qm_i2c.h:89
qm_i2c_transfer_t::callback_data
void * callback_data
User callback data.
Definition: qm_i2c.h:163
qm_i2c_transfer_t::tx
uint8_t * tx
Write data.
Definition: qm_i2c.h:131
QM_I2C_TX_ABRT_7B_ADDR_NOACK
7-bit address noack.
Definition: qm_i2c.h:63
qm_i2c_config_t::stop_detect_behaviour
qm_i2c_slave_stop_t stop_detect_behaviour
Slave stop detect behaviour.
Definition: qm_i2c.h:118
QM_I2C_7_BIT
7-bit mode.
Definition: qm_i2c.h:37
QM_I2C_RX_OVER
Rx overflow.
Definition: qm_i2c.h:88
QM_I2C_TX_ABRT_SLVRD_INTX
Slave read completion.
Definition: qm_i2c.h:83
QM_I2C_SLAVE_INTERRUPT_ALWAYS
Interrupt regardless of whether this slave is addressed or not.
Definition: qm_i2c.h:102
qm_i2c_dma_channel_config
int qm_i2c_dma_channel_config(const qm_i2c_t i2c, const qm_dma_t dma_controller_id, const qm_dma_channel_id_t channel_id, const qm_dma_channel_direction_t direction)
Configure a DMA channel with a specific transfer direction.
Definition: qm_i2c.c:1490
qm_i2c_transfer_t::stop
bool stop
Master: Generate STOP.
Definition: qm_i2c.h:140
QM_I2C_10_BIT
10-bit mode.
Definition: qm_i2c.h:38
qm_i2c_irq_transfer_terminate
int qm_i2c_irq_transfer_terminate(const qm_i2c_t i2c)
Terminate I2C IRQ transfer.
Definition: qm_i2c.c:1217
QM_I2C_SPEED_FAST
Fast mode (400 Kbps).
Definition: qm_i2c.h:54
QM_I2C_TX_ABRT_SBYTE_ACKDET
Start ACK.
Definition: qm_i2c.h:72
qm_i2c_addr_t
qm_i2c_addr_t
QM I2C addressing type.
Definition: qm_i2c.h:36
qm_i2c_config_t::slave_addr
uint16_t slave_addr
I2C address when in slave mode.
Definition: qm_i2c.h:115
qm_i2c_status_t
qm_i2c_status_t
I2C status type.
Definition: qm_i2c.h:61
QM_I2C_TX_ABRT_USER_ABRT
User abort.
Definition: qm_i2c.h:84
qm_i2c_master_irq_transfer
int qm_i2c_master_irq_transfer(const qm_i2c_t i2c, const qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Interrupt based master transfer on I2C.
Definition: qm_i2c.c:1073
QM_I2C_TX_ABRT_TXDATA_NOACK
Tx data noack.
Definition: qm_i2c.h:68
QM_I2C_TX_EMPTY
TX buffer empty.
Definition: qm_i2c.h:91
qm_i2c_speed_t
qm_i2c_speed_t
QM I2C speed type.
Definition: qm_i2c.h:52
qm_i2c_get_status
int qm_i2c_get_status(const qm_i2c_t i2c, qm_i2c_status_t *const status)
Retrieve I2C bus status.
Definition: qm_i2c.c:903
qm_i2c_slave_irq_transfer
int qm_i2c_slave_irq_transfer(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
Interrupt based slave transfer on I2C.
Definition: qm_i2c.c:1123
qm_i2c_mode_t
qm_i2c_mode_t
QM I2C master / slave mode type.
Definition: qm_i2c.h:44
QM_I2C_START_DETECTED
Start or restart detected.
Definition: qm_i2c.h:90
qm_i2c_slave_stop_t
qm_i2c_slave_stop_t
QM I2C slave stop detect behaviour.
Definition: qm_i2c.h:100
QM_I2C_TX_ABRT_10B_RD_NORSTRT
10-bit address read and restart disabled.
Definition: qm_i2c.h:78
qm_i2c_config_t::mode
qm_i2c_mode_t mode
Master or slave mode.
Definition: qm_i2c.h:114
qm_i2c_slave_dma_transfer
int qm_i2c_slave_dma_transfer(const qm_i2c_t i2c, const qm_i2c_transfer_t *const xfer)
Perform a DMA based slave transfer on the I2C bus.
QM_I2C_TX_ABRT_MASTER_DIS
Master disabled.
Definition: qm_i2c.h:79
qm_i2c_slave_irq_transfer_update
int qm_i2c_slave_irq_transfer_update(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
I2C interrupt based slave transfer buffer update.
Definition: qm_i2c.c:1164
qm_dma_channel_direction_t
qm_dma_channel_direction_t
DMA channel direction.
Definition: qm_dma.h:56
qm_i2c_transfer_t::rx
uint8_t * rx
Read data.
Definition: qm_i2c.h:133
QM_I2C_TX_ABRT_SLV_ARBLOST
Slave lost bus.
Definition: qm_i2c.h:82
qm_i2c_transfer_t::rx_len
uint32_t rx_len
Read buffer length.
Definition: qm_i2c.h:134
QM_I2C_SLAVE_INTERRUPT_WHEN_ADDRESSED
Trigger interrupt only if this slave is being addressed.
Definition: qm_i2c.h:105
QM_I2C_TX_ABRT_10ADDR2_NOACK
10-bit second address byte address noack.
Definition: qm_i2c.h:67
QM_I2C_TX_OVER
Tx overflow.
Definition: qm_i2c.h:87
QM_I2C_TX_ARB_LOST
Master lost arbitration.
Definition: qm_i2c.h:80
qm_i2c_t
qm_i2c_t
Number of I2C controllers.
Definition: qm_soc_regs.h:861
QM_I2C_GEN_CALL_DETECTED
Stop detected.
Definition: qm_i2c.h:94
qm_i2c_transfer_t
I2C transfer type.
Definition: qm_i2c.h:130
QM_I2C_IDLE
Controller idle.
Definition: qm_i2c.h:62
QM_I2C_SPEED_FAST_PLUS
Fast plus mode (1 Mbps).
Definition: qm_i2c.h:55
qm_i2c_context_t
I2C context to be saved between sleep/resume.
Definition: qm_soc_regs.h:1260
QM_I2C_SPEED_STD
Standard mode (100 Kbps).
Definition: qm_i2c.h:53
qm_i2c_dma_transfer_terminate
int qm_i2c_dma_transfer_terminate(const qm_i2c_t i2c)
Terminate any DMA transfer going on on the controller.
Definition: qm_i2c.c:1235
QM_I2C_TX_ABRT_GCALL_READ
Read after general call.
Definition: qm_i2c.h:70
QM_I2C_MASTER
Master mode.
Definition: qm_i2c.h:45
qm_i2c_config_t
I2C configuration type.
Definition: qm_i2c.h:111
qm_dma_channel_id_t
qm_dma_channel_id_t
DMA channel IDs.
Definition: qm_soc_regs.h:1486
QM_I2C_TX_ABRT_HS_ACKDET
High Speed master ID ACK.
Definition: qm_i2c.h:71
QM_I2C_TX_ABORT
Tx abort.
Definition: qm_i2c.h:86
qm_i2c_restore_context
int qm_i2c_restore_context(const qm_i2c_t i2c, const qm_i2c_context_t *const ctx)
Restore I2C context.
Definition: qm_i2c.c:1690
QM_I2C_RX_FULL
RX buffer full.
Definition: qm_i2c.h:92
qm_i2c_config_t::address_mode
qm_i2c_addr_t address_mode
7 bit or 10 bit addressing.
Definition: qm_i2c.h:113