Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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Data Structures
SoC Registers (Sensor Subsystem)

Quark SE SoC Sensor Subsystem Registers. More...

## Data Structures
struct | qm_irq_context_t
| SS IRQ context type. More...
struct | qm_ss_gpio_context_t
| SS GPIO context type. More...
struct | qm_ss_i2c_context_t
| SS I2C context type. More...
struct | qm_ss_adc_context_t
| SS ADC context type. More...
struct | qm_ss_spi_context_t
| Sensor Subsystem SPI context type. More...

## SS Timer
enum | qm_ss_timer_reg_t
enum | qm_ss_timer_t
| Sensor Subsystem Timers.

## SS GPIO
GPIO registers and definitions.
enum | qm_ss_gpio_reg_t
| Sensor Subsystem GPIO register block type. More...
enum | qm_ss_gpio_t
| Sensor Subsystem GPIO. More...

## SS I2C
I2C registers and definitions.
enum | qm_ss_i2c_reg_t
| Sensor Subsystem I2C register block type. More...
enum | qm_ss_i2c_t
| Sensor Subsystem I2C.
enum | qm_ss_adc_reg_t { QM_SS_ADC_SET = 0, QM_SS_ADC_DIVSEQSTAT, QM_SS_ADC_SEQ, QM_SS_ADC_CTRL, QM_SS_ADC_INTSTAT, QM_SS_ADC_SAMPLE }
| Sensor Subsystem ADC. More...
enum | qm_ss_adc_t { QM_SS_ADC_0 = 0 }
| Sensor Subsystem ADC. More...

## SS CREG
CREG Registers.
enum | qm_ss_creg_reg_t { QM_SS_IO_CREG_MST0_CTRL = 0x0, QM_SS_IO_CREG_SLV0_OBSR = 0x80, QM_SS_IO_CREG_SLV1_OBSR = 0x180 }

## SS SPI
SPI registers and definitions.
enum | qm_ss_spi_reg_t { QM_SS_SPI_CTRL = 0, QM_SS_SPI_SPIEN = 2, QM_SS_SPI_TIMING = 4, QM_SS_SPI_FTLR, QM_SS_SPI_TXFLR = 7, QM_SS_SPI_RXFLR, QM_SS_SPI_SR, QM_SS_SPI_INTR_STAT, QM_SS_SPI_INTR_MASK, QM_SS_SPI_CLR_INTR, QM_SS_SPI_DR }
| Sensor Subsystem SPI register map. More...
enum | qm_ss_spi_t { QM_SS_SPI_0 = 0, QM_SS_SPI_1 }
| Sensor Subsystem SPI modules. More...

## Detailed Description

Quark SE SoC Sensor Subsystem Registers.

For detailed description please read the SOC datasheet.

## Enumeration Type Documentation

enum qm_ss_adc_reg_t

Sensor Subsystem ADC.

Sensor Subsystem ADC registers

Enumerator
QM_SS_ADC_SET | ADC and sequencer settings register.
QM_SS_ADC_DIVSEQSTAT | ADC clock and sequencer status register.
QM_SS_ADC_SEQ | ADC sequence entry register.
QM_SS_ADC_CTRL | ADC control register.
QM_SS_ADC_INTSTAT | ADC interrupt status register.
QM_SS_ADC_SAMPLE | ADC sample register.

Definition at line 541 of file qm_sensor_regs.h.

enum qm_ss_adc_t

Sensor Subsystem ADC.

Enumerator
QM_SS_ADC_0 | ADC first module.

Definition at line 551 of file qm_sensor_regs.h.

enum qm_ss_creg_reg_t

Enumerator
QM_SS_IO_CREG_MST0_CTRL | Master control register.
QM_SS_IO_CREG_SLV0_OBSR | Slave control register.
QM_SS_IO_CREG_SLV1_OBSR | Slave control register.

Definition at line 628 of file qm_sensor_regs.h.

enum qm_ss_gpio_reg_t

Sensor Subsystem GPIO register block type.

Definition at line 159 of file qm_sensor_regs.h.

enum qm_ss_gpio_t

Sensor Subsystem GPIO.

Definition at line 196 of file qm_sensor_regs.h.

enum qm_ss_i2c_reg_t

Sensor Subsystem I2C register block type.

Definition at line 211 of file qm_sensor_regs.h.

enum qm_ss_spi_reg_t

Sensor Subsystem SPI register map.

Enumerator
QM_SS_SPI_CTRL | SPI control register.
QM_SS_SPI_SPIEN | SPI enable register.
QM_SS_SPI_TIMING | SPI serial clock divider value.
QM_SS_SPI_FTLR | Threshold value for TX/RX FIFO.
QM_SS_SPI_TXFLR | Number of valid data entries in TX FIFO.
QM_SS_SPI_RXFLR | Number of valid data entries in RX FIFO.
QM_SS_SPI_SR | SPI status register.
QM_SS_SPI_INTR_STAT | Interrupt status register.
QM_SS_SPI_INTR_MASK | Interrupt mask register.
QM_SS_SPI_CLR_INTR | Interrupt clear register.
QM_SS_SPI_DR | RW buffer for FIFOs.

Definition at line 676 of file qm_sensor_regs.h.

enum qm_ss_spi_t

Sensor Subsystem SPI modules.

Enumerator
QM_SS_SPI_0 | SPI module 0.
QM_SS_SPI_1 | SPI module 1.

Definition at line 704 of file qm_sensor_regs.h.