Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_interrupt_router.c
1 /*
2 * {% copyright %}
3 */
4
5 #include "qm_common.h"
6 #include "qm_soc_regs.h"
7 #include "qm_interrupt_router.h"
8 #include "qm_interrupt_router_regs.h"
9
10 /* Event router base addr for LMT interrupt routing, for linear IRQ mapping */
11 #define INTERRUPT_ROUTER_LMT_INT_MASK_BASE \
12 (&QM_INTERRUPT_ROUTER->i2c_master_0_int_mask)
13
14 void _qm_ir_unmask_int(uint32_t irq, uint32_t register_offset)
15 {
16 uint32_t *interrupt_router_intmask;
17
18 /* Route peripheral interrupt to Lakemont/Sensor Subsystem */
19 interrupt_router_intmask =
20 (uint32_t *)INTERRUPT_ROUTER_LMT_INT_MASK_BASE + register_offset;
21
22 if (!QM_IR_INT_LOCK_MASK(*interrupt_router_intmask)) {
23 switch (irq) {
24 case QM_IRQ_COMPARATOR_0_INT:
25 /*
26 * Comparator mask uses 1 bit per comparator rather than the
27 * generic host mask.
28 */
29 #if (QM_SENSOR)
30 QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask &=
31 ~0x0007ffff;
32 #else
33 QM_INTERRUPT_ROUTER->comparator_0_host_int_mask &=
34 ~0x0007ffff;
35 #endif
36 break;
37 case QM_IRQ_MAILBOX_0_INT:
38 /* Masking MAILBOX irq is done inside mbox driver */
39 break;
40 case QM_IRQ_DMA_0_ERROR_INT:
41 /*
42 * DMA error mask uses 1 bit per DMA channel rather than the
43 * generic host mask.
44 */
45 #if (QM_SENSOR)
46 *interrupt_router_intmask &= ~QM_IR_DMA_ERROR_SS_MASK;
47 #else
48 *interrupt_router_intmask &= ~QM_IR_DMA_ERROR_HOST_MASK;
49 #endif
50 break;
51 default:
52 QM_IR_UNMASK_INTERRUPTS(*interrupt_router_intmask);
53 break;
54 }
55 }
56 }
57
58 void _qm_ir_mask_int(uint32_t irq, uint32_t register_offset)
59 {
60 uint32_t *interrupt_router_intmask;
61
62 /* Route peripheral interrupt to Lakemont/Sensor Subsystem */
63 interrupt_router_intmask =
64 (uint32_t *)INTERRUPT_ROUTER_LMT_INT_MASK_BASE + register_offset;
65
66 /**/
67 if (!QM_IR_INT_LOCK_MASK(*interrupt_router_intmask)) {
68 switch (irq) {
69 case QM_IRQ_COMPARATOR_0_INT:
70 #if (QM_SENSOR)
71 QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask |=
72 0x0007ffff;
73 #else
74 QM_INTERRUPT_ROUTER->comparator_0_host_int_mask |=
75 0x0007ffff;
76 #endif
77 break;
78 case QM_IRQ_MAILBOX_0_INT:
79 /* Masking MAILBOX irq id done inside mbox driver */
80 break;
81 case QM_IRQ_DMA_0_ERROR_INT:
82 /*
83 * DMA error mask uses 1 bit per DMA channel rather than the
84 * generic host mask.
85 */
86 #if (QM_SENSOR)
87 *interrupt_router_intmask |= QM_IR_DMA_ERROR_SS_MASK;
88 #else
89 *interrupt_router_intmask |= QM_IR_DMA_ERROR_HOST_MASK;
90 #endif
91 break;
92 default:
93 QM_IR_MASK_INTERRUPTS(*interrupt_router_intmask);
94 break;
95 }
96 }
97 }