Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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soc_watch.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __SOC_WATCH_H__
6 #define __SOC_WATCH_H__
7
8 /* This file relies on the SOC being defined, which comes from qm_soc_regs.h */
9 #include "qm_soc_regs.h"
10
11 /**
12 * SoC Watch (Energy Analyzer).
13 *
14 * @defgroup group SOC_WATCH
15 * @{
16 */
17
18 #include "qm_common.h"
19
20 /*
21 * To activate the functionality in this file, compile with
22 * SOC_WATCH_ENABLE=1 on the make command line.
23 *
24 * Accurate timestamping through sleep modes also requires:
25 * + board design: provide an RTC crystal
26 * + application : don't reset or disable the RTC.
27 */
28
29 /**
30 * Power profiling events enumeration.
31 *
32 * In order to maintain binary compatibility, only SOCW_EVENT_MAX should
33 * ever be altered: new events should be inserted before SOCW_EVENT_MAX,
34 * and SOCW_EVENT_MAX incremented. Add events, do not replace them.
35 */
36 typedef enum {
37 SOCW_EVENT_HALT = 0, /**< CPU Halt. */
38 SOCW_EVENT_INTERRUPT = 1, /**< CPU interrupt generated. */
39 SOCW_EVENT_SLEEP = 2, /**< Sleep mode entered. */
40 SOCW_EVENT_REGISTER = 3, /**< SOC register altered. */
41 SOCW_EVENT_APP = 4, /**< Application-defined event. */
42 SOCW_EVENT_FREQ = 5, /**< Frequency altered. */
43 SOCW_EVENT_MAX = 6 /**< End of events sentinel. */
44 } soc_watch_event_t;
45
46 /*
47 * Power profiling events for ARC Sensor states.
48 *
49 * Internally socwatch process the SS1 and SS2 as Halt
50 * Sleep events encoding respectively.
51 */
52 #define SOCW_ARC_EVENT_SS1 SOCW_EVENT_HALT
53 #define SOCW_ARC_EVENT_SS2 SOCW_EVENT_SLEEP
54
55 /**
56 * Register ID enumeration.
57 *
58 * The Register Event stores a register ID enumeration instead of a
59 * register address in order to save space. Registers can be added,
60 * but they should not be deleted, in order to preserve compatibility
61 * with different versions of the post-processor.
62 *
63 * Note that most of these names mirror the names used elsewhere in
64 * the QMSI code, although these are upper case, while the register
65 * pointer names are in lower case. That's one clue for identifying
66 * where logging calls should to be added: wherever you see one of the
67 * named registers below being written, you should consider that write
68 * may need a corresponding SoC Watch logging call.
69 */
70 #if (QUARK_D2000)
71 typedef enum {
72 /* Clock rate registers */
73 SOCW_REG_OSC0_CFG1 = 0, /**< 0x000 OSC0_CFG1 register. */
74 SOCW_REG_CCU_LP_CLK_CTL = 1, /**< 0x02C Clock Control register.*/
75 SOCW_REG_CCU_SYS_CLK_CTL = 2, /**< 0x038 System Clock Control. */
76 /* Clock gating registers. */
77 SOCW_REG_CCU_PERIPH_CLK_GATE_CTL = 3, /**< 0x018 Perip Clock Gate Ctl.*/
78 SOCW_REG_CCU_EXT_CLK_CTL = 4, /**< 0x024 CCU Ext Clock Gate Ctl.*/
79 /* Registers affecting power consumption */
80 SOCW_REG_CMP_PWR = 5, /**< 0x30C Comprtr Power Enable. */
81 SOCW_REG_PMUX_PULLUP = 6, /**< 0x900 Pin Mux Pullup. */
82 SOCW_REG_PMUX_SLEW = 7, /**< 0x910 Pin Mux Slew. */
83 SOCW_REG_PMUX_IN_EN = 8, /**< 0x920 Pin Mux In Enable. */
84 SOCW_REG_MAX, /**< Register enum sentinel. */
85 } soc_watch_reg_t;
86
87 #elif(QUARK_SE)
88 typedef enum {
89 /* Clock rate registers */
90 SOCW_REG_OSC0_CFG1 = 0, /**< 0x000 OSC0_CFG1 register. */
91 SOCW_REG_CCU_LP_CLK_CTL = 1, /**< 0x02C Clock Control register. */
92 SOCW_REG_CCU_SYS_CLK_CTL = 2, /**< 0x038 System Clock Control. */
93 /* Clock gating registers. */
94 SOCW_REG_CCU_PERIPH_CLK_GATE_CTL = 3, /**< 0x018 Perip Clock Gate Ctl.*/
95 SOCW_REG_CCU_SS_PERIPH_CLK_GATE_CTL = 4, /**< 0x0028 SS PCL Gate Ctl.*/
96 SOCW_REG_CCU_EXT_CLK_CTL = 5, /**< 0x024 CCU Ext Clock Gate Ctl.*/
97 /* Registers affecting power consumption */
98 SOCW_REG_CMP_PWR = 6, /**< 0x30C Comparator Power Enable. */
99 SOCW_REG_SLP_CFG = 7, /**< 0x550 Sleep Configuration. */
100 SOCW_REG_PMUX_PULLUP0 = 8, /**< 0x900 Pin Mux Pullup. */
101 SOCW_REG_PMUX_PULLUP1 = 9, /**< 0x904 Pin Mux Pullup. */
102 SOCW_REG_PMUX_PULLUP2 = 10, /**< 0x908 Pin Mux Pullup. */
103 SOCW_REG_PMUX_PULLUP3 = 11, /**< 0x90c Pin Mux Pullup. */
104 SOCW_REG_PMUX_SLEW0 = 12, /**< 0x910 Pin Mux Slew. */
105 SOCW_REG_PMUX_SLEW1 = 13, /**< 0x914 Pin Mux Slew. */
106 SOCW_REG_PMUX_SLEW2 = 14, /**< 0x918 Pin Mux Slew. */
107 SOCW_REG_PMUX_SLEW3 = 15, /**< 0x91c Pin Mux Slew. */
108 SOCW_REG_PMUX_IN_EN0 = 16, /**< 0x920 Pin Mux In Enable. */
109 SOCW_REG_PMUX_IN_EN1 = 17, /**< 0x924 Pin Mux In Enable. */
110 SOCW_REG_PMUX_IN_EN2 = 18, /**< 0x928 Pin Mux In Enable. */
111 SOCW_REG_PMUX_IN_EN3 = 19, /**< 0x92c Pin Mux In Enable. */
112 SOCW_REG_MAX, /**< Register enum sentinel. */
113 } soc_watch_reg_t;
114 #endif /* QUARK_SE */
115
116 /**
117 * Log a power profile event.
118 *
119 * Log an event related to power management. This should be things like
120 * halts, or register reads which cause us to go to low power states, or
121 * register reads that affect the clock rate, or other clock gating.
122 *
123 * @param[in] event_id The Event ID of the profile event.
124 * @param[in] ev_data A parameter to the event ID (if the event needs one).
125 */
126 void soc_watch_log_event(soc_watch_event_t event_id, uintptr_t ev_data);
127
128 /**
129 * Log an application event via the power profile logger.
130 *
131 * This allows applications layered on top of QMSI to log their own
132 * events. The subtype identifies the type of data for the user, and
133 * 'data' is the actual information being logged.
134 *
135 * @param[in] event_id The Event ID of the profile event.
136 * @param[in] ev_subtype A 1-byte user-defined event_id.
137 * @param[in] ev_data A parameter to the event ID (if the event needs one).
138 *
139 * @returns Nothing.
140 */
141 void soc_watch_log_app_event(soc_watch_event_t event_id, uint8_t ev_subtype,
142 uintptr_t ev_data);
143
144 /**
145 * Trigger a buffer flush via watchpoint.
146 * This allows applications layered on top of QMSI to trigger the transfer of
147 * profiler information to the host whenever it requires.
148 */
149 void soc_watch_trigger_flush();
150
151 /**
152 * @}
153 */
154
155 #endif /* __SOC_WATCH_H__ */
SOCW_EVENT_INTERRUPT
CPU interrupt generated.
Definition: soc_watch.h:38
SOCW_EVENT_FREQ
Frequency altered.
Definition: soc_watch.h:42
SOCW_EVENT_REGISTER
SOC register altered.
Definition: soc_watch.h:40
SOCW_REG_PMUX_PULLUP2
0x908 Pin Mux Pullup.
Definition: soc_watch.h:102
SOCW_REG_PMUX_PULLUP3
0x90c Pin Mux Pullup.
Definition: soc_watch.h:103
SOCW_EVENT_SLEEP
Sleep mode entered.
Definition: soc_watch.h:39
SOCW_REG_CCU_EXT_CLK_CTL
0x024 CCU Ext Clock Gate Ctl.
Definition: soc_watch.h:78
SOCW_REG_CCU_PERIPH_CLK_GATE_CTL
0x018 Perip Clock Gate Ctl.
Definition: soc_watch.h:77
SOCW_REG_CMP_PWR
0x30C Comprtr Power Enable.
Definition: soc_watch.h:80
SOCW_REG_PMUX_PULLUP0
0x900 Pin Mux Pullup.
Definition: soc_watch.h:100
SOCW_REG_CCU_LP_CLK_CTL
0x02C Clock Control register.
Definition: soc_watch.h:74
soc_watch_log_event
void soc_watch_log_event(soc_watch_event_t event_id, uintptr_t ev_data)
Log a power profile event.
Definition: soc_watch.c:334
SOCW_REG_PMUX_IN_EN2
0x928 Pin Mux In Enable.
Definition: soc_watch.h:110
soc_watch_trigger_flush
void soc_watch_trigger_flush()
Trigger a buffer flush via watchpoint.
Definition: soc_watch.c:467
SOCW_EVENT_HALT
CPU Halt.
Definition: soc_watch.h:37
SOCW_REG_PMUX_IN_EN1
0x924 Pin Mux In Enable.
Definition: soc_watch.h:109
soc_watch_event_t
soc_watch_event_t
Power profiling events enumeration.
Definition: soc_watch.h:36
SOCW_REG_PMUX_IN_EN3
0x92c Pin Mux In Enable.
Definition: soc_watch.h:111
SOCW_REG_PMUX_SLEW3
0x91c Pin Mux Slew.
Definition: soc_watch.h:107
SOCW_REG_PMUX_PULLUP1
0x904 Pin Mux Pullup.
Definition: soc_watch.h:101
SOCW_REG_PMUX_SLEW2
0x918 Pin Mux Slew.
Definition: soc_watch.h:106
soc_watch_log_app_event
void soc_watch_log_app_event(soc_watch_event_t event_id, uint8_t ev_subtype, uintptr_t ev_data)
Log an application event via the power profile logger.
Definition: soc_watch.c:344
SOCW_REG_OSC0_CFG1
0x000 OSC0_CFG1 register.
Definition: soc_watch.h:73
soc_watch_reg_t
soc_watch_reg_t
Register ID enumeration.
Definition: soc_watch.h:71
SOCW_REG_SLP_CFG
0x550 Sleep Configuration.
Definition: soc_watch.h:99
SOCW_EVENT_APP
Application-defined event.
Definition: soc_watch.h:41
SOCW_REG_PMUX_PULLUP
0x900 Pin Mux Pullup.
Definition: soc_watch.h:81
SOCW_REG_PMUX_SLEW1
0x914 Pin Mux Slew.
Definition: soc_watch.h:105
SOCW_REG_PMUX_IN_EN
0x920 Pin Mux In Enable.
Definition: soc_watch.h:83
SOCW_REG_CCU_SYS_CLK_CTL
0x038 System Clock Control.
Definition: soc_watch.h:75
SOCW_REG_PMUX_IN_EN0
0x920 Pin Mux In Enable.
Definition: soc_watch.h:108
SOCW_REG_PMUX_SLEW0
0x910 Pin Mux Slew.
Definition: soc_watch.h:104
SOCW_REG_MAX
Register enum sentinel.
Definition: soc_watch.h:84
SOCW_REG_PMUX_SLEW
0x910 Pin Mux Slew.
Definition: soc_watch.h:82
SOCW_REG_CCU_SS_PERIPH_CLK_GATE_CTL
0x0028 SS PCL Gate Ctl.
Definition: soc_watch.h:95
SOCW_EVENT_MAX
End of events sentinel.
Definition: soc_watch.h:43