Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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Enumerations | Functions
SOC_WATCH

SoC Watch (Energy Analyzer). More...

## Enumerations
enum | soc_watch_event_t { SOCW_EVENT_HALT = 0, SOCW_EVENT_INTERRUPT = 1, SOCW_EVENT_SLEEP = 2, SOCW_EVENT_REGISTER = 3, SOCW_EVENT_APP = 4, SOCW_EVENT_FREQ = 5, SOCW_EVENT_MAX = 6 }
| Power profiling events enumeration. More...
enum | soc_watch_reg_t { SOCW_REG_OSC0_CFG1 = 0, SOCW_REG_CCU_LP_CLK_CTL = 1, SOCW_REG_CCU_SYS_CLK_CTL = 2, SOCW_REG_CCU_PERIPH_CLK_GATE_CTL = 3, SOCW_REG_CCU_EXT_CLK_CTL = 4, SOCW_REG_CMP_PWR = 5, SOCW_REG_PMUX_PULLUP = 6, SOCW_REG_PMUX_SLEW = 7, SOCW_REG_PMUX_IN_EN = 8, SOCW_REG_MAX, SOCW_REG_OSC0_CFG1 = 0, SOCW_REG_CCU_LP_CLK_CTL = 1, SOCW_REG_CCU_SYS_CLK_CTL = 2, SOCW_REG_CCU_PERIPH_CLK_GATE_CTL = 3, SOCW_REG_CCU_SS_PERIPH_CLK_GATE_CTL = 4, SOCW_REG_CCU_EXT_CLK_CTL = 4, SOCW_REG_CMP_PWR = 5, SOCW_REG_SLP_CFG = 7, SOCW_REG_PMUX_PULLUP0 = 8, SOCW_REG_PMUX_PULLUP1 = 9, SOCW_REG_PMUX_PULLUP2 = 10, SOCW_REG_PMUX_PULLUP3 = 11, SOCW_REG_PMUX_SLEW0 = 12, SOCW_REG_PMUX_SLEW1 = 13, SOCW_REG_PMUX_SLEW2 = 14, SOCW_REG_PMUX_SLEW3 = 15, SOCW_REG_PMUX_IN_EN0 = 16, SOCW_REG_PMUX_IN_EN1 = 17, SOCW_REG_PMUX_IN_EN2 = 18, SOCW_REG_PMUX_IN_EN3 = 19, SOCW_REG_MAX }
| Register ID enumeration. More...
enum | soc_watch_reg_t { SOCW_REG_OSC0_CFG1 = 0, SOCW_REG_CCU_LP_CLK_CTL = 1, SOCW_REG_CCU_SYS_CLK_CTL = 2, SOCW_REG_CCU_PERIPH_CLK_GATE_CTL = 3, SOCW_REG_CCU_EXT_CLK_CTL = 4, SOCW_REG_CMP_PWR = 5, SOCW_REG_PMUX_PULLUP = 6, SOCW_REG_PMUX_SLEW = 7, SOCW_REG_PMUX_IN_EN = 8, SOCW_REG_MAX, SOCW_REG_OSC0_CFG1 = 0, SOCW_REG_CCU_LP_CLK_CTL = 1, SOCW_REG_CCU_SYS_CLK_CTL = 2, SOCW_REG_CCU_PERIPH_CLK_GATE_CTL = 3, SOCW_REG_CCU_SS_PERIPH_CLK_GATE_CTL = 4, SOCW_REG_CCU_EXT_CLK_CTL = 4, SOCW_REG_CMP_PWR = 5, SOCW_REG_SLP_CFG = 7, SOCW_REG_PMUX_PULLUP0 = 8, SOCW_REG_PMUX_PULLUP1 = 9, SOCW_REG_PMUX_PULLUP2 = 10, SOCW_REG_PMUX_PULLUP3 = 11, SOCW_REG_PMUX_SLEW0 = 12, SOCW_REG_PMUX_SLEW1 = 13, SOCW_REG_PMUX_SLEW2 = 14, SOCW_REG_PMUX_SLEW3 = 15, SOCW_REG_PMUX_IN_EN0 = 16, SOCW_REG_PMUX_IN_EN1 = 17, SOCW_REG_PMUX_IN_EN2 = 18, SOCW_REG_PMUX_IN_EN3 = 19, SOCW_REG_MAX }

## Functions
void | soc_watch_log_event (soc_watch_event_t event_id, uintptr_t ev_data)
| Log a power profile event. More...
void | soc_watch_log_app_event (soc_watch_event_t event_id, uint8_t ev_subtype, uintptr_t ev_data)
| Log an application event via the power profile logger. More...
void | soc_watch_trigger_flush ()
| Trigger a buffer flush via watchpoint. More...

## Detailed Description

SoC Watch (Energy Analyzer).

SoC Pins definition.

## Enumeration Type Documentation

enum soc_watch_event_t

Power profiling events enumeration.

In order to maintain binary compatibility, only SOCW_EVENT_MAX should ever be altered: new events should be inserted before SOCW_EVENT_MAX, and SOCW_EVENT_MAX incremented. Add events, do not replace them.

Enumerator
SOCW_EVENT_HALT | CPU Halt.
SOCW_EVENT_INTERRUPT | CPU interrupt generated.
SOCW_EVENT_SLEEP | Sleep mode entered.
SOCW_EVENT_REGISTER | SOC register altered.
SOCW_EVENT_APP | Application-defined event.
SOCW_EVENT_FREQ | Frequency altered.
SOCW_EVENT_MAX | End of events sentinel.

Definition at line 36 of file soc_watch.h.

enum soc_watch_reg_t

Register ID enumeration.

The Register Event stores a register ID enumeration instead of a register address in order to save space. Registers can be added, but they should not be deleted, in order to preserve compatibility with different versions of the post-processor.

Note that most of these names mirror the names used elsewhere in the QMSI code, although these are upper case, while the register pointer names are in lower case. That's one clue for identifying where logging calls should to be added: wherever you see one of the named registers below being written, you should consider that write may need a corresponding SoC Watch logging call.

Enumerator
SOCW_REG_OSC0_CFG1 | 0x000 OSC0_CFG1 register.
SOCW_REG_CCU_LP_CLK_CTL | 0x02C Clock Control register.
SOCW_REG_CCU_SYS_CLK_CTL | 0x038 System Clock Control.
SOCW_REG_CCU_PERIPH_CLK_GATE_CTL | 0x018 Perip Clock Gate Ctl.
SOCW_REG_CCU_EXT_CLK_CTL | 0x024 CCU Ext Clock Gate Ctl.
SOCW_REG_CMP_PWR | 0x30C Comprtr Power Enable. 0x30C Comparator Power Enable.
SOCW_REG_PMUX_PULLUP | 0x900 Pin Mux Pullup.
SOCW_REG_PMUX_SLEW | 0x910 Pin Mux Slew.
SOCW_REG_PMUX_IN_EN | 0x920 Pin Mux In Enable.
SOCW_REG_MAX | Register enum sentinel.
SOCW_REG_OSC0_CFG1 | 0x000 OSC0_CFG1 register.
SOCW_REG_CCU_LP_CLK_CTL | 0x02C Clock Control register.
SOCW_REG_CCU_SYS_CLK_CTL | 0x038 System Clock Control.
SOCW_REG_CCU_PERIPH_CLK_GATE_CTL | 0x018 Perip Clock Gate Ctl.
SOCW_REG_CCU_SS_PERIPH_CLK_GATE_CTL | 0x0028 SS PCL Gate Ctl.
SOCW_REG_CCU_EXT_CLK_CTL | 0x024 CCU Ext Clock Gate Ctl.
SOCW_REG_CMP_PWR | 0x30C Comprtr Power Enable. 0x30C Comparator Power Enable.
SOCW_REG_SLP_CFG | 0x550 Sleep Configuration.
SOCW_REG_PMUX_PULLUP0 | 0x900 Pin Mux Pullup.
SOCW_REG_PMUX_PULLUP1 | 0x904 Pin Mux Pullup.
SOCW_REG_PMUX_PULLUP2 | 0x908 Pin Mux Pullup.
SOCW_REG_PMUX_PULLUP3 | 0x90c Pin Mux Pullup.
SOCW_REG_PMUX_SLEW0 | 0x910 Pin Mux Slew.
SOCW_REG_PMUX_SLEW1 | 0x914 Pin Mux Slew.
SOCW_REG_PMUX_SLEW2 | 0x918 Pin Mux Slew.
SOCW_REG_PMUX_SLEW3 | 0x91c Pin Mux Slew.
SOCW_REG_PMUX_IN_EN0 | 0x920 Pin Mux In Enable.
SOCW_REG_PMUX_IN_EN1 | 0x924 Pin Mux In Enable.
SOCW_REG_PMUX_IN_EN2 | 0x928 Pin Mux In Enable.
SOCW_REG_PMUX_IN_EN3 | 0x92c Pin Mux In Enable.
SOCW_REG_MAX | Register enum sentinel.

Definition at line 71 of file soc_watch.h.

enum soc_watch_reg_t

Enumerator
SOCW_REG_OSC0_CFG1 | 0x000 OSC0_CFG1 register.
SOCW_REG_CCU_LP_CLK_CTL | 0x02C Clock Control register.
SOCW_REG_CCU_SYS_CLK_CTL | 0x038 System Clock Control.
SOCW_REG_CCU_PERIPH_CLK_GATE_CTL | 0x018 Perip Clock Gate Ctl.
SOCW_REG_CCU_EXT_CLK_CTL | 0x024 CCU Ext Clock Gate Ctl.
SOCW_REG_CMP_PWR | 0x30C Comprtr Power Enable. 0x30C Comparator Power Enable.
SOCW_REG_PMUX_PULLUP | 0x900 Pin Mux Pullup.
SOCW_REG_PMUX_SLEW | 0x910 Pin Mux Slew.
SOCW_REG_PMUX_IN_EN | 0x920 Pin Mux In Enable.
SOCW_REG_MAX | Register enum sentinel.
SOCW_REG_OSC0_CFG1 | 0x000 OSC0_CFG1 register.
SOCW_REG_CCU_LP_CLK_CTL | 0x02C Clock Control register.
SOCW_REG_CCU_SYS_CLK_CTL | 0x038 System Clock Control.
SOCW_REG_CCU_PERIPH_CLK_GATE_CTL | 0x018 Perip Clock Gate Ctl.
SOCW_REG_CCU_SS_PERIPH_CLK_GATE_CTL | 0x0028 SS PCL Gate Ctl.
SOCW_REG_CCU_EXT_CLK_CTL | 0x024 CCU Ext Clock Gate Ctl.
SOCW_REG_CMP_PWR | 0x30C Comprtr Power Enable. 0x30C Comparator Power Enable.
SOCW_REG_SLP_CFG | 0x550 Sleep Configuration.
SOCW_REG_PMUX_PULLUP0 | 0x900 Pin Mux Pullup.
SOCW_REG_PMUX_PULLUP1 | 0x904 Pin Mux Pullup.
SOCW_REG_PMUX_PULLUP2 | 0x908 Pin Mux Pullup.
SOCW_REG_PMUX_PULLUP3 | 0x90c Pin Mux Pullup.
SOCW_REG_PMUX_SLEW0 | 0x910 Pin Mux Slew.
SOCW_REG_PMUX_SLEW1 | 0x914 Pin Mux Slew.
SOCW_REG_PMUX_SLEW2 | 0x918 Pin Mux Slew.
SOCW_REG_PMUX_SLEW3 | 0x91c Pin Mux Slew.
SOCW_REG_PMUX_IN_EN0 | 0x920 Pin Mux In Enable.
SOCW_REG_PMUX_IN_EN1 | 0x924 Pin Mux In Enable.
SOCW_REG_PMUX_IN_EN2 | 0x928 Pin Mux In Enable.
SOCW_REG_PMUX_IN_EN3 | 0x92c Pin Mux In Enable.
SOCW_REG_MAX | Register enum sentinel.

Definition at line 88 of file soc_watch.h.

## Function Documentation

void soc_watch_log_app_event | ( | soc_watch_event_t | event_id,
|  | uint8_t | ev_subtype,
|  | uintptr_t | ev_data
| ) |  |

Log an application event via the power profile logger.

This allows applications layered on top of QMSI to log their own events. The subtype identifies the type of data for the user, and 'data' is the actual information being logged.

Parameters

  [in] | event_id | The Event ID of the profile event.
  [in] | ev_subtype | A 1-byte user-defined event_id.
  [in] | ev_data | A parameter to the event ID (if the event needs one).

Returns
  Nothing.

Definition at line 344 of file soc_watch.c.

References SOCW_EVENT_HALT, SOCW_EVENT_INTERRUPT, SOCW_EVENT_MAX, and SOCW_EVENT_SLEEP.

Referenced by soc_watch_log_event().

void soc_watch_log_event | ( | soc_watch_event_t | event_id,
|  | uintptr_t | ev_data
| ) |  |

Log a power profile event.

Log an event related to power management. This should be things like halts, or register reads which cause us to go to low power states, or register reads that affect the clock rate, or other clock gating.

Parameters

  [in] | event_id | The Event ID of the profile event.
  [in] | ev_data | A parameter to the event ID (if the event needs one).

Definition at line 334 of file soc_watch.c.

References soc_watch_log_app_event().

void soc_watch_trigger_flush | ( |  | ) |

Trigger a buffer flush via watchpoint.

This allows applications layered on top of QMSI to trigger the transfer of profiler information to the host whenever it requires.

Definition at line 467 of file soc_watch.c.