Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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ISR

Interrupt Service Routines. More...

## Functions
| QM_ISR_DECLARE (qm_adc_0_cal_isr)
| ISR for ADC 0 convert and calibration interrupt. More...
| QM_ISR_DECLARE (qm_adc_0_pwr_isr)
| ISR for ADC 0 change mode interrupt. More...
| QM_ISR_DECLARE (qm_aonpt_0_isr)
| ISR for Always-on Periodic Timer 0 interrupt. More...
| QM_ISR_DECLARE (qm_comparator_0_isr)
| ISR for Analog Comparator 0 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_error_isr)
| ISR for DMA error interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_0)
| ISR for DMA channel 0 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_1)
| ISR for DMA channel 1 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_2)
| ISR for DMA channel 2 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_3)
| ISR for DMA channel 3 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_4)
| ISR for DMA channel 4 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_5)
| ISR for DMA channel 5 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_6)
| ISR for DMA channel 6 interrupt. More...
| QM_ISR_DECLARE (qm_dma_0_isr_7)
| ISR for DMA 0 channel 7 interrupt. More...
| QM_ISR_DECLARE (qm_flash_mpr_0_isr)
| ISR for FPR 0 interrupt. More...
| QM_ISR_DECLARE (qm_flash_mpr_1_isr)
| ISR for FPR 1 interrupt. More...
| QM_ISR_DECLARE (qm_gpio_0_isr)
| ISR for GPIO 0 interrupt. More...
| QM_ISR_DECLARE (qm_aon_gpio_0_isr)
| ISR for AON GPIO 0 interrupt. More...
| QM_ISR_DECLARE (qm_i2c_0_irq_isr)
| ISR for I2C 0 irq mode transfer interrupt. More...
| QM_ISR_DECLARE (qm_i2c_1_irq_isr)
| ISR for I2C 1 irq mode transfer interrupt. More...
| QM_ISR_DECLARE (qm_i2c_0_dma_isr)
| ISR for I2C 0 dma mode transfer interrupt. More...
| QM_ISR_DECLARE (qm_i2c_1_dma_isr)
| ISR for I2C 1 dma mode transfer interrupt. More...
| QM_ISR_DECLARE (qm_mailbox_0_isr)
| ISR for Mailbox interrupt. More...
| QM_ISR_DECLARE (qm_sram_mpr_0_isr)
| ISR for Memory Protection Region interrupt. More...
| QM_ISR_DECLARE (qm_pic_timer_0_isr)
| ISR for PIC Timer interrupt. More...
| QM_ISR_DECLARE (qm_pwm_0_isr_0)
| ISR for PWM 0 Channel 0 interrupt. More...
| QM_ISR_DECLARE (qm_pwm_0_isr_1)
| ISR for PWM 0 channel 1 interrupt. More...
| QM_ISR_DECLARE (qm_pwm_0_isr_2)
| ISR for PWM 0 channel 2 interrupt. More...
| QM_ISR_DECLARE (qm_pwm_0_isr_3)
| ISR for PWM 0 channel 3 interrupt. More...
| QM_ISR_DECLARE (qm_rtc_0_isr)
| ISR for RTC 0 interrupt. More...
| QM_ISR_DECLARE (qm_spi_master_0_isr)
| ISR for SPI Master 0 interrupt. More...
| QM_ISR_DECLARE (qm_spi_master_1_isr)
| ISR for SPI Master 1 interrupt. More...
| QM_ISR_DECLARE (qm_spi_slave_0_isr)
| ISR for SPI Slave 0 interrupt. More...
| QM_ISR_DECLARE (qm_uart_0_isr)
| ISR for UART 0 interrupt. More...
| QM_ISR_DECLARE (qm_uart_1_isr)
| ISR for UART 1 interrupt. More...
| QM_ISR_DECLARE (qm_wdt_0_isr)
| ISR for WDT 0 interrupt. More...
| QM_ISR_DECLARE (qm_wdt_1_isr)
| ISR for WDT 1 interrupt. More...
| QM_ISR_DECLARE (qm_usb_0_isr)
| ISR for USB 0 interrupt. More...

## Detailed Description

Interrupt Service Routines.

## Function Documentation

QM_ISR_DECLARE | ( | qm_adc_0_cal_isr |  | ) |

ISR for ADC 0 convert and calibration interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_ADC_0_CAL_INT, qm_adc_0_cal_isr);

if IRQ based transfers are used.

Definition at line 166 of file qm_adc.c.

QM_ISR_DECLARE | ( | qm_adc_0_pwr_isr |  | ) |

ISR for ADC 0 change mode interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_ADC_0_PWR_INT, qm_adc_0_pwr_isr);

if IRQ based transfers are used.

Definition at line 174 of file qm_adc.c.

QM_ISR_DECLARE | ( | qm_aonpt_0_isr |  | ) |

ISR for Always-on Periodic Timer 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_AONPT_0_INT, qm_aonpt_0_isr);

if IRQ based transfers are used.

Definition at line 103 of file qm_aon_counters.c.

References qm_power_soc_restore().

QM_ISR_DECLARE | ( | qm_comparator_0_isr |  | ) |

ISR for Analog Comparator 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_COMPARATOR_0_INT, qm_comparator_0_isr);

if IRQ based transfers are used.

Definition at line 17 of file qm_comparator.c.

References qm_power_soc_restore().

QM_ISR_DECLARE | ( | qm_dma_0_error_isr |  | ) |

ISR for DMA error interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_ERROR_INT, qm_dma_0_error_isr);

if IRQ based transfers are used.

Definition at line 152 of file qm_dma.c.

References QM_DMA_0.

QM_ISR_DECLARE | ( | qm_dma_0_isr_0 |  | ) |

ISR for DMA channel 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_0, qm_dma_0_isr_0);

if IRQ based transfers are used.

Definition at line 158 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_0.

QM_ISR_DECLARE | ( | qm_dma_0_isr_1 |  | ) |

ISR for DMA channel 1 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_1, qm_dma_0_isr_1);

if IRQ based transfers are used.

Definition at line 164 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_1.

QM_ISR_DECLARE | ( | qm_dma_0_isr_2 |  | ) |

ISR for DMA channel 2 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_2, qm_dma_0_isr_2);

if IRQ based transfers are used.

Definition at line 171 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_2.

QM_ISR_DECLARE | ( | qm_dma_0_isr_3 |  | ) |

ISR for DMA channel 3 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_3, qm_dma_0_isr_3);

if IRQ based transfers are used.

Definition at line 177 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_3.

QM_ISR_DECLARE | ( | qm_dma_0_isr_4 |  | ) |

ISR for DMA channel 4 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_4, qm_dma_0_isr_4);

if IRQ based transfers are used.

Definition at line 183 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_4.

QM_ISR_DECLARE | ( | qm_dma_0_isr_5 |  | ) |

ISR for DMA channel 5 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_5, qm_dma_0_isr_5);

if IRQ based transfers are used.

Definition at line 189 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_5.

QM_ISR_DECLARE | ( | qm_dma_0_isr_6 |  | ) |

ISR for DMA channel 6 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_6, qm_dma_0_isr_6);

if IRQ based transfers are used.

Definition at line 195 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_6.

QM_ISR_DECLARE | ( | qm_dma_0_isr_7 |  | ) |

ISR for DMA 0 channel 7 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_7, qm_dma_0_isr_7);

if IRQ based transfers are used.

Definition at line 201 of file qm_dma.c.

References QM_DMA_0, and QM_DMA_CHANNEL_7.

QM_ISR_DECLARE | ( | qm_flash_mpr_0_isr |  | ) |

ISR for FPR 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_FLASH_MPR_0_INT, qm_flash_mpr_0_isr);

if IRQ based transfers are used.

Definition at line 12 of file qm_fpr.c.

QM_ISR_DECLARE | ( | qm_flash_mpr_1_isr |  | ) |

ISR for FPR 1 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_FLASH_MPR_1_INT, qm_flash_mpr_1_isr);

if IRQ based transfers are used.

Definition at line 23 of file qm_fpr.c.

QM_ISR_DECLARE | ( | qm_gpio_0_isr |  | ) |

ISR for GPIO 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_GPIO_0_INT, qm_gpio_0_isr);

if IRQ based transfers are used.

Definition at line 45 of file qm_gpio.c.

QM_ISR_DECLARE | ( | qm_aon_gpio_0_isr |  | ) |

ISR for AON GPIO 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_AON_GPIO_0_INT, qm_aon_gpio_0_isr);

if IRQ based transfers are used.

Definition at line 52 of file qm_gpio.c.

QM_ISR_DECLARE | ( | qm_i2c_0_irq_isr |  | ) |

ISR for I2C 0 irq mode transfer interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_I2C_0_INT, qm_i2c_0_irq_isr);

if IRQ based transfers are used.

Definition at line 711 of file qm_i2c.c.

QM_ISR_DECLARE | ( | qm_i2c_1_irq_isr |  | ) |

ISR for I2C 1 irq mode transfer interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_I2C_1_INT, qm_i2c_1_irq_isr);

if IRQ based transfers are used.

Definition at line 724 of file qm_i2c.c.

QM_ISR_DECLARE | ( | qm_i2c_0_dma_isr |  | ) |

ISR for I2C 0 dma mode transfer interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_I2C_0_INT, qm_i2c_0_dma_isr);

if DMA based transfers are used.

Definition at line 717 of file qm_i2c.c.

QM_ISR_DECLARE | ( | qm_i2c_1_dma_isr |  | ) |

ISR for I2C 1 dma mode transfer interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_I2C_1_INT, qm_i2c_1_dma_isr);

if DMA based transfers are used.

Definition at line 730 of file qm_i2c.c.

QM_ISR_DECLARE | ( | qm_mailbox_0_isr |  | ) |

ISR for Mailbox interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_MAILBOX_0_INT, qm_mailbox_0_isr);

if IRQ based transfers are used.

Definition at line 66 of file qm_mailbox_se.c.

QM_ISR_DECLARE | ( | qm_sram_mpr_0_isr |  | ) |

ISR for Memory Protection Region interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_SRAM_MPR_0_INT, qm_sram_mpr_0_isr);

if IRQ based transfers are used.

Definition at line 14 of file qm_mpr.c.

QM_ISR_DECLARE | ( | qm_pic_timer_0_isr |  | ) |

ISR for PIC Timer interrupt.

On Quark Microcontroller D2000 Development Platform, this function needs to be registered with:

qm_int_vector_request(QM_X86_PIC_TIMER_INT_VECTOR,
qm_pic_timer_0_isr);

if IRQ based transfers are used.

On Quark SE, this function needs to be registered with:

QM_IRQ_REQUEST(QM_IRQ_PIC_TIMER, qm_pic_timer_0_isr);

if IRQ based transfers are used.

Definition at line 27 of file qm_pic_timer.c.

QM_ISR_DECLARE | ( | qm_pwm_0_isr_0 |  | ) |

ISR for PWM 0 Channel 0 interrupt.

If there is only one interrupt per controller this ISR handles all channel interrupts.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_PWM_0_INT, qm_pwm_0_isr);

if IRQ based transfers are used.

Definition at line 62 of file qm_pwm.c.

References qm_pwm_channel_t::eoi, qm_pwm_reg_t::timer, and qm_pwm_reg_t::timersintstatus.

QM_ISR_DECLARE | ( | qm_pwm_0_isr_1 |  | ) |

ISR for PWM 0 channel 1 interrupt.

This function needs to be registered with

qm_irq_request(QM_IRQ_PWM_1, qm_pwm_0_isr_1);

if IRQ based transfers are used.

Definition at line 46 of file qm_pwm.c.

QM_ISR_DECLARE | ( | qm_pwm_0_isr_2 |  | ) |

ISR for PWM 0 channel 2 interrupt.

This function needs to be registered with

qm_irq_request(QM_IRQ_PWM_2, qm_pwm_0_isr_2);

if IRQ based transfers are used.

Definition at line 51 of file qm_pwm.c.

QM_ISR_DECLARE | ( | qm_pwm_0_isr_3 |  | ) |

ISR for PWM 0 channel 3 interrupt.

This function needs to be registered with

qm_irq_request(QM_IRQ_PWM_3, qm_pwm_0_isr_3);

if IRQ based transfers are used.

Definition at line 56 of file qm_pwm.c.

QM_ISR_DECLARE | ( | qm_rtc_0_isr |  | ) |

ISR for RTC 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);

if IRQ based transfers are used.

Definition at line 18 of file qm_rtc.c.

References qm_power_soc_restore().

QM_ISR_DECLARE | ( | qm_spi_master_0_isr |  | ) |

ISR for SPI Master 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_SPI_MASTER_0_INT, qm_spi_master_0_isr);

if IRQ based transfers are used.

Definition at line 716 of file qm_spi.c.

QM_ISR_DECLARE | ( | qm_spi_master_1_isr |  | ) |

ISR for SPI Master 1 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_SPI_MASTER_1_INT, qm_spi_master_1_isr);

if IRQ based transfers are used.

Definition at line 723 of file qm_spi.c.

QM_ISR_DECLARE | ( | qm_spi_slave_0_isr |  | ) |

ISR for SPI Slave 0 interrupt.

This function needs to be registered with

qm_irq_request(QM_IRQ_SPI_SLAVE_0_INT, qm_spi_slave_0_isr);

if IRQ based transfers are used.

Definition at line 730 of file qm_spi.c.

QM_ISR_DECLARE | ( | qm_uart_0_isr |  | ) |

ISR for UART 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_UART_0_INT, qm_uart_0_isr);

if IRQ based transfers are used.

Definition at line 203 of file qm_uart.c.

QM_ISR_DECLARE | ( | qm_uart_1_isr |  | ) |

ISR for UART 1 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_UART_1_INT, qm_uart_1_isr);

if IRQ based transfers are used.

Definition at line 209 of file qm_uart.c.

QM_ISR_DECLARE | ( | qm_wdt_0_isr |  | ) |

ISR for WDT 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_WDT_0_INT, qm_wdt_0_isr);

if IRQ based transfers are used.

Definition at line 20 of file qm_wdt.c.

QM_ISR_DECLARE | ( | qm_wdt_1_isr |  | ) |

ISR for WDT 1 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_WDT_1_INT, qm_wdt_1_isr);

if IRQ based transfers are used.

Definition at line 32 of file qm_wdt.c.

QM_ISR_DECLARE | ( | qm_usb_0_isr |  | ) |

ISR for USB 0 interrupt.

This function needs to be registered with

QM_IRQ_REQUEST(QM_IRQ_USB_0_INT, qm_usb_0_isr);

if IRQ based transfers are used.

Definition at line 410 of file qm_usb.c.