Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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ss_clk.c
1 /*
2 * {% copyright %}
3 */
4
5 #include "qm_common.h"
6 #include "ss_clk.h"
7
8 int ss_clk_gpio_enable(const qm_ss_gpio_t gpio)
9 {
10 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
11 int addr =
12 (gpio == QM_SS_GPIO_0) ? QM_SS_GPIO_0_BASE : QM_SS_GPIO_1_BASE;
13 __builtin_arc_sr(QM_SS_GPIO_LS_SYNC_CLK_EN |
14 QM_SS_GPIO_LS_SYNC_SYNC_LVL,
15 addr + QM_SS_GPIO_LS_SYNC);
16 return 0;
17 }
18
19 int ss_clk_gpio_disable(const qm_ss_gpio_t gpio)
20 {
21 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
22 int addr =
23 (gpio == QM_SS_GPIO_0) ? QM_SS_GPIO_0_BASE : QM_SS_GPIO_1_BASE;
24 __builtin_arc_sr(0, addr + QM_SS_GPIO_LS_SYNC);
25 return 0;
26 }
27
28 int ss_clk_spi_enable(const qm_ss_spi_t spi)
29 {
30 QM_CHECK(spi < QM_SS_SPI_NUM, -EINVAL);
31 int addr = (spi == QM_SS_SPI_0) ? QM_SS_SPI_0_BASE : QM_SS_SPI_1_BASE;
32 QM_SS_REG_AUX_OR(addr + QM_SS_SPI_CTRL, QM_SS_SPI_CTRL_CLK_ENA);
33 return 0;
34 }
35
36 int ss_clk_spi_disable(const qm_ss_spi_t spi)
37 {
38 QM_CHECK(spi < QM_SS_SPI_NUM, -EINVAL);
39 int addr = (spi == QM_SS_SPI_0) ? QM_SS_SPI_0_BASE : QM_SS_SPI_1_BASE;
40 QM_SS_REG_AUX_NAND(addr + QM_SS_SPI_CTRL, QM_SS_SPI_CTRL_CLK_ENA);
41 return 0;
42 }
43
44 int ss_clk_i2c_enable(const qm_ss_i2c_t i2c)
45 {
46 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
47 int addr = (i2c == QM_SS_I2C_0) ? QM_SS_I2C_0_BASE : QM_SS_I2C_1_BASE;
48 QM_SS_REG_AUX_OR(addr + QM_SS_I2C_CON, QM_SS_I2C_CON_CLK_ENA);
49 return 0;
50 }
51
52 int ss_clk_i2c_disable(const qm_ss_i2c_t i2c)
53 {
54 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
55 int addr = (i2c == QM_SS_I2C_0) ? QM_SS_I2C_0_BASE : QM_SS_I2C_1_BASE;
56 QM_SS_REG_AUX_NAND(addr + QM_SS_I2C_CON, QM_SS_I2C_CON_CLK_ENA);
57 return 0;
58 }
59
60 int ss_clk_adc_enable(void)
61 {
62 /* Enable the ADC clock */
63 QM_SS_REG_AUX_OR(QM_SS_ADC_BASE + QM_SS_ADC_CTRL,
64 QM_SS_ADC_CTRL_CLK_ENA);
65 return 0;
66 }
67
68 int ss_clk_adc_disable(void)
69 {
70 /* Disable the ADC clock */
71 QM_SS_REG_AUX_NAND(QM_SS_ADC_BASE + QM_SS_ADC_CTRL,
72 QM_SS_ADC_CTRL_CLK_ENA);
73 return 0;
74 }
75
76 int ss_clk_adc_set_div(const uint32_t div)
77 {
78 uint32_t reg;
79
80 /*
81 * Scale the max divisor with the system clock speed. Clock speeds less
82 * than 1 MHz will not work properly.
83 */
84 QM_CHECK(div <= QM_SS_ADC_DIV_MAX * clk_sys_get_ticks_per_us(),
85 -EINVAL);
86
87 /* Set the ADC divisor */
88 reg = __builtin_arc_lr(QM_SS_ADC_BASE + QM_SS_ADC_DIVSEQSTAT);
89 reg &= ~(QM_SS_ADC_DIVSEQSTAT_CLK_RATIO_MASK);
90 __builtin_arc_sr(reg | div, QM_SS_ADC_BASE + QM_SS_ADC_DIVSEQSTAT);
91
92 return 0;
93 }
ss_clk_spi_enable
int ss_clk_spi_enable(const qm_ss_spi_t spi)
Enable clocking for SS SPI peripheral.
Definition: ss_clk.c:28
ss_clk_gpio_enable
int ss_clk_gpio_enable(const qm_ss_gpio_t gpio)
Enable clocking for SS GPIO peripheral.
Definition: ss_clk.c:8
QM_SS_ADC_DIVSEQSTAT
ADC clock and sequencer status register.
Definition: qm_sensor_regs.h:543
QM_SS_SPI_0
SPI module 0.
Definition: qm_sensor_regs.h:705
qm_ss_gpio_t
qm_ss_gpio_t
Sensor Subsystem GPIO.
Definition: qm_sensor_regs.h:196
ss_clk_i2c_disable
int ss_clk_i2c_disable(const qm_ss_i2c_t i2c)
Disable clocking for SS I2C peripheral.
Definition: ss_clk.c:52
qm_ss_i2c_t
qm_ss_i2c_t
Sensor Subsystem I2C.
Definition: qm_sensor_regs.h:532
ss_clk_adc_set_div
int ss_clk_adc_set_div(const uint32_t div)
Set clock divisor for SS ADC.
Definition: ss_clk.c:76
ss_clk_adc_disable
int ss_clk_adc_disable(void)
Disable the SS ADC clock.
Definition: ss_clk.c:68
QM_SS_ADC_CTRL
ADC control register.
Definition: qm_sensor_regs.h:545
clk_sys_get_ticks_per_us
uint32_t clk_sys_get_ticks_per_us(void)
Get number of system ticks per micro second.
Definition: clk.c:347
ss_clk_spi_disable
int ss_clk_spi_disable(const qm_ss_spi_t spi)
Disable clocking for SS SPI peripheral.
Definition: ss_clk.c:36
ss_clk_gpio_disable
int ss_clk_gpio_disable(const qm_ss_gpio_t gpio)
Disable clocking for SS GPIO peripheral.
Definition: ss_clk.c:19
ss_clk_i2c_enable
int ss_clk_i2c_enable(const qm_ss_i2c_t i2c)
Enable clocking for SS I2C peripheral.
Definition: ss_clk.c:44
QM_SS_SPI_CTRL
SPI control register.
Definition: qm_sensor_regs.h:677
qm_ss_spi_t
qm_ss_spi_t
Sensor Subsystem SPI modules.
Definition: qm_sensor_regs.h:704
ss_clk_adc_enable
int ss_clk_adc_enable(void)
Enable the SS ADC clock.
Definition: ss_clk.c:60