Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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Data Fields
qm_interrupt_router_reg_t Struct Reference
SoC Interrupt Router (D2000) | SoC Interrupt Router (SE)

Interrupt register map. More...

`#include <qm_interrupt_router_regs.h>`

## Data Fields
QM_RW uint32_t | i2c_master_0_int_mask
| I2C Master 0, Mask 0. More...
QM_RW uint32_t | spi_master_0_int_mask
| SPI Master 0, Mask 3. More...
QM_RW uint32_t | spi_slave_0_int_mask
| SPI Slave 0, Mask 5. More...
QM_RW uint32_t | uart_0_int_mask
| UART 0, Mask 6. More...
QM_RW uint32_t | uart_1_int_mask
| UART 1, Mask 7. More...
QM_RW uint32_t | gpio_0_int_mask
| GPIO 0, Mask 9. More...
QM_RW uint32_t | timer_0_int_mask
| Timer 0, Mask 10. More...
QM_RW uint32_t | rtc_0_int_mask
| RTC 0, Mask 12. More...
QM_RW uint32_t | wdt_0_int_mask
| WDT 0, Mask 13. More...
QM_RW uint32_t | dma_0_int_0_mask
| DMA 0 int 0, Mask 14. More...
QM_RW uint32_t | dma_0_int_1_mask
| DMA 0 int 1, Mask 15. More...
QM_RW uint32_t | comparator_0_host_halt_int_mask
| Comparator 0 Host halt, Mask 24. More...
QM_RW uint32_t | comparator_0_host_int_mask
| Comparator 0 Host, Mask 26. More...
QM_RW uint32_t | host_bus_error_int_mask
| Host bus error, Mask 27. More...
QM_RW uint32_t | dma_0_error_int_mask
| DMA 0 Error, Mask 28. More...
QM_RW uint32_t | sram_mpr_0_int_mask
| SRAM MPR 0, Mask 29. More...
QM_RW uint32_t | flash_mpr_0_int_mask
| Flash MPR 0, Mask 30. More...
QM_RW uint32_t | aonpt_0_int_mask
| AONPT 0, Mask 32. More...
QM_RW uint32_t | adc_0_pwr_int_mask
| ADC 0 PWR, Mask 33. More...
QM_RW uint32_t | adc_0_cal_int_mask
| ADC 0 CAL, Mask 34. More...
QM_RW uint32_t | lock_int_mask_reg
| Interrupt Mask Lock Register. More...
QM_RW uint32_t | ss_adc_0_error_int_mask
| Sensor ADC 0 Error. More...
QM_RW uint32_t | ss_adc_0_int_mask
| Sensor ADC 0. More...
QM_RW uint32_t | ss_gpio_0_int_mask
| Sensor GPIO 0. More...
QM_RW uint32_t | ss_gpio_1_int_mask
| Sensor GPIO 1. More...
int_ss_i2c_reg_t | ss_i2c_0_int
| Sensor I2C 0 Masks. More...
int_ss_i2c_reg_t | ss_i2c_1_int
| Sensor I2C 1 Masks. More...
int_ss_spi_reg_t | ss_spi_0_int
| Sensor SPI 0 Masks. More...
int_ss_spi_reg_t | ss_spi_1_int
| Sensor SPI 1 Masks. More...
QM_RW uint32_t | i2c_master_1_int_mask
| I2C Master 1. More...
QM_RW uint32_t | spi_master_1_int_mask
| SPI Master 1. More...
QM_RW uint32_t | i2s_0_int_mask
| I2S 0. More...
QM_RW uint32_t | pwm_0_int_mask
| PWM 0. More...
QM_RW uint32_t | usb_0_int_mask
| USB 0. More...
QM_RW uint32_t | dma_0_int_2_mask
| DMA 0 Ch 2. More...
QM_RW uint32_t | dma_0_int_3_mask
| DMA 0 Ch 3. More...
QM_RW uint32_t | dma_0_int_4_mask
| DMA 0 Ch 4. More...
QM_RW uint32_t | dma_0_int_5_mask
| DMA 0 Ch 5. More...
QM_RW uint32_t | dma_0_int_6_mask
| DMA 0 Ch 6. More...
QM_RW uint32_t | dma_0_int_7_mask
| DMA 0 Ch 7. More...
QM_RW uint32_t | mailbox_0_int_mask
| Mailbox 0 Combined 8 Channel Host and Sensor Masks. More...
QM_RW uint32_t | comparator_0_ss_halt_int_mask
| Comparator Sensor Halt Mask. More...
QM_RW uint32_t | comparator_0_ss_int_mask
| Comparator Sensor Mask. More...
QM_RW uint32_t | flash_mpr_1_int_mask
| Flash MPR 1. More...
QM_RW uint32_t | aon_gpio_0_int_mask
| AON GPIO 0. More...

## Detailed Description

Interrupt register map.

Definition at line 77 of file qm_interrupt_router_regs.h.

## Field Documentation

QM_RW uint32_t qm_interrupt_router_reg_t::adc_0_cal_int_mask

ADC 0 CAL, Mask 34.

ADC 0 CAL.

Definition at line 106 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::adc_0_pwr_int_mask

ADC 0 PWR, Mask 33.

ADC 0 PWR.

Definition at line 105 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::aon_gpio_0_int_mask

AON GPIO 0.

Definition at line 287 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::aonpt_0_int_mask

AONPT 0, Mask 32.

AONPT 0.

Definition at line 104 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::comparator_0_host_halt_int_mask

Comparator 0 Host halt, Mask 24.

Comparator Host Halt Mask.

Definition at line 95 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::comparator_0_host_int_mask

Comparator 0 Host, Mask 26.

Comparator Host Mask.

Definition at line 98 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::comparator_0_ss_halt_int_mask

Comparator Sensor Halt Mask.

Definition at line 272 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::comparator_0_ss_int_mask

Comparator Sensor Mask.

Definition at line 276 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_error_int_mask

DMA 0 Error, Mask 28.

DMA 0 Error.

Definition at line 100 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_0_mask

DMA 0 int 0, Mask 14.

DMA 0 Ch 0.

Definition at line 91 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_1_mask

DMA 0 int 1, Mask 15.

DMA 0 Ch 1.

Definition at line 92 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_2_mask

DMA 0 Ch 2.

Definition at line 263 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_3_mask

DMA 0 Ch 3.

Definition at line 264 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_4_mask

DMA 0 Ch 4.

Definition at line 265 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_5_mask

DMA 0 Ch 5.

Definition at line 266 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_6_mask

DMA 0 Ch 6.

Definition at line 267 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::dma_0_int_7_mask

DMA 0 Ch 7.

Definition at line 268 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::flash_mpr_0_int_mask

Flash MPR 0, Mask 30.

Flash MPR 0.

Definition at line 102 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::flash_mpr_1_int_mask

Flash MPR 1.

Definition at line 283 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::gpio_0_int_mask

GPIO 0, Mask 9.

GPIO 0.

Definition at line 86 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::host_bus_error_int_mask

Host bus error, Mask 27.

Host bus error.

Definition at line 99 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::i2c_master_0_int_mask

I2C Master 0, Mask 0.

I2C Master 0.

Definition at line 78 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::i2c_master_1_int_mask

I2C Master 1.

Definition at line 248 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::i2s_0_int_mask

I2S 0.

Definition at line 255 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::lock_int_mask_reg

Interrupt Mask Lock Register.

Definition at line 108 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::mailbox_0_int_mask

Mailbox 0 Combined 8 Channel Host and Sensor Masks.

Definition at line 270 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::pwm_0_int_mask

PWM 0.

Definition at line 257 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::rtc_0_int_mask

RTC 0, Mask 12.

RTC 0.

Definition at line 89 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::spi_master_0_int_mask

SPI Master 0, Mask 3.

SPI Master 0.

Definition at line 80 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::spi_master_1_int_mask

SPI Master 1.

Definition at line 251 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::spi_slave_0_int_mask

SPI Slave 0, Mask 5.

SPI Slave 0.

Definition at line 82 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::sram_mpr_0_int_mask

SRAM MPR 0, Mask 29.

SRAM MPR 0.

Definition at line 101 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::ss_adc_0_error_int_mask

Sensor ADC 0 Error.

Definition at line 239 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::ss_adc_0_int_mask

Sensor ADC 0.

Definition at line 240 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::ss_gpio_0_int_mask

Sensor GPIO 0.

Definition at line 241 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::ss_gpio_1_int_mask

Sensor GPIO 1.

Definition at line 242 of file qm_interrupt_router_regs.h.

int_ss_i2c_reg_t qm_interrupt_router_reg_t::ss_i2c_0_int

Sensor I2C 0 Masks.

Definition at line 243 of file qm_interrupt_router_regs.h.

int_ss_i2c_reg_t qm_interrupt_router_reg_t::ss_i2c_1_int

Sensor I2C 1 Masks.

Definition at line 244 of file qm_interrupt_router_regs.h.

int_ss_spi_reg_t qm_interrupt_router_reg_t::ss_spi_0_int

Sensor SPI 0 Masks.

Definition at line 245 of file qm_interrupt_router_regs.h.

int_ss_spi_reg_t qm_interrupt_router_reg_t::ss_spi_1_int

Sensor SPI 1 Masks.

Definition at line 246 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::timer_0_int_mask

Timer 0, Mask 10.

Definition at line 87 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::uart_0_int_mask

UART 0, Mask 6.

UART 0.

Definition at line 83 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::uart_1_int_mask

UART 1, Mask 7.

UART 1.

Definition at line 84 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::usb_0_int_mask

USB 0.

Definition at line 258 of file qm_interrupt_router_regs.h.

QM_RW uint32_t qm_interrupt_router_reg_t::wdt_0_int_mask

WDT 0, Mask 13.

WDT 0.

Definition at line 90 of file qm_interrupt_router_regs.h.