Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_soc_regs.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __REGISTERS_H__
6 #define __REGISTERS_H__
7
8 #include "qm_common.h"
9 #include "qm_interrupt_router_regs.h"
10 #include "qm_soc_interrupts.h"
11 #include "flash_layout.h"
12
13 /**
14 * Quark D2000 SoC Registers.
15 *
16 * @defgroup groupQUARKD2000SEREG SoC Registers (D2000)
17 * @{
18 */
19
20 #define QUARK_D2000 (1)
21 #define HAS_MVIC (1)
22 #define HAS_SOC_CONTEXT_RETENTION (1)
23
24 /**
25 * @name System Core
26 * @{
27 */
28
29 /** System Core register map. */
30 typedef struct {
31 QM_RW uint32_t osc0_cfg0; /**< Hybrid Oscillator Configuration 0. */
32 QM_RW uint32_t osc0_stat1; /**< Hybrid Oscillator status 1. */
33 QM_RW uint32_t osc0_cfg1; /**< Hybrid Oscillator configuration 1. */
34 QM_RW uint32_t osc1_stat0; /**< RTC Oscillator status 0. */
35 QM_RW uint32_t osc1_cfg0; /**< RTC Oscillator Configuration 0. */
36 QM_RW uint32_t reserved;
37 QM_RW uint32_t
38 ccu_periph_clk_gate_ctl; /**< Peripheral Clock Gate Control. */
39 QM_RW uint32_t
40 ccu_periph_clk_div_ctl0; /**< Peripheral Clock Divider Control 0. */
41 QM_RW uint32_t
42 ccu_gpio_db_clk_ctl; /**< Peripheral Clock Divider Control 1. */
43 QM_RW uint32_t
44 ccu_ext_clock_ctl; /**< External Clock Control Register. */
45 QM_RW uint32_t reserved1;
46 QM_RW uint32_t ccu_lp_clk_ctl; /**< System Low Power Clock Control. */
47 QM_RW uint32_t wake_mask; /**< Wake Mask register. */
48 QM_RW uint32_t ccu_mlayer_ahb_ctl; /**< AHB Control Register. */
49 QM_RW uint32_t ccu_sys_clk_ctl; /**< System Clock Control Register. */
50 QM_RW uint32_t osc_lock_0; /**< Clocks Lock Register. */
51 QM_RW uint32_t soc_ctrl; /**< SoC Control Register. */
52 QM_RW uint32_t soc_ctrl_lock; /**< SoC Control Register Lock. */
53 } qm_scss_ccu_reg_t;
54
55 #if (UNIT_TEST)
56 qm_scss_ccu_reg_t test_scss_ccu;
57 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)(&test_scss_ccu))
58
59 #else
60 #define QM_SCSS_CCU_BASE (0xB0800000)
61 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)QM_SCSS_CCU_BASE)
62 #endif
63
64 /* The GPS0 register usage. */
65 #define QM_GPS0_BIT_FM (0) /**< Start Firmware Manager. */
66
67 /* Hybrid oscillator output select select (0=Silicon, 1=Crystal) */
68 #define QM_OSC0_MODE_SEL BIT(3)
69 #define QM_OSC0_PD BIT(2)
70 #define QM_OSC1_PD BIT(1)
71
72 /* Enable Crystal oscillator. */
73 #define QM_OSC0_EN_CRYSTAL BIT(0)
74
75 /* Crystal oscillator parameters. */
76 #define OSC0_CFG1_OSC0_FADJ_XTAL_MASK (0x000F0000)
77 #define OSC0_CFG1_OSC0_FADJ_XTAL_OFFS (16)
78 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_MASK (0x00600000)
79 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_OFFS (21)
80
81 /* Silicon Oscillator parameters. */
82 #define OSC0_CFG1_FTRIMOTP_MASK (0x3FF00000)
83 #define OSC0_CFG1_FTRIMOTP_OFFS (20)
84 #define OSC0_CFG1_SI_FREQ_SEL_MASK (0x00000300)
85 #define OSC0_CFG1_SI_FREQ_SEL_OFFS (8)
86
87 #define QM_OSC0_LOCK_SI BIT(0)
88 #define QM_OSC0_LOCK_XTAL BIT(1)
89 #define QM_OSC0_EN_SI_OSC BIT(1)
90
91 #define QM_SI_OSC_1V2_MODE BIT(0)
92
93 /* Peripheral clock divider control. */
94 #define QM_CCU_PERIPH_PCLK_DIV_OFFSET (1)
95 #define QM_CCU_PERIPH_PCLK_DIV_EN BIT(0)
96
97 /* System clock control. */
98 #define QM_CCU_SYS_CLK_SEL BIT(0)
99 #define QM_CCU_PERIPH_CLK_EN BIT(1)
100 #define QM_CCU_ADC_CLK_DIV_OFFSET (16)
101 #define QM_CCU_ADC_CLK_DIV_DEF_MASK (0xFC00FFFF)
102 #define QM_CCU_PERIPH_PCLK_DIV_DEF_MASK (0xFFFFFFF8)
103 #define QM_CCU_RTC_CLK_EN BIT(1)
104 #define QM_CCU_RTC_CLK_DIV_EN BIT(2)
105 #define QM_CCU_SYS_CLK_DIV_EN BIT(7)
106 #define QM_CCU_SYS_CLK_DIV_MASK (0x00000700)
107
108 #define QM_OSC0_SI_FREQ_SEL_DEF_MASK (0xFFFFFCFF)
109 #define QM_CCU_SYS_CLK_DIV_DEF_MASK (0xFFFFF47F)
110 #define QM_OSC0_SI_FREQ_SEL_4MHZ (3 >> 8)
111
112 #define QM_CCU_EXTERN_DIV_OFFSET (3)
113 #define QM_CCU_EXT_CLK_DIV_EN BIT(2)
114 #define QM_CCU_GPIO_DB_DIV_OFFSET (2)
115 #define QM_CCU_GPIO_DB_CLK_DIV_EN BIT(1)
116 #define QM_CCU_GPIO_DB_CLK_EN BIT(0)
117 #define QM_CCU_RTC_CLK_DIV_OFFSET (3)
118 #define QM_CCU_SYS_CLK_DIV_OFFSET (8)
119 #define QM_CCU_GPIO_DB_CLK_DIV_DEF_MASK (0xFFFFFFE1)
120 #define QM_CCU_EXT_CLK_DIV_DEF_MASK (0xFFFFFFE3)
121 #define QM_CCU_RTC_CLK_DIV_DEF_MASK (0xFFFFFF83)
122 #define QM_CCU_DMA_CLK_EN BIT(6)
123 #define QM_CCU_WAKE_MASK_RTC_BIT BIT(2)
124 #define QM_CCU_WAKE_MASK_GPIO_BIT BIT(15)
125 #define QM_CCU_WAKE_MASK_COMPARATOR_BIT BIT(14)
126 #define QM_CCU_WAKE_MASK_GPIO_BIT BIT(15)
127
128 #define QM_HYB_OSC_PD_LATCH_EN BIT(14)
129 #define QM_RTC_OSC_PD_LATCH_EN BIT(15)
130 #define QM_CCU_EXIT_TO_HYBOSC BIT(4)
131 #define QM_CCU_MEM_HALT_EN BIT(3)
132 #define QM_CCU_CPU_HALT_EN BIT(2)
133
134 #define QM_WAKE_PROBE_MODE_MASK BIT(13)
135
136 /** @} */
137
138 /**
139 * @name General Purpose
140 * @{
141 */
142
143 /** General Purpose register map. */
144 typedef struct {
145 QM_RW uint32_t gps0; /**< General Purpose Sticky Register 0. */
146 QM_RW uint32_t gps1; /**< General Purpose Sticky Register 1. */
147 QM_RW uint32_t gps2; /**< General Purpose Sticky Register 2. */
148 QM_RW uint32_t gps3; /**< General Purpose Sticky Register 3. */
149 QM_RW uint32_t reserved;
150 QM_RW uint32_t gp0; /**< General Purpose Scratchpad Register 0. */
151 QM_RW uint32_t gp1; /**< General Purpose Scratchpad Register 1. */
152 QM_RW uint32_t gp2; /**< General Purpose Scratchpad Register 2. */
153 QM_RW uint32_t gp3; /**< General Purpose Scratchpad Register 3. */
154 QM_RW uint32_t reserved1[3];
155 QM_RW uint32_t wo_sp; /**< Write-One-to-Set Scratchpad Register. */
156 QM_RW uint32_t
157 wo_st; /**< Write-One-to-Set Sticky Scratchpad Register. */
158 } qm_scss_gp_reg_t;
159
160 #if (UNIT_TEST)
161 qm_scss_gp_reg_t test_scss_gp;
162 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)(&test_scss_gp))
163
164 #else
165 #define QM_SCSS_GP_BASE (0xB0800100)
166 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)QM_SCSS_GP_BASE)
167 #endif
168
169 #define QM_GPS0_POWER_STATES_MASK (BIT(6) | BIT(7) | BIT(8) | BIT(9))
170 #define QM_GPS0_POWER_STATE_SLEEP BIT(6)
171 #define QM_GPS0_POWER_STATE_DEEP_SLEEP BIT(7)
172
173 /** @} */
174
175 /**
176 * @name Comparator
177 * @{
178 */
179
180 /** Comparator register map. */
181 typedef struct {
182 QM_RW uint32_t cmp_en; /**< Comparator enable. */
183 QM_RW uint32_t cmp_ref_sel; /**< Comparator reference select. */
184 QM_RW uint32_t
185 cmp_ref_pol; /**< Comparator reference polarity select register. */
186 QM_RW uint32_t cmp_pwr; /**< Comparator power enable register. */
187 QM_RW uint32_t reserved[6];
188 QM_RW uint32_t cmp_stat_clr; /**< Comparator clear register. */
189 } qm_scss_cmp_reg_t;
190
191 #if (UNIT_TEST)
192 qm_scss_cmp_reg_t test_scss_cmp;
193 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)(&test_scss_cmp))
194
195 #else
196 #define QM_SCSS_CMP_BASE (0xB0800300)
197 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)QM_SCSS_CMP_BASE)
198 #endif
199
200 #define QM_AC_HP_COMPARATORS_MASK (0x7FFC0)
201
202 /** @} */
203
204 /**
205 * @name Power Management
206 * @{
207 */
208
209 /** Power Management register map. */
210 typedef struct {
211 QM_RW uint32_t aon_vr; /**< AON Voltage Regulator. */
212 QM_RW uint32_t reserved[5];
213 QM_RW uint32_t pm_wait; /**< Power Management Wait. */
214 QM_RW uint32_t reserved1;
215 QM_RW uint32_t p_sts; /**< Processor Status. */
216 QM_RW uint32_t reserved2[3];
217 QM_RW uint32_t rstc; /**< Reset Control. */
218 QM_RW uint32_t rsts; /**< Reset Status. */
219 QM_RW uint32_t reserved3[7];
220 QM_RW uint32_t pm_lock; /**< Power Management Lock. */
221 } qm_scss_pmu_reg_t;
222
223 #if (UNIT_TEST)
224 qm_scss_pmu_reg_t test_scss_pmu;
225 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)(&test_scss_pmu))
226
227 #else
228 #define QM_SCSS_PMU_BASE (0xB0800540)
229 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)QM_SCSS_PMU_BASE)
230 #endif
231
232 #define QM_P_STS_HALT_INTERRUPT_REDIRECTION BIT(26)
233
234 /*
235 * Rename ROK_BUF_VREG register bit to ROK_BUF_VREG_STATUS to avoid confusion
236 * and preprocessor issues with ROK_BUF_VREG_MASK register bit.
237 */
238 #define QM_AON_VR_ROK_BUF_VREG_STATUS BIT(15)
239 #define QM_AON_VR_ROK_BUF_VREG_MASK BIT(9)
240 #define QM_AON_VR_VREG_SEL BIT(8)
241 #define QM_AON_VR_PASS_CODE (0x9DC4 << 16)
242 #define QM_AON_VR_VSEL_MASK (0xFFE0)
243 #define QM_AON_VR_VSEL_1V35 (0xB)
244 #define QM_AON_VR_VSEL_1V8 (0x10)
245 #define QM_AON_VR_VSTRB BIT(5)
246
247 /** @} */
248
249 /**
250 * @name Always-on Counters.
251 * @{
252 */
253
254 /** Number of Always-on counter controllers. */
255 typedef enum { QM_AONC_0 = 0, QM_AONC_NUM } qm_aonc_t;
256
257 /** Always-on Counter Controller register map. */
258 typedef struct {
259 QM_RW uint32_t aonc_cnt; /**< Always-on counter register. */
260 QM_RW uint32_t aonc_cfg; /**< Always-on counter enable. */
261 QM_RW uint32_t aonpt_cnt; /**< Always-on periodic timer. */
262 QM_RW uint32_t
263 aonpt_stat; /**< Always-on periodic timer status register. */
264 QM_RW uint32_t aonpt_ctrl; /**< Always-on periodic timer control. */
265 QM_RW uint32_t
266 aonpt_cfg; /**< Always-on periodic timer configuration register. */
267 } qm_aonc_reg_t;
268
269 #define qm_aonc_context_t uint8_t
270
271 #define HAS_AONPT_BUSY_BIT (0)
272
273 #define QM_AONC_ENABLE (BIT(0))
274 #define QM_AONC_DISABLE (~QM_AONC_ENABLE)
275
276 #define QM_AONPT_INTERRUPT (BIT(0))
277
278 #define QM_AONPT_CLR (BIT(0))
279 #define QM_AONPT_RST (BIT(1))
280
281 #if (UNIT_TEST)
282 qm_aonc_reg_t test_aonc_instance[QM_AONC_NUM];
283 qm_aonc_reg_t *test_aonc[QM_AONC_NUM];
284
285 #define QM_AONC test_aonc
286
287 #else
288 extern qm_aonc_reg_t *qm_aonc[QM_AONC_NUM];
289 #define QM_AONC_0_BASE (0xB0800700)
290 #define QM_AONC qm_aonc
291 #endif
292
293 /** @} */
294
295 /**
296 * @name Peripheral Registers
297 * @{
298 */
299
300 /** Peripheral Registers register map. */
301 typedef struct {
302 QM_RW uint32_t periph_cfg0; /**< Peripheral Configuration. */
303 QM_RW uint32_t reserved[2];
304 QM_RW uint32_t cfg_lock; /**< Configuration Lock. */
305 } qm_scss_peripheral_reg_t;
306
307 #if (UNIT_TEST)
308 qm_scss_peripheral_reg_t test_scss_peripheral;
309 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)(&test_scss_peripheral))
310
311 #else
312 #define QM_SCSS_PERIPHERAL_BASE (0xB0800804)
313 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)QM_SCSS_PERIPHERAL_BASE)
314 #endif
315
316 /** @} */
317
318 /**
319 * @name Pin MUX
320 * @{
321 */
322
323 /** Pin MUX register map. */
324 typedef struct {
325 QM_RW uint32_t pmux_pullup[1]; /**< Pin Mux Pullup. */
326 QM_RW uint32_t reserved[3];
327 QM_RW uint32_t pmux_slew[1]; /**< Pin Mux Slew Rate. */
328 QM_RW uint32_t reserved1[3];
329 QM_RW uint32_t pmux_in_en[1]; /**< Pin Mux Input Enable. */
330 QM_RW uint32_t reserved2[3];
331 QM_RW uint32_t pmux_sel[2]; /**< Pin Mux Select. */
332 QM_RW uint32_t reserved3[5];
333 QM_RW uint32_t pmux_pullup_lock; /**< Pin Mux Pullup Lock. */
334 QM_RW uint32_t pmux_slew_lock; /**< Pin Mux Slew Rate Lock. */
335 QM_RW uint32_t pmux_sel_0_lock; /**< Pin Mux Select Lock 0. */
336 QM_RW uint32_t reserved4[2];
337 QM_RW uint32_t pmux_in_en_lock; /**< Pin Mux Slew Rate Lock. */
338 } qm_scss_pmux_reg_t;
339
340 #if (UNIT_TEST)
341 qm_scss_pmux_reg_t test_scss_pmux;
342 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)(&test_scss_pmux))
343
344 #else
345 #define QM_SCSS_PMUX_BASE (0xB0800900)
346 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)QM_SCSS_PMUX_BASE)
347 #endif
348
349 /** @} */
350
351 /**
352 * @name ID
353 * @{
354 */
355
356 /** Information register map. */
357 typedef struct {
358 QM_RW uint32_t id; /**< Identification Register. */
359 QM_RW uint32_t rev; /**< Revision Register. */
360 QM_RW uint32_t fs; /**< Flash Size Register. */
361 QM_RW uint32_t rs; /**< RAM Size Register. */
362 QM_RW uint32_t cotps; /**< Code OTP Size Register. */
363 QM_RW uint32_t dotps; /**< Data OTP Size Register. */
364 } qm_scss_info_reg_t;
365
366 #if (UNIT_TEST)
367 qm_scss_info_reg_t test_scss_info;
368 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)(&test_scss_info))
369
370 #else
371 #define QM_SCSS_INFO_BASE (0xB0801000)
372 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)QM_SCSS_INFO_BASE)
373 #endif
374
375 /** @} */
376
377 /**
378 * @name PWM / Timer
379 * @{
380 */
381
382 /** Number of PWM / Timer controllers. */
383 typedef enum { QM_PWM_0 = 0, QM_PWM_NUM } qm_pwm_t;
384
385 /** PWM ID type. */
386 typedef enum { QM_PWM_ID_0 = 0, QM_PWM_ID_1, QM_PWM_ID_NUM } qm_pwm_id_t;
387
388 /** PWM / Timer channel register map. */
389 typedef struct {
390 QM_RW uint32_t loadcount; /**< Load Coun.t */
391 QM_RW uint32_t currentvalue; /**< Current Value. */
392 QM_RW uint32_t controlreg; /**< Control. */
393 QM_RW uint32_t eoi; /**< End Of Interrupt. */
394 QM_RW uint32_t intstatus; /**< Interrupt Status. */
395 } qm_pwm_channel_t;
396
397 /** PWM / Timer register map. */
398 typedef struct {
399 qm_pwm_channel_t timer[QM_PWM_ID_NUM]; /**< 2 Timers. */
400 QM_RW uint32_t reserved[30];
401 QM_RW uint32_t timersintstatus; /**< Timers Interrupt Status */
402 QM_RW uint32_t timerseoi; /**< Timers End Of Interrupt */
403 QM_RW uint32_t timersrawintstatus; /**< Timers Raw Interrupt Status */
404 QM_RW uint32_t timerscompversion; /**< Timers Component Version */
405 QM_RW uint32_t
406 timer_loadcount2[QM_PWM_ID_NUM]; /**< Timer Load Count 2 */
407 } qm_pwm_reg_t;
408
409 #define qm_pwm_context_t uint8_t
410
411 #if (UNIT_TEST)
412 qm_pwm_reg_t test_pwm_instance[QM_PWM_NUM];
413 qm_pwm_reg_t *test_pwm[QM_PWM_NUM];
414 #define QM_PWM test_pwm
415
416 #else
417 extern qm_pwm_reg_t *qm_pwm[QM_PWM_NUM];
418 /* PWM register base address. */
419 #define QM_PWM_BASE (0xB0000800)
420 /* PWM register block. */
421 #define QM_PWM qm_pwm
422 #endif
423
424 #define PWM_START (1)
425
426 #define QM_PWM_CONF_MODE_MASK (0xA)
427 #define QM_PWM_CONF_INT_EN_MASK (0x4)
428
429 #define QM_PWM_INTERRUPT_MASK_OFFSET (0x2)
430
431 #define NUM_PWM_CONTROLLER_INTERRUPTS (1)
432
433 /**
434 * Timer N Control (TimerNControlReg)
435 *
436 * 31:4 RO reserved
437 * 3 RW Timer PWM
438 * 1 - PWM Mode
439 * 0 - Timer Mode
440 * 2 RW Timer Interrupt Mask, set to 1b to mask interrupt.
441 * 1 RW Timer Mode
442 * 1 - user-defined count mode
443 * 0 - free-running mode
444 * 0 RW Timer Enable
445 * 0 - Disable PWM/Timer
446 * 1 - Enable PWM/Timer
447 */
448
449 #define QM_PWM_TIMERNCONTROLREG_TIMER_ENABLE (BIT(0))
450 #define QM_PWM_TIMERNCONTROLREG_TIMER_MODE (BIT(1))
451 #define QM_PWM_TIMERNCONTROLREG_TIMER_INTERRUPT_MASK (BIT(2))
452 #define QM_PWM_TIMERNCONTROLREG_TIMER_PWM (BIT(3))
453
454 #define QM_PWM_MODE_TIMER_FREE_RUNNING_VALUE (0)
455 #define QM_PWM_MODE_TIMER_COUNT_VALUE (QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
456 #define QM_PWM_MODE_PWM_VALUE \
457 (QM_PWM_TIMERNCONTROLREG_TIMER_PWM | QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
458
459 /** @} */
460
461 /**
462 * @name WDT
463 * @{
464 */
465
466 /** Number of WDT controllers. */
467 typedef enum { QM_WDT_0 = 0, QM_WDT_NUM } qm_wdt_t;
468
469 /** Watchdog timer register map. */
470 typedef struct {
471 QM_RW uint32_t wdt_cr; /**< Control Register. */
472 QM_RW uint32_t wdt_torr; /**< Timeout Range Register. */
473 QM_RW uint32_t wdt_ccvr; /**< Current Counter Value Register. */
474 QM_RW uint32_t wdt_crr; /**< Current Restart Register. */
475 QM_RW uint32_t wdt_stat; /**< Interrupt Status Register. */
476 QM_RW uint32_t wdt_eoi; /**< Interrupt Clear Register. */
477 QM_RW uint32_t wdt_comp_param_5; /**< Component Parameters. */
478 QM_RW uint32_t wdt_comp_param_4; /**< Component Parameters. */
479 QM_RW uint32_t wdt_comp_param_3; /**< Component Parameters. */
480 QM_RW uint32_t wdt_comp_param_2; /**< Component Parameters. */
481 QM_RW uint32_t
482 wdt_comp_param_1; /**< Component Parameters Register 1. */
483 QM_RW uint32_t wdt_comp_version; /**< Component Version Register. */
484 QM_RW uint32_t wdt_comp_type; /**< Component Type Register. */
485 } qm_wdt_reg_t;
486
487 #define qm_wdt_context_t uint8_t
488
489 #if (UNIT_TEST)
490 qm_wdt_reg_t test_wdt_instance[QM_WDT_NUM];
491 qm_wdt_reg_t *test_wdt[QM_WDT_NUM];
492 #define QM_WDT test_wdt
493
494 #else
495 extern qm_wdt_reg_t *qm_wdt[QM_WDT_NUM];
496 /* WDT register base address. */
497 #define QM_WDT_0_BASE (0xB0000000)
498
499 /* WDT register block. */
500 #define QM_WDT qm_wdt
501 #endif
502
503 /* Watchdog enable. */
504 #define QM_WDT_CR_WDT_ENABLE (BIT(0))
505 /* Watchdog mode. */
506 #define QM_WDT_CR_RMOD (BIT(1))
507 /* Watchdog mode offset. */
508 #define QM_WDT_CR_RMOD_OFFSET (1)
509 /* Watchdog Timeout Mask. */
510 #define QM_WDT_TORR_TOP_MASK (0xF)
511 /* Watchdog reload special value. */
512 #define QM_WDT_RELOAD_VALUE (0x76)
513 /* Number of WDT controllers. */
514 #define NUM_WDT_CONTROLLERS (1)
515 /* Watchdog does not have pause enable. */
516 #define HAS_WDT_PAUSE (0)
517 /* Software SoC watch required. */
518 #define HAS_SW_SOCWATCH (1)
519 /* Peripheral WDT clock enable mask. */
520 #define QM_WDT_CLOCK_EN_MASK (BIT(10))
521 /* Required to enable WDT clock on start. */
522 #define HAS_WDT_CLOCK_ENABLE (1)
523
524 /**
525 * WDT timeout table (in clock cycles):
526 * Each table entry corresponds with the value loaded
527 * into the WDT at the time of a WDT reload for the
528 * corresponding timeout range register value.
529 *
530 * TORR | Timeout (Clock Cycles)
531 * 0. | 2^16 (65536)
532 * 1. | 2^17 (131072)
533 * 2. | 2^18 (262144)
534 * 3. | 2^19 (524288)
535 * 4. | 2^20 (1048576)
536 * 5. | 2^21 (2097152)
537 * 6. | 2^22 (4194304)
538 * 7. | 2^23 (8388608)
539 * 8. | 2^24 (16777216)
540 * 9. | 2^25 (33554432)
541 * 10. | 2^26 (67108864)
542 * 11. | 2^27 (134217728)
543 * 12. | 2^28 (268435456)
544 * 13. | 2^29 (536870912)
545 * 14. | 2^30 (1073741824)
546 * 15. | 2^31 (2147483648)
547 */
548
549 /** @} */
550
551 /**
552 * @name UART
553 * @{
554 */
555
556 /* Break character Bit. */
557 #define QM_UART_LCR_BREAK BIT(6)
558 /* Divisor Latch Access Bit. */
559 #define QM_UART_LCR_DLAB BIT(7)
560
561 /* Request to Send Bit. */
562 #define QM_UART_MCR_RTS BIT(1)
563 /* Loopback Enable Bit. */
564 #define QM_UART_MCR_LOOPBACK BIT(4)
565 /* Auto Flow Control Enable Bit. */
566 #define QM_UART_MCR_AFCE BIT(5)
567
568 /* FIFO Enable Bit. */
569 #define QM_UART_FCR_FIFOE BIT(0)
570 /* Reset Receive FIFO. */
571 #define QM_UART_FCR_RFIFOR BIT(1)
572 /* Reset Transmit FIFO. */
573 #define QM_UART_FCR_XFIFOR BIT(2)
574
575 /* Default FIFO RX & TX Thresholds, half full for both. */
576 #define QM_UART_FCR_DEFAULT_TX_RX_THRESHOLD (0xB0)
577 /* Change TX Threshold to empty, keep RX Threshold to default. */
578 #define QM_UART_FCR_TX_0_RX_1_2_THRESHOLD (0x80)
579
580 /* Transmit Holding Register Empty. */
581 #define QM_UART_IIR_THR_EMPTY (0x02)
582 /* Received Data Available. */
583 #define QM_UART_IIR_RECV_DATA_AVAIL (0x04)
584 /* Receiver Line Status. */
585 #define QM_UART_IIR_RECV_LINE_STATUS (0x06)
586 /* Character Timeout. */
587 #define QM_UART_IIR_CHAR_TIMEOUT (0x0C)
588 /* Interrupt ID Mask. */
589 #define QM_UART_IIR_IID_MASK (0x0F)
590
591 /* Data Ready Bit. */
592 #define QM_UART_LSR_DR BIT(0)
593 /* Overflow Error Bit. */
594 #define QM_UART_LSR_OE BIT(1)
595 /* Parity Error Bit. */
596 #define QM_UART_LSR_PE BIT(2)
597 /* Framing Error Bit. */
598 #define QM_UART_LSR_FE BIT(3)
599 /* Break Interrupt Bit. */
600 #define QM_UART_LSR_BI BIT(4)
601 /* Transmit Holding Register Empty Bit. */
602 #define QM_UART_LSR_THRE BIT(5)
603 /* Transmitter Empty Bit. */
604 #define QM_UART_LSR_TEMT BIT(6)
605 /* Receiver FIFO Error Bit. */
606 #define QM_UART_LSR_RFE BIT(7)
607
608 /* Enable Received Data Available Interrupt. */
609 #define QM_UART_IER_ERBFI BIT(0)
610 /* Enable Transmit Holding Register Empty Interrupt. */
611 #define QM_UART_IER_ETBEI BIT(1)
612 /* Enable Receiver Line Status Interrupt. */
613 #define QM_UART_IER_ELSI BIT(2)
614 /* Programmable THRE Interrupt Mode. */
615 #define QM_UART_IER_PTIME BIT(7)
616
617 /* Line Status Errors. */
618 #define QM_UART_LSR_ERROR_BITS \
619 (QM_UART_LSR_OE | QM_UART_LSR_PE | QM_UART_LSR_FE | QM_UART_LSR_BI)
620
621 /* FIFO Depth. */
622 #define QM_UART_FIFO_DEPTH (16)
623 /* FIFO Half Depth. */
624 #define QM_UART_FIFO_HALF_DEPTH (QM_UART_FIFO_DEPTH / 2)
625
626 /* Divisor Latch High Offset. */
627 #define QM_UART_CFG_BAUD_DLH_OFFS 16
628 /* Divisor Latch Low Offset. */
629 #define QM_UART_CFG_BAUD_DLL_OFFS 8
630 /* Divisor Latch Fraction Offset. */
631 #define QM_UART_CFG_BAUD_DLF_OFFS 0
632 /* Divisor Latch High Mask. */
633 #define QM_UART_CFG_BAUD_DLH_MASK (0xFF << QM_UART_CFG_BAUD_DLH_OFFS)
634 /* Divisor Latch Low Mask. */
635 #define QM_UART_CFG_BAUD_DLL_MASK (0xFF << QM_UART_CFG_BAUD_DLL_OFFS)
636 /* Divisor Latch Fraction Mask. */
637 #define QM_UART_CFG_BAUD_DLF_MASK (0xFF << QM_UART_CFG_BAUD_DLF_OFFS)
638
639 /* Divisor Latch Packing Helper. */
640 #define QM_UART_CFG_BAUD_DL_PACK(dlh, dll, dlf) \
641 (dlh << QM_UART_CFG_BAUD_DLH_OFFS | dll << QM_UART_CFG_BAUD_DLL_OFFS | \
642 dlf << QM_UART_CFG_BAUD_DLF_OFFS)
643
644 /* Divisor Latch High Unpacking Helper. */
645 #define QM_UART_CFG_BAUD_DLH_UNPACK(packed) \
646 ((packed & QM_UART_CFG_BAUD_DLH_MASK) >> QM_UART_CFG_BAUD_DLH_OFFS)
647 /* Divisor Latch Low Unpacking Helper. */
648 #define QM_UART_CFG_BAUD_DLL_UNPACK(packed) \
649 ((packed & QM_UART_CFG_BAUD_DLL_MASK) >> QM_UART_CFG_BAUD_DLL_OFFS)
650 /* Divisor Latch Fraction Unpacking Helper. */
651 #define QM_UART_CFG_BAUD_DLF_UNPACK(packed) \
652 ((packed & QM_UART_CFG_BAUD_DLF_MASK) >> QM_UART_CFG_BAUD_DLF_OFFS)
653
654 /** Number of UART controllers. */
655 typedef enum { QM_UART_0 = 0, QM_UART_1, QM_UART_NUM } qm_uart_t;
656
657 /** UART register map. */
658 typedef struct {
659 QM_RW uint32_t
660 rbr_thr_dll; /**< Rx Buffer/ Tx Holding/ Div Latch Low. */
661 QM_RW uint32_t ier_dlh; /**< Interrupt Enable / Divisor Latch High. */
662 QM_RW uint32_t iir_fcr; /**< Interrupt Identification / FIFO Control. */
663 QM_RW uint32_t lcr; /**< Line Control. */
664 QM_RW uint32_t mcr; /**< MODEM Control. */
665 QM_RW uint32_t lsr; /**< Line Status. */
666 QM_RW uint32_t msr; /**< MODEM Status. */
667 QM_RW uint32_t scr; /**< Scratchpad. */
668 QM_RW uint32_t reserved[23];
669 QM_RW uint32_t usr; /**< UART Status. */
670 QM_RW uint32_t reserved1[9];
671 QM_RW uint32_t htx; /**< Halt Transmission. */
672 QM_RW uint32_t dmasa; /**< DMA Software Acknowledge. */
673 QM_RW uint32_t tcr; /**< Transceiver Control Register. */
674 QM_RW uint32_t de_en; /**< Driver Output Enable Register. */
675 QM_RW uint32_t re_en; /**< Receiver Output Enable Register. */
676 QM_RW uint32_t det; /**< Driver Output Enable Timing Register. */
677 QM_RW uint32_t tat; /**< TurnAround Timing Register. */
678 QM_RW uint32_t dlf; /**< Divisor Latch Fraction. */
679 QM_RW uint32_t rar; /**< Receive Address Register. */
680 QM_RW uint32_t tar; /**< Transmit Address Register. */
681 QM_RW uint32_t lcr_ext; /**< Line Extended Control Register. */
682 QM_RW uint32_t padding[204]; /* 0x400 - 0xD0 */
683 } qm_uart_reg_t;
684
685 #define qm_uart_context_t uint8_t
686
687 #if (UNIT_TEST)
688 qm_uart_reg_t test_uart_instance;
689 qm_uart_reg_t *test_uart[QM_UART_NUM];
690 #define QM_UART test_uart
691
692 #else
693 /* UART register base address. */
694 #define QM_UART_0_BASE (0xB0002000)
695 #define QM_UART_1_BASE (0xB0002400)
696 /* UART register block. */
697 extern qm_uart_reg_t *qm_uart[QM_UART_NUM];
698 #define QM_UART qm_uart
699 #endif
700
701 /** @} */
702
703 /**
704 * @name SPI
705 * @{
706 */
707
708 /** Number of SPI controllers. */
709 typedef enum { QM_SPI_MST_0 = 0, QM_SPI_SLV_0, QM_SPI_NUM } qm_spi_t;
710
711 /** SPI register map. */
712 typedef struct {
713 QM_RW uint32_t ctrlr0; /**< Control Register 0. */
714 QM_RW uint32_t ctrlr1; /**< Control Register 1. */
715 QM_RW uint32_t ssienr; /**< SSI Enable Register. */
716 QM_RW uint32_t mwcr; /**< Microwire Control Register. */
717 QM_RW uint32_t ser; /**< Slave Enable Register. */
718 QM_RW uint32_t baudr; /**< Baud Rate Select. */
719 QM_RW uint32_t txftlr; /**< Transmit FIFO Threshold Level. */
720 QM_RW uint32_t rxftlr; /**< Receive FIFO Threshold Level. */
721 QM_RW uint32_t txflr; /**< Transmit FIFO Level Register. */
722 QM_RW uint32_t rxflr; /**< Receive FIFO Level Register. */
723 QM_RW uint32_t sr; /**< Status Register. */
724 QM_RW uint32_t imr; /**< Interrupt Mask Register. */
725 QM_RW uint32_t isr; /**< Interrupt Status Register. */
726 QM_RW uint32_t risr; /**< Raw Interrupt Status Register. */
727 QM_RW uint32_t
728 txoicr; /**< Tx FIFO Overflow Interrupt Clear Register. */
729 QM_RW uint32_t
730 rxoicr; /**< Rx FIFO Overflow Interrupt Clear Register. */
731 QM_RW uint32_t
732 rxuicr; /**< Rx FIFO Underflow Interrupt Clear Register. */
733 QM_RW uint32_t msticr; /**< Multi-Master Interrupt Clear Register. */
734 QM_RW uint32_t icr; /**< Interrupt Clear Register. */
735 QM_RW uint32_t dmacr; /**< DMA Control Register. */
736 QM_RW uint32_t dmatdlr; /**< DMA Transmit Data Level. */
737 QM_RW uint32_t dmardlr; /**< DMA Receive Data Level. */
738 QM_RW uint32_t idr; /**< Identification Register. */
739 QM_RW uint32_t ssi_comp_version; /**< coreKit Version ID register. */
740 QM_RW uint32_t dr[36]; /**< Data Register. */
741 QM_RW uint32_t rx_sample_dly; /**< RX Sample Delay Register. */
742 QM_RW uint32_t padding[0x1C4]; /* (0x800 - 0xF0) / 4 */
743 } qm_spi_reg_t;
744
745 #define qm_spi_context_t uint8_t
746
747 #if (UNIT_TEST)
748 qm_spi_reg_t test_spi;
749 qm_spi_reg_t *test_spi_controllers[QM_SPI_NUM];
750
751 #define QM_SPI test_spi_controllers
752
753 #else
754 /* SPI Master register base address. */
755 #define QM_SPI_MST_0_BASE (0xB0001000)
756 extern qm_spi_reg_t *qm_spi_controllers[QM_SPI_NUM];
757 #define QM_SPI qm_spi_controllers
758
759 /* SPI Slave register base address. */
760 #define QM_SPI_SLV_BASE (0xB0001800)
761 #endif
762
763 /* SPI Ctrlr0 register */
764 #define QM_SPI_CTRLR0_DFS_32_MASK (0x001F0000)
765 #define QM_SPI_CTRLR0_TMOD_MASK (0x00000300)
766 #define QM_SPI_CTRLR0_SCPOL_SCPH_MASK (0x000000C0)
767 #define QM_SPI_CTRLR0_FRF_MASK (0x00000030)
768 #define QM_SPI_CTRLR0_DFS_32_OFFSET (16)
769 #define QM_SPI_CTRLR0_TMOD_OFFSET (8)
770 #define QM_SPI_CTRLR0_SCPOL_SCPH_OFFSET (6)
771 #define QM_SPI_CTRLR0_FRF_OFFSET (4)
772 #define QM_SPI_CTRLR0_SLV_OE BIT(10)
773
774 /* SPI SSI Enable register */
775 #define QM_SPI_SSIENR_SSIENR BIT(0)
776
777 /* SPI Status register */
778 #define QM_SPI_SR_BUSY BIT(0)
779 #define QM_SPI_SR_TFNF BIT(1)
780 #define QM_SPI_SR_TFE BIT(2)
781 #define QM_SPI_SR_RFNE BIT(3)
782 #define QM_SPI_SR_RFF BIT(4)
783
784 /* SPI Interrupt Mask register */
785 #define QM_SPI_IMR_MASK_ALL (0x00)
786 #define QM_SPI_IMR_TXEIM BIT(0)
787 #define QM_SPI_IMR_TXOIM BIT(1)
788 #define QM_SPI_IMR_RXUIM BIT(2)
789 #define QM_SPI_IMR_RXOIM BIT(3)
790 #define QM_SPI_IMR_RXFIM BIT(4)
791
792 /* SPI Interrupt Status register */
793 #define QM_SPI_ISR_TXEIS BIT(0)
794 #define QM_SPI_ISR_TXOIS BIT(1)
795 #define QM_SPI_ISR_RXUIS BIT(2)
796 #define QM_SPI_ISR_RXOIS BIT(3)
797 #define QM_SPI_ISR_RXFIS BIT(4)
798
799 /* SPI Raw Interrupt Status register */
800 #define QM_SPI_RISR_TXEIR BIT(0)
801 #define QM_SPI_RISR_TXOIR BIT(1)
802 #define QM_SPI_RISR_RXUIR BIT(2)
803 #define QM_SPI_RISR_RXOIR BIT(3)
804 #define QM_SPI_RISR_RXFIR BIT(4)
805
806 /* SPI DMA control */
807 #define QM_SPI_DMACR_RDMAE BIT(0)
808 #define QM_SPI_DMACR_TDMAE BIT(1)
809
810 /** @} */
811
812 /**
813 * @name RTC
814 * @{
815 */
816
817 /** Number of RTC controllers. */
818 typedef enum { QM_RTC_0 = 0, QM_RTC_NUM } qm_rtc_t;
819
820 /** RTC register map. */
821 typedef struct {
822 QM_RW uint32_t rtc_ccvr; /**< Current Counter Value Register. */
823 QM_RW uint32_t rtc_cmr; /**< Current Match Register. */
824 QM_RW uint32_t rtc_clr; /**< Counter Load Register. */
825 QM_RW uint32_t rtc_ccr; /**< Counter Control Register. */
826 QM_RW uint32_t rtc_stat; /**< Interrupt Status Register. */
827 QM_RW uint32_t rtc_rstat; /**< Interrupt Raw Status Register. */
828 QM_RW uint32_t rtc_eoi; /**< End of Interrupt Register. */
829 QM_RW uint32_t rtc_comp_version; /**< End of Interrupt Register. */
830 } qm_rtc_reg_t;
831
832 #define qm_rtc_context_t uint8_t
833
834 #define QM_RTC_CCR_INTERRUPT_ENABLE BIT(0)
835 #define QM_RTC_CCR_INTERRUPT_MASK BIT(1)
836 #define QM_RTC_CCR_ENABLE BIT(2)
837
838 #if (UNIT_TEST)
839 qm_rtc_reg_t test_rtc_instance[QM_RTC_NUM];
840 qm_rtc_reg_t *test_rtc[QM_RTC_NUM];
841
842 #define QM_RTC test_rtc
843
844 #else
845 extern qm_rtc_reg_t *qm_rtc[QM_RTC_NUM];
846 /* RTC register base address. */
847 #define QM_RTC_BASE (0xB0000400)
848
849 /* RTC register block. */
850 #define QM_RTC qm_rtc
851 #endif
852
853 /** @} */
854
855 /**
856 * @name I2C
857 * @{
858 */
859
860 /** Number of I2C controllers. */
861 typedef enum { QM_I2C_0 = 0, QM_I2C_NUM } qm_i2c_t;
862
863 /** I2C register map. */
864 typedef struct {
865 QM_RW uint32_t ic_con; /**< Control Register. */
866 QM_RW uint32_t ic_tar; /**< Master Target Address. */
867 QM_RW uint32_t ic_sar; /**< Slave Address. */
868 QM_RW uint32_t ic_hs_maddr; /**< High Speed Master ID. */
869 QM_RW uint32_t ic_data_cmd; /**< Data Buffer and Command. */
870 QM_RW uint32_t
871 ic_ss_scl_hcnt; /**< Standard Speed Clock SCL High Count. */
872 QM_RW uint32_t
873 ic_ss_scl_lcnt; /**< Standard Speed Clock SCL Low Count. */
874 QM_RW uint32_t ic_fs_scl_hcnt; /**< Fast Speed Clock SCL High Count. */
875 QM_RW uint32_t
876 ic_fs_scl_lcnt; /**< Fast Speed I2C Clock SCL Low Count. */
877 QM_RW uint32_t
878 ic_hs_scl_hcnt; /**< High Speed I2C Clock SCL High Count. */
879 QM_RW uint32_t
880 ic_hs_scl_lcnt; /**< High Speed I2C Clock SCL Low Count. */
881 QM_RW uint32_t ic_intr_stat; /**< Interrupt Status. */
882 QM_RW uint32_t ic_intr_mask; /**< Interrupt Mask. */
883 QM_RW uint32_t ic_raw_intr_stat; /**< Raw Interrupt Status. */
884 QM_RW uint32_t ic_rx_tl; /**< Receive FIFO Threshold Level. */
885 QM_RW uint32_t ic_tx_tl; /**< Transmit FIFO Threshold Level. */
886 QM_RW uint32_t
887 ic_clr_intr; /**< Clear Combined and Individual Interrupt. */
888 QM_RW uint32_t ic_clr_rx_under; /**< Clear RX_UNDER Interrupt. */
889 QM_RW uint32_t ic_clr_rx_over; /**< Clear RX_OVER Interrupt. */
890 QM_RW uint32_t ic_clr_tx_over; /**< Clear TX_OVER Interrupt. */
891 QM_RW uint32_t ic_clr_rd_req; /**< Clear RD_REQ Interrupt. */
892 QM_RW uint32_t ic_clr_tx_abrt; /**< Clear TX_ABRT Interrupt. */
893 QM_RW uint32_t ic_clr_rx_done; /**< Clear RX_DONE Interrupt. */
894 QM_RW uint32_t ic_clr_activity; /**< Clear ACTIVITY Interrupt. */
895 QM_RW uint32_t ic_clr_stop_det; /**< Clear STOP_DET Interrupt. */
896 QM_RW uint32_t ic_clr_start_det; /**< Clear START_DET Interrupt. */
897 QM_RW uint32_t ic_clr_gen_call; /**< Clear GEN_CALL Interrupt. */
898 QM_RW uint32_t ic_enable; /**< Enable. */
899 QM_RW uint32_t ic_status; /**< Status. */
900 QM_RW uint32_t ic_txflr; /**< Transmit FIFO Level. */
901 QM_RW uint32_t ic_rxflr; /**< Receive FIFO Level. */
902 QM_RW uint32_t ic_sda_hold; /**< SDA Hold. */
903 QM_RW uint32_t ic_tx_abrt_source; /**< Transmit Abort Source. */
904 QM_RW uint32_t reserved;
905 QM_RW uint32_t ic_dma_cr; /**< SDA Setup. */
906 QM_RW uint32_t ic_dma_tdlr; /**< DMA Transmit Data Level Register. */
907 QM_RW uint32_t ic_dma_rdlr; /**< I2C Receive Data Level Register. */
908 QM_RW uint32_t ic_sda_setup; /**< SDA Setup. */
909 QM_RW uint32_t ic_ack_general_call; /**< General Call Ack. */
910 QM_RW uint32_t ic_enable_status; /**< Enable Status. */
911 QM_RW uint32_t ic_fs_spklen; /**< SS and FS Spike Suppression Limit. */
912 QM_RW uint32_t ic_hs_spklen; /**< HS spike suppression limit. */
913 QM_RW uint32_t
914 ic_clr_restart_det; /**< clear the RESTART_DET interrupt. */
915 QM_RW uint32_t reserved1[18];
916 QM_RW uint32_t ic_comp_param_1; /**< Configuration Parameters. */
917 QM_RW uint32_t ic_comp_version; /**< Component Version. */
918 QM_RW uint32_t ic_comp_type; /**< Component Type. */
919 } qm_i2c_reg_t;
920
921 #define qm_i2c_context_t uint8_t
922
923 #if (UNIT_TEST)
924 qm_i2c_reg_t test_i2c_instance[QM_I2C_NUM];
925 qm_i2c_reg_t *test_i2c[QM_I2C_NUM];
926
927 #define QM_I2C test_i2c
928
929 #else
930 /* I2C Master register base address. */
931 #define QM_I2C_0_BASE (0xB0002800)
932
933 /** I2C register block. */
934 extern qm_i2c_reg_t *qm_i2c[QM_I2C_NUM];
935 #define QM_I2C qm_i2c
936 #endif
937
938 #define QM_I2C_IC_ENABLE_CONTROLLER_EN BIT(0)
939 #define QM_I2C_IC_ENABLE_CONTROLLER_ABORT BIT(1)
940 #define QM_I2C_IC_ENABLE_STATUS_IC_EN BIT(0)
941 #define QM_I2C_IC_CON_MASTER_MODE BIT(0)
942 #define QM_I2C_IC_CON_SLAVE_DISABLE BIT(6)
943 #define QM_I2C_IC_CON_10BITADDR_MASTER BIT(4)
944 #define QM_I2C_IC_CON_10BITADDR_MASTER_OFFSET (4)
945 #define QM_I2C_IC_CON_10BITADDR_SLAVE BIT(3)
946 #define QM_I2C_IC_CON_10BITADDR_SLAVE_OFFSET (3)
947 #define QM_I2C_IC_CON_SPEED_OFFSET (1)
948 #define QM_I2C_IC_CON_SPEED_SS BIT(1)
949 #define QM_I2C_IC_CON_SPEED_FS_FSP BIT(2)
950 #define QM_I2C_IC_CON_SPEED_MASK (0x06)
951 #define QM_I2C_IC_CON_RESTART_EN BIT(5)
952 #define QM_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
953 #define QM_I2C_IC_DATA_CMD_READ BIT(8)
954 #define QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL BIT(9)
955 #define QM_I2C_IC_DATA_CMD_LSB_MASK (0x000000FF)
956 #define QM_I2C_IC_RAW_INTR_STAT_RX_FULL BIT(2)
957 #define QM_I2C_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
958 #define QM_I2C_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
959 #define QM_I2C_IC_RAW_INTR_STAT_RESTART_DETECTED BIT(12)
960 #define QM_I2C_IC_TX_ABRT_SOURCE_NAK_MASK (0x1F)
961 #define QM_I2C_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
962 #define QM_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
963 #define QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK (0x1FFFF)
964 #define QM_I2C_IC_STATUS_BUSY_MASK (0x00000060)
965 #define QM_I2C_IC_STATUS_RFF BIT(4)
966 #define QM_I2C_IC_STATUS_RFNE BIT(3)
967 #define QM_I2C_IC_STATUS_TFE BIT(2)
968 #define QM_I2C_IC_STATUS_TNF BIT(1)
969 #define QM_I2C_IC_INTR_MASK_ALL (0x00)
970 #define QM_I2C_IC_INTR_MASK_RX_UNDER BIT(0)
971 #define QM_I2C_IC_INTR_MASK_RX_OVER BIT(1)
972 #define QM_I2C_IC_INTR_MASK_RX_FULL BIT(2)
973 #define QM_I2C_IC_INTR_MASK_TX_OVER BIT(3)
974 #define QM_I2C_IC_INTR_MASK_TX_EMPTY BIT(4)
975 #define QM_I2C_IC_INTR_MASK_RD_REQ BIT(5)
976 #define QM_I2C_IC_INTR_MASK_TX_ABORT BIT(6)
977 #define QM_I2C_IC_INTR_MASK_RX_DONE BIT(7)
978 #define QM_I2C_IC_INTR_MASK_ACTIVITY BIT(8)
979 #define QM_I2C_IC_INTR_MASK_STOP_DETECTED BIT(9)
980 #define QM_I2C_IC_INTR_MASK_START_DETECTED BIT(10)
981 #define QM_I2C_IC_INTR_MASK_GEN_CALL_DETECTED BIT(11)
982 #define QM_I2C_IC_INTR_MASK_RESTART_DETECTED BIT(12)
983 #define QM_I2C_IC_INTR_STAT_RX_UNDER BIT(0)
984 #define QM_I2C_IC_INTR_STAT_RX_OVER BIT(1)
985 #define QM_I2C_IC_INTR_STAT_RX_FULL BIT(2)
986 #define QM_I2C_IC_INTR_STAT_TX_OVER BIT(3)
987 #define QM_I2C_IC_INTR_STAT_TX_EMPTY BIT(4)
988 #define QM_I2C_IC_INTR_STAT_RD_REQ BIT(5)
989 #define QM_I2C_IC_INTR_STAT_TX_ABRT BIT(6)
990 #define QM_I2C_IC_INTR_STAT_RX_DONE BIT(7)
991 #define QM_I2C_IC_INTR_STAT_STOP_DETECTED BIT(9)
992 #define QM_I2C_IC_INTR_STAT_START_DETECTED BIT(10)
993 #define QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED BIT(11)
994 #define QM_I2C_IC_LCNT_MAX (65525)
995 #define QM_I2C_IC_LCNT_MIN (8)
996 #define QM_I2C_IC_HCNT_MAX (65525)
997 #define QM_I2C_IC_HCNT_MIN (6)
998 #define QM_I2C_IC_TAR_MASK (0x3FF)
999
1000 #define QM_I2C_FIFO_SIZE (16)
1001
1002 /* I2C DMA */
1003 #define QM_I2C_IC_DMA_CR_RX_ENABLE BIT(0)
1004 #define QM_I2C_IC_DMA_CR_TX_ENABLE BIT(1)
1005
1006 /** @} */
1007
1008 /**
1009 * @name GPIO
1010 * @{
1011 */
1012
1013 /** Number of GPIO controllers. */
1014 typedef enum { QM_GPIO_0 = 0, QM_GPIO_NUM } qm_gpio_t;
1015
1016 /** GPIO register map. */
1017 typedef struct {
1018 QM_RW uint32_t gpio_swporta_dr; /**< Port A Data. */
1019 QM_RW uint32_t gpio_swporta_ddr; /**< Port A Data Direction. */
1020 QM_RW uint32_t reserved[10];
1021 QM_RW uint32_t gpio_inten; /**< Interrupt Enable. */
1022 QM_RW uint32_t gpio_intmask; /**< Interrupt Mask. */
1023 QM_RW uint32_t gpio_inttype_level; /**< Interrupt Type. */
1024 QM_RW uint32_t gpio_int_polarity; /**< Interrupt Polarity. */
1025 QM_RW uint32_t gpio_intstatus; /**< Interrupt Status. */
1026 QM_RW uint32_t gpio_raw_intstatus; /**< Raw Interrupt Status. */
1027 QM_RW uint32_t gpio_debounce; /**< Debounce Enable. */
1028 QM_RW uint32_t gpio_porta_eoi; /**< Clear Interrupt. */
1029 QM_RW uint32_t gpio_ext_porta; /**< Port A External Port. */
1030 QM_RW uint32_t reserved1[3];
1031 QM_RW uint32_t gpio_ls_sync; /**< Synchronization Level. */
1032 QM_RW uint32_t gpio_id_code; /**< GPIO ID code. */
1033 QM_RW uint32_t gpio_int_bothedge; /**< Interrupt both edge type. */
1034 QM_RW uint32_t gpio_ver_id_code; /**< GPIO Component Version. */
1035 QM_RW uint32_t gpio_config_reg2; /**< GPIO Configuration Register 2. */
1036 QM_RW uint32_t gpio_config_reg1; /**< GPIO Configuration Register 1. */
1037 } qm_gpio_reg_t;
1038
1039 #define qm_gpio_context_t uint8_t
1040
1041 #define QM_NUM_GPIO_PINS (25)
1042
1043 #if (UNIT_TEST)
1044 qm_gpio_reg_t test_gpio_instance;
1045 qm_gpio_reg_t *test_gpio[QM_GPIO_NUM];
1046
1047 #define QM_GPIO test_gpio
1048 #else
1049
1050 /* GPIO register base address. */
1051 #define QM_GPIO_BASE (0xB0000C00)
1052
1053 /* GPIO register block. */
1054 extern qm_gpio_reg_t *qm_gpio[QM_GPIO_NUM];
1055 #define QM_GPIO qm_gpio
1056 #endif
1057
1058 /** @} */
1059
1060 /**
1061 * @name ADC
1062 * @{
1063 */
1064
1065 /** Number of ADC controllers. */
1066 typedef enum { QM_ADC_0 = 0, QM_ADC_NUM } qm_adc_t;
1067
1068 /** ADC register map. */
1069 typedef struct {
1070 QM_RW uint32_t adc_seq0; /**< ADC Channel Sequence Table Entry 0 */
1071 QM_RW uint32_t adc_seq1; /**< ADC Channel Sequence Table Entry 1 */
1072 QM_RW uint32_t adc_seq2; /**< ADC Channel Sequence Table Entry 2 */
1073 QM_RW uint32_t adc_seq3; /**< ADC Channel Sequence Table Entry 3 */
1074 QM_RW uint32_t adc_seq4; /**< ADC Channel Sequence Table Entry 4 */
1075 QM_RW uint32_t adc_seq5; /**< ADC Channel Sequence Table Entry 5 */
1076 QM_RW uint32_t adc_seq6; /**< ADC Channel Sequence Table Entry 6 */
1077 QM_RW uint32_t adc_seq7; /**< ADC Channel Sequence Table Entry 7 */
1078 QM_RW uint32_t adc_cmd; /**< ADC Command Register */
1079 QM_RW uint32_t adc_intr_status; /**< ADC Interrupt Status Register */
1080 QM_RW uint32_t adc_intr_enable; /**< ADC Interrupt Enable Register */
1081 QM_RW uint32_t adc_sample; /**< ADC Sample Register */
1082 QM_RW uint32_t adc_calibration; /**< ADC Calibration Data Register */
1083 QM_RW uint32_t adc_fifo_count; /**< ADC FIFO Count Register */
1084 QM_RW uint32_t adc_op_mode; /**< ADC Operating Mode Register */
1085 } qm_adc_reg_t;
1086
1087 #if (UNIT_TEST)
1088 qm_adc_reg_t test_adc;
1089
1090 #define QM_ADC ((qm_adc_reg_t *)(&test_adc))
1091 #else
1092 /* ADC register block */
1093 #define QM_ADC ((qm_adc_reg_t *)QM_ADC_BASE)
1094
1095 /* ADC register base. */
1096 #define QM_ADC_BASE (0xB0004000)
1097 #endif
1098
1099 #define QM_ADC_DIV_MAX (1023)
1100 #define QM_ADC_DELAY_MAX (0x1FFF)
1101 #define QM_ADC_CAL_MAX (0x3F)
1102 #define QM_ADC_FIFO_LEN (32)
1103 #define QM_ADC_FIFO_CLEAR (0xFFFFFFFF)
1104 /* ADC sequence table */
1105 #define QM_ADC_CAL_SEQ_TABLE_DEFAULT (0x80808080)
1106 /* ADC command */
1107 #define QM_ADC_CMD_SW_OFFSET (24)
1108 #define QM_ADC_CMD_SW_MASK (0xFF000000)
1109 #define QM_ADC_CMD_CAL_DATA_OFFSET (16)
1110 #define QM_ADC_CMD_RESOLUTION_OFFSET (14)
1111 #define QM_ADC_CMD_RESOLUTION_MASK (0xC000)
1112 #define QM_ADC_CMD_NS_OFFSET (4)
1113 #define QM_ADC_CMD_NS_MASK (0x1F0)
1114 #define QM_ADC_CMD_IE_OFFSET (3)
1115 #define QM_ADC_CMD_IE BIT(3)
1116 /* Interrupt enable */
1117 #define QM_ADC_INTR_ENABLE_CC BIT(0)
1118 #define QM_ADC_INTR_ENABLE_FO BIT(1)
1119 #define QM_ADC_INTR_ENABLE_CONT_CC BIT(2)
1120 /* Interrupt status */
1121 #define QM_ADC_INTR_STATUS_CC BIT(0)
1122 #define QM_ADC_INTR_STATUS_FO BIT(1)
1123 #define QM_ADC_INTR_STATUS_CONT_CC BIT(2)
1124 /* Operating mode */
1125 #define QM_ADC_OP_MODE_IE BIT(27)
1126 #define QM_ADC_OP_MODE_DELAY_OFFSET (0x3)
1127 #define QM_ADC_OP_MODE_DELAY_MASK (0xFFF8)
1128 #define QM_ADC_OP_MODE_OM_MASK (0x7)
1129
1130 /** @} */
1131
1132 /**
1133 * @name Flash
1134 * @{
1135 */
1136
1137 #define NUM_FLASH_CONTROLLERS (1)
1138 #define HAS_FLASH_WRITE_DISABLE (1)
1139
1140 /** Number of Flash controllers. */
1141 typedef enum { QM_FLASH_0 = 0, QM_FLASH_NUM } qm_flash_t;
1142
1143 /** Flash register map. */
1144 typedef struct {
1145 QM_RW uint32_t tmg_ctrl; /**< TMG_CTRL */
1146 QM_RW uint32_t rom_wr_ctrl; /**< ROM_WR_CTRL */
1147 QM_RW uint32_t rom_wr_data; /**< ROM_WR_DATA */
1148 QM_RW uint32_t flash_wr_ctrl; /**< FLASH_WR_CTRL */
1149 QM_RW uint32_t flash_wr_data; /**< FLASH_WR_DATA */
1150 QM_RW uint32_t flash_stts; /**< FLASH_STTS */
1151 QM_RW uint32_t ctrl; /**< CTRL */
1152 QM_RW uint32_t fpr_rd_cfg[4]; /**< 4 FPR_RD_CFG registers */
1153 QM_RW uint32_t
1154 mpr_wr_cfg; /**< Flash Write Protection Control Register */
1155 QM_RW uint32_t mpr_vsts; /**< Protection Status Register */
1156 QM_RW uint32_t mpr_vdata; /**< MPR Violation Data Value Register */
1157 } qm_flash_reg_t;
1158
1159 #define qm_flash_context_t uint8_t
1160
1161 #define QM_FLASH_REGION_DATA_0_SIZE (0x1000)
1162 #define QM_FLASH_REGION_DATA_0_PAGES (0x02)
1163
1164 #if (UNIT_TEST)
1165 qm_flash_reg_t test_flash_instance;
1166 qm_flash_reg_t *test_flash[QM_FLASH_NUM];
1167 uint8_t test_flash_page[0x800];
1168
1169 #define QM_FLASH test_flash
1170
1171 #define QM_FLASH_REGION_DATA_0_BASE (test_flash_page)
1172 #define QM_FLASH_REGION_SYS_0_BASE (test_flash_page)
1173 #define QM_FLASH_REGION_OTP_0_BASE (test_flash_page)
1174
1175 #define QM_FLASH_PAGE_MASK (0xCFF)
1176 #define QM_FLASH_MAX_ADDR (0xFFFFFFFF)
1177 #else
1178
1179 /* Flash physical address mappings */
1180 #define QM_FLASH_REGION_DATA_0_BASE (0x00200000)
1181 #define QM_FLASH_REGION_SYS_0_BASE (0x00180000)
1182 #define QM_FLASH_REGION_OTP_0_BASE (0x00000000)
1183
1184 #define QM_FLASH_PAGE_MASK (0xF800)
1185 #define QM_FLASH_MAX_ADDR (0x8000)
1186
1187 /* Flash controller register base address. */
1188 #define QM_FLASH_BASE_0 (0xB0100000)
1189
1190 /* Flash controller register block. */
1191 extern qm_flash_reg_t *qm_flash[QM_FLASH_NUM];
1192 #define QM_FLASH qm_flash
1193
1194 #endif
1195
1196 #define QM_FLASH_REGION_DATA_BASE_OFFSET (0x04)
1197 #define QM_FLASH_MAX_WAIT_STATES (0xF)
1198 #define QM_FLASH_MAX_US_COUNT (0x3F)
1199 #define QM_FLASH_MAX_PAGE_NUM \
1200 (QM_FLASH_MAX_ADDR / (4 * QM_FLASH_PAGE_SIZE_DWORDS))
1201 #define QM_FLASH_CLK_SLOW BIT(14)
1202 #define QM_FLASH_LVE_MODE BIT(5)
1203
1204 /* Flash mask to clear timing. */
1205 #define QM_FLASH_TMG_DEF_MASK (0xFFFFFC00)
1206 /* Flash mask to clear micro seconds. */
1207 #define QM_FLASH_MICRO_SEC_COUNT_MASK (0x3F)
1208 /* Flash mask to clear wait state. */
1209 #define QM_FLASH_WAIT_STATE_MASK (0x3C0)
1210 /* Flash wait state offset bit. */
1211 #define QM_FLASH_WAIT_STATE_OFFSET (6)
1212 /* Flash write disable offset bit. */
1213 #define QM_FLASH_WRITE_DISABLE_OFFSET (4)
1214 /* Flash write disable value. */
1215 #define QM_FLASH_WRITE_DISABLE_VAL BIT(4)
1216
1217 /* Flash page erase request. */
1218 #define ER_REQ BIT(1)
1219 /* Flash page erase done. */
1220 #define ER_DONE (1)
1221 /* Flash page write request. */
1222 #define WR_REQ (1)
1223 /* Flash page write done. */
1224 #define WR_DONE BIT(1)
1225
1226 /* Flash write address offset. */
1227 #define WR_ADDR_OFFSET (2)
1228 /* Flash perform mass erase includes OTP region. */
1229 #define MASS_ERASE_INFO BIT(6)
1230 /* Flash perform mass erase. */
1231 #define MASS_ERASE BIT(7)
1232
1233 /* ROM read disable for upper 4k. */
1234 #define ROM_RD_DIS_U BIT(3)
1235 /* ROM read disable for lower 4k. */
1236 #define ROM_RD_DIS_L BIT(2)
1237 /* Flash prefetch buffer flush bit. */
1238 #define QM_FLASH_CTRL_PRE_FLUSH_MASK BIT(1)
1239 /* Flash prefetch enable bit. */
1240 #define QM_FLASH_CTRL_PRE_EN_MASK BIT(0)
1241
1242 #define QM_FLASH_ADDRESS_MASK (0x7FF)
1243 /* Increment by 4 bytes each time, but there is an offset of 2, so 0x10. */
1244 #define QM_FLASH_ADDR_INC (0x10)
1245
1246 /* Flash page size in dwords. */
1247 #define QM_FLASH_PAGE_SIZE_DWORDS (0x200)
1248 /* Flash page size in bytes. */
1249 #define QM_FLASH_PAGE_SIZE_BYTES (0x800)
1250 /* Flash page size in bits. */
1251 #define QM_FLASH_PAGE_SIZE_BITS (11)
1252 /* OTP ROM_PROG bit. */
1253 #define QM_FLASH_STTS_ROM_PROG (BIT(2))
1254
1255 /** @} */
1256
1257 /**
1258 * @name Flash Protection Region
1259 * @{
1260 */
1261
1262 /**
1263 * FPR register map.
1264 */
1265 typedef enum {
1266 QM_FPR_0, /**< FPR 0. */
1267 QM_FPR_1, /**< FPR 1. */
1268 QM_FPR_2, /**< FPR 2. */
1269 QM_FPR_3, /**< FPR 3. */
1270 QM_FPR_NUM
1271 } qm_fpr_id_t;
1272
1273 #define qm_fpr_context_t uint8_t
1274
1275 /* The addressing granularity of FPRs. */
1276 #define QM_FPR_GRANULARITY (1024)
1277
1278 /** @} */
1279
1280 /**
1281 * @name Memory Protection Region
1282 * @{
1283 */
1284
1285 /* MPR identifier */
1286 typedef enum {
1287 QM_MPR_0 = 0, /**< Memory Protection Region 0. */
1288 QM_MPR_1, /**< Memory Protection Region 1. */
1289 QM_MPR_2, /**< Memory Protection Region 2. */
1290 QM_MPR_3, /**< Memory Protection Region 3. */
1291 QM_MPR_NUM /**< Number of Memory Protection Regions. */
1292 } qm_mpr_id_t;
1293
1294 /** Memory Protection Region register map. */
1295 typedef struct {
1296 QM_RW uint32_t mpr_cfg[4]; /**< MPR CFG */
1297 QM_RW uint32_t mpr_vdata; /**< MPR_VDATA */
1298 QM_RW uint32_t mpr_vsts; /**< MPR_VSTS */
1299 } qm_mpr_reg_t;
1300
1301 #define qm_mpr_context_t uint8_t
1302
1303 /* The addressing granularity of MPRs. */
1304 #define QM_MPR_GRANULARITY (1024)
1305
1306 #if (UNIT_TEST)
1307 qm_mpr_reg_t test_mpr;
1308
1309 #define QM_MPR ((qm_mpr_reg_t *)(&test_mpr))
1310
1311 #else
1312
1313 #define QM_MPR_BASE (0xB0400000)
1314 #define QM_MPR ((qm_mpr_reg_t *)QM_MPR_BASE)
1315
1316 #endif
1317
1318 #define QM_MPR_UP_BOUND_OFFSET (10)
1319 #define QM_MPR_WR_EN_OFFSET (20)
1320 #define QM_MPR_WR_EN_MASK 0x700000
1321 #define QM_MPR_RD_EN_OFFSET (24)
1322 #define QM_MPR_RD_EN_MASK 0x7000000
1323 #define QM_MPR_EN_LOCK_OFFSET (30)
1324 #define QM_MPR_EN_LOCK_MASK 0xC0000000
1325 #define QM_MPR_VSTS_VALID BIT(31)
1326
1327 /** @} */
1328
1329 /**
1330 * @name PIC
1331 * @{
1332 */
1333
1334 /** PIC timer register structure. */
1335 typedef struct {
1336 QM_RW uint32_t reg;
1337 QM_RW uint32_t pad[3];
1338 } pic_timer_reg_pad_t;
1339
1340 /** PIC timer register map. */
1341 typedef struct {
1342 QM_RW pic_timer_reg_pad_t lvttimer; /**< Local Vector Table Timer */
1343 QM_RW pic_timer_reg_pad_t reserved[5];
1344 QM_RW pic_timer_reg_pad_t timer_icr; /**< Initial Count Register */
1345 QM_RW pic_timer_reg_pad_t timer_ccr; /**< Current Count Register */
1346 } qm_pic_timer_reg_t;
1347
1348 #define qm_pic_timer_context_t uint8_t
1349
1350 #if (UNIT_TEST)
1351 qm_pic_timer_reg_t test_pic_timer;
1352 #define QM_PIC_TIMER ((qm_pic_timer_reg_t *)(&test_pic_timer))
1353
1354 #else
1355 /* PIC timer base address. */
1356 #define QM_PIC_TIMER_BASE (0xFEE00320)
1357 #define QM_PIC_TIMER ((qm_pic_timer_reg_t *)QM_PIC_TIMER_BASE)
1358 #endif
1359
1360 /** @} */
1361
1362 /**
1363 * @name Peripheral Clock
1364 * @{
1365 */
1366
1367 /** Peripheral clock register map. */
1368 typedef enum {
1369 CLK_PERIPH_REGISTER = BIT(0), /**< Peripheral Clock Gate Enable. */
1370 CLK_PERIPH_CLK = BIT(1), /**< Peripheral Clock Enable. */
1371 CLK_PERIPH_I2C_M0 = BIT(2), /**< I2C Master 0 Clock Enable. */
1372 CLK_PERIPH_SPI_S = BIT(4), /**< SPI Slave Clock Enable. */
1373 CLK_PERIPH_SPI_M0 = BIT(5), /**< SPI Master 0 Clock Enable. */
1374 CLK_PERIPH_GPIO_INTERRUPT = BIT(7), /**< GPIO Interrupt Clock Enable. */
1375 CLK_PERIPH_GPIO_DB = BIT(8), /**< GPIO Debounce Clock Enable. */
1376 CLK_PERIPH_WDT_REGISTER = BIT(10), /**< Watchdog Clock Enable. */
1377 CLK_PERIPH_RTC_REGISTER = BIT(11), /**< RTC Clock Gate Enable. */
1378 CLK_PERIPH_PWM_REGISTER = BIT(12), /**< PWM Clock Gate Enable. */
1379 CLK_PERIPH_GPIO_REGISTER = BIT(13), /**< GPIO Clock Gate Enable. */
1380 CLK_PERIPH_SPI_M0_REGISTER =
1381 BIT(14), /**< SPI Master 0 Clock Gate Enable. */
1382 CLK_PERIPH_SPI_S_REGISTER =
1383 BIT(16), /**< SPI Slave Clock Gate Enable. */
1384 CLK_PERIPH_UARTA_REGISTER = BIT(17), /**< UARTA Clock Gate Enable. */
1385 CLK_PERIPH_UARTB_REGISTER = BIT(18), /**< UARTB Clock Gate Enable. */
1386 CLK_PERIPH_I2C_M0_REGISTER =
1387 BIT(19), /**< I2C Master 0 Clock Gate Enable. */
1388 CLK_PERIPH_ADC = BIT(22), /**< ADC Clock Enable. */
1389 CLK_PERIPH_ADC_REGISTER = BIT(23), /**< ADC Clock Gate Enable. */
1390 CLK_PERIPH_ALL = 0xCFFFFF /**< Quark D2000 peripherals Enable. */
1391 } clk_periph_t;
1392
1393 /* Default mask values */
1394 #define CLK_EXTERN_DIV_DEF_MASK (0xFFFFFFE3)
1395 #define CLK_SYS_CLK_DIV_DEF_MASK (0xFFFFF87F)
1396 #define CLK_RTC_DIV_DEF_MASK (0xFFFFFF83)
1397 #define CLK_GPIO_DB_DIV_DEF_MASK (0xFFFFFFE1)
1398 #define CLK_ADC_DIV_DEF_MASK (0xFC00FFFF)
1399 #define CLK_PERIPH_DIV_DEF_MASK (0xFFFFFFF9)
1400
1401 /** @} */
1402
1403 /**
1404 * @name MVIC
1405 * @{
1406 */
1407
1408 /** MVIC register structure. */
1409 typedef struct {
1410 QM_RW uint32_t reg;
1411 QM_RW uint32_t pad[3];
1412 } mvic_reg_pad_t;
1413
1414 /** MVIC register map. */
1415 typedef struct {
1416 QM_RW mvic_reg_pad_t tpr; /**< Task priority. */
1417 QM_RW mvic_reg_pad_t reserved;
1418 QM_RW mvic_reg_pad_t ppr; /**< Processor priority. */
1419 QM_RW mvic_reg_pad_t eoi; /**< End of interrupt. */
1420 QM_RW mvic_reg_pad_t reserved1[3];
1421 QM_RW mvic_reg_pad_t sivr; /**< Spurious vector. */
1422 QM_RW mvic_reg_pad_t reserved2;
1423 QM_RW mvic_reg_pad_t isr; /**< In-service. */
1424 QM_RW mvic_reg_pad_t reserved3[15];
1425 QM_RW mvic_reg_pad_t irr; /**< Interrupt request. */
1426 QM_RW mvic_reg_pad_t reserved4[16];
1427 QM_RW mvic_reg_pad_t lvttimer; /**< Timer vector. */
1428 QM_RW mvic_reg_pad_t reserved5[5];
1429 QM_RW mvic_reg_pad_t icr; /**< Timer initial count. */
1430 QM_RW mvic_reg_pad_t ccr; /**< Timer current count. */
1431 } qm_mvic_reg_t;
1432
1433 #define qm_irq_context_t uint8_t
1434
1435 #define QM_MVIC_REG_VER (0x01) /* MVIC version. */
1436 #define QM_MVIC_REG_REDTBL (0x10) /* Redirection table base. */
1437
1438 #if (UNIT_TEST)
1439 qm_mvic_reg_t test_mvic;
1440 #define QM_MVIC ((qm_mvic_reg_t *)(&test_mvic))
1441
1442 #else
1443 /* Interrupt Controller base address. */
1444 #define QM_MVIC_BASE (0xFEE00080)
1445 #define QM_MVIC ((qm_mvic_reg_t *)QM_MVIC_BASE)
1446 #endif
1447
1448 #define QM_INT_CONTROLLER QM_MVIC
1449 /* Signal the interrupt controller that the interrupt was handled. The vector
1450 * argument is ignored. */
1451 #if defined(ENABLE_EXTERNAL_ISR_HANDLING)
1452 #define QM_ISR_EOI(vector)
1453 #else
1454 #define QM_ISR_EOI(vector) (QM_INT_CONTROLLER->eoi.reg = 0)
1455 #endif
1456
1457 typedef struct {
1458 QM_RW mvic_reg_pad_t ioregsel; /**< Register selector. */
1459 QM_RW mvic_reg_pad_t iowin; /**< Register window. */
1460 } qm_ioapic_reg_t;
1461
1462 #if (UNIT_TEST)
1463 qm_ioapic_reg_t test_ioapic;
1464 #define QM_IOAPIC ((qm_ioapic_reg_t *)(&test_ioapic))
1465
1466 #else
1467 /* IO/APIC. */
1468 #define QM_IOAPIC_BASE (0xFEC00000)
1469 #define QM_IOAPIC ((qm_ioapic_reg_t *)QM_IOAPIC_BASE)
1470 #endif
1471
1472 /** @} */
1473
1474 /**
1475 * @name DMA
1476 * @{
1477 */
1478
1479 /** DMA instances. */
1480 typedef enum {
1481 QM_DMA_0, /**< DMA controller id. */
1482 QM_DMA_NUM /**< Number of DMA controllers. */
1483 } qm_dma_t;
1484
1485 /** DMA channel IDs. */
1486 typedef enum {
1487 QM_DMA_CHANNEL_0 = 0, /**< DMA channel id for channel 0 */
1488 QM_DMA_CHANNEL_1, /**< DMA channel id for channel 1 */
1489 QM_DMA_CHANNEL_NUM /**< Number of DMA channels */
1490 } qm_dma_channel_id_t;
1491
1492 /** DMA hardware handshake interfaces. */
1493 typedef enum {
1494 DMA_HW_IF_UART_A_TX = 0x0, /**< UART_A_TX */
1495 DMA_HW_IF_UART_A_RX = 0x1, /**< UART_A_RX */
1496 DMA_HW_IF_UART_B_TX = 0x2, /**< UART_B_TX*/
1497 DMA_HW_IF_UART_B_RX = 0x3, /**< UART_B_RX */
1498 DMA_HW_IF_SPI_MASTER_0_TX = 0x4, /**< SPI_Master_0_TX */
1499 DMA_HW_IF_SPI_MASTER_0_RX = 0x5, /**< SPI_Master_0_RX */
1500 DMA_HW_IF_SPI_SLAVE_TX = 0x8, /**< SPI_Slave_TX */
1501 DMA_HW_IF_SPI_SLAVE_RX = 0x9, /**< SPI_Slave_RX */
1502 DMA_HW_IF_I2C_MASTER_0_TX = 0xc, /**< I2C_Master_0_TX */
1503 DMA_HW_IF_I2C_MASTER_0_RX = 0xd, /**< I2C_Master_0_RX */
1504 } qm_dma_handshake_interface_t;
1505
1506 /** DMA channel register map. */
1507 typedef struct {
1508 QM_RW uint32_t sar_low; /**< SAR */
1509 QM_RW uint32_t sar_high; /**< SAR */
1510 QM_RW uint32_t dar_low; /**< DAR */
1511 QM_RW uint32_t dar_high; /**< DAR */
1512 QM_RW uint32_t llp_low; /**< LLP */
1513 QM_RW uint32_t llp_high; /**< LLP */
1514 QM_RW uint32_t ctrl_low; /**< CTL */
1515 QM_RW uint32_t ctrl_high; /**< CTL */
1516 QM_RW uint32_t src_stat_low; /**< SSTAT */
1517 QM_RW uint32_t src_stat_high; /**< SSTAT */
1518 QM_RW uint32_t dst_stat_low; /**< DSTAT */
1519 QM_RW uint32_t dst_stat_high; /**< DSTAT */
1520 QM_RW uint32_t src_stat_addr_low; /**< SSTATAR */
1521 QM_RW uint32_t src_stat_addr_high; /**< SSTATAR */
1522 QM_RW uint32_t dst_stat_addr_low; /**< DSTATAR */
1523 QM_RW uint32_t dst_stat_addr_high; /**< DSTATAR */
1524 QM_RW uint32_t cfg_low; /**< CFG */
1525 QM_RW uint32_t cfg_high; /**< CFG */
1526 QM_RW uint32_t src_sg_low; /**< SGR */
1527 QM_RW uint32_t src_sg_high; /**< SGR */
1528 QM_RW uint32_t dst_sg_low; /**< DSR */
1529 QM_RW uint32_t dst_sg_high; /**< DSR */
1530 } qm_dma_chan_reg_t;
1531
1532 #define qm_dma_context_t uint8_t
1533
1534 /* DMA channel control register offsets and masks. */
1535 #define QM_DMA_CTL_L_INT_EN_MASK BIT(0)
1536 #define QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET (1)
1537 #define QM_DMA_CTL_L_DST_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET)
1538 #define QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET (4)
1539 #define QM_DMA_CTL_L_SRC_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET)
1540 #define QM_DMA_CTL_L_DINC_OFFSET (7)
1541 #define QM_DMA_CTL_L_DINC_MASK (0x3 << QM_DMA_CTL_L_DINC_OFFSET)
1542 #define QM_DMA_CTL_L_SINC_OFFSET (9)
1543 #define QM_DMA_CTL_L_SINC_MASK (0x3 << QM_DMA_CTL_L_SINC_OFFSET)
1544 #define QM_DMA_CTL_L_DEST_MSIZE_OFFSET (11)
1545 #define QM_DMA_CTL_L_DEST_MSIZE_MASK (0x7 << QM_DMA_CTL_L_DEST_MSIZE_OFFSET)
1546 #define QM_DMA_CTL_L_SRC_MSIZE_OFFSET (14)
1547 #define QM_DMA_CTL_L_SRC_MSIZE_MASK (0x7 << QM_DMA_CTL_L_SRC_MSIZE_OFFSET)
1548 #define QM_DMA_CTL_L_TT_FC_OFFSET (20)
1549 #define QM_DMA_CTL_L_TT_FC_MASK (0x7 << QM_DMA_CTL_L_TT_FC_OFFSET)
1550 #define QM_DMA_CTL_L_LLP_DST_EN_MASK BIT(27)
1551 #define QM_DMA_CTL_L_LLP_SRC_EN_MASK BIT(28)
1552 #define QM_DMA_CTL_H_BLOCK_TS_OFFSET (0)
1553 #define QM_DMA_CTL_H_BLOCK_TS_MASK (0xfff << QM_DMA_CTL_H_BLOCK_TS_OFFSET)
1554 #define QM_DMA_CTL_H_BLOCK_TS_MAX 4095
1555 #define QM_DMA_CTL_H_BLOCK_TS_MIN 1
1556
1557 /* DMA channel config register offsets and masks. */
1558 #define QM_DMA_CFG_L_CH_SUSP_MASK BIT(8)
1559 #define QM_DMA_CFG_L_FIFO_EMPTY_MASK BIT(9)
1560 #define QM_DMA_CFG_L_HS_SEL_DST_OFFSET 10
1561 #define QM_DMA_CFG_L_HS_SEL_DST_MASK BIT(QM_DMA_CFG_L_HS_SEL_DST_OFFSET)
1562 #define QM_DMA_CFG_L_HS_SEL_SRC_OFFSET 11
1563 #define QM_DMA_CFG_L_HS_SEL_SRC_MASK BIT(QM_DMA_CFG_L_HS_SEL_SRC_OFFSET)
1564 #define QM_DMA_CFG_L_DST_HS_POL_OFFSET 18
1565 #define QM_DMA_CFG_L_DST_HS_POL_MASK BIT(QM_DMA_CFG_L_DST_HS_POL_OFFSET)
1566 #define QM_DMA_CFG_L_SRC_HS_POL_OFFSET 19
1567 #define QM_DMA_CFG_L_SRC_HS_POL_MASK BIT(QM_DMA_CFG_L_SRC_HS_POL_OFFSET)
1568 #define QM_DMA_CFG_L_RELOAD_SRC_MASK BIT(30)
1569 #define QM_DMA_CFG_L_RELOAD_DST_MASK BIT(31)
1570 #define QM_DMA_CFG_H_DS_UPD_EN_OFFSET (5)
1571 #define QM_DMA_CFG_H_DS_UPD_EN_MASK BIT(QM_DMA_CFG_H_DS_UPD_EN_OFFSET)
1572 #define QM_DMA_CFG_H_SS_UPD_EN_OFFSET (6)
1573 #define QM_DMA_CFG_H_SS_UPD_EN_MASK BIT(QM_DMA_CFG_H_SS_UPD_EN_OFFSET)
1574 #define QM_DMA_CFG_H_SRC_PER_OFFSET (7)
1575 #define QM_DMA_CFG_H_SRC_PER_MASK (0xf << QM_DMA_CFG_H_SRC_PER_OFFSET)
1576 #define QM_DMA_CFG_H_DEST_PER_OFFSET (11)
1577 #define QM_DMA_CFG_H_DEST_PER_MASK (0xf << QM_DMA_CFG_H_DEST_PER_OFFSET)
1578
1579 #define QM_DMA_ENABLE_CLOCK(dma) \
1580 (QM_SCSS_CCU->ccu_mlayer_ahb_ctl |= QM_CCU_DMA_CLK_EN)
1581
1582 /** DMA interrupt register map. */
1583 typedef struct {
1584 QM_RW uint32_t raw_tfr_low; /**< RawTfr */
1585 QM_RW uint32_t raw_tfr_high; /**< RawTfr */
1586 QM_RW uint32_t raw_block_low; /**< RawBlock */
1587 QM_RW uint32_t raw_block_high; /**< RawBlock */
1588 QM_RW uint32_t raw_src_trans_low; /**< RawSrcTran */
1589 QM_RW uint32_t raw_src_trans_high; /**< RawSrcTran */
1590 QM_RW uint32_t raw_dst_trans_low; /**< RawDstTran */
1591 QM_RW uint32_t raw_dst_trans_high; /**< RawDstTran */
1592 QM_RW uint32_t raw_err_low; /**< RawErr */
1593 QM_RW uint32_t raw_err_high; /**< RawErr */
1594 QM_RW uint32_t status_tfr_low; /**< StatusTfr */
1595 QM_RW uint32_t status_tfr_high; /**< StatusTfr */
1596 QM_RW uint32_t status_block_low; /**< StatusBlock */
1597 QM_RW uint32_t status_block_high; /**< StatusBlock */
1598 QM_RW uint32_t status_src_trans_low; /**< StatusSrcTran */
1599 QM_RW uint32_t status_src_trans_high; /**< StatusSrcTran */
1600 QM_RW uint32_t status_dst_trans_low; /**< StatusDstTran */
1601 QM_RW uint32_t status_dst_trans_high; /**< StatusDstTran */
1602 QM_RW uint32_t status_err_low; /**< StatusErr */
1603 QM_RW uint32_t status_err_high; /**< StatusErr */
1604 QM_RW uint32_t mask_tfr_low; /**< MaskTfr */
1605 QM_RW uint32_t mask_tfr_high; /**< MaskTfr */
1606 QM_RW uint32_t mask_block_low; /**< MaskBlock */
1607 QM_RW uint32_t mask_block_high; /**< MaskBlock */
1608 QM_RW uint32_t mask_src_trans_low; /**< MaskSrcTran */
1609 QM_RW uint32_t mask_src_trans_high; /**< MaskSrcTran */
1610 QM_RW uint32_t mask_dst_trans_low; /**< MaskDstTran */
1611 QM_RW uint32_t mask_dst_trans_high; /**< MaskDstTran */
1612 QM_RW uint32_t mask_err_low; /**< MaskErr */
1613 QM_RW uint32_t mask_err_high; /**< MaskErr */
1614 QM_RW uint32_t clear_tfr_low; /**< ClearTfr */
1615 QM_RW uint32_t clear_tfr_high; /**< ClearTfr */
1616 QM_RW uint32_t clear_block_low; /**< ClearBlock */
1617 QM_RW uint32_t clear_block_high; /**< ClearBlock */
1618 QM_RW uint32_t clear_src_trans_low; /**< ClearSrcTran */
1619 QM_RW uint32_t clear_src_trans_high; /**< ClearSrcTran */
1620 QM_RW uint32_t clear_dst_trans_low; /**< ClearDstTran */
1621 QM_RW uint32_t clear_dst_trans_high; /**< ClearDstTran */
1622 QM_RW uint32_t clear_err_low; /**< ClearErr */
1623 QM_RW uint32_t clear_err_high; /**< ClearErr */
1624 QM_RW uint32_t status_int_low; /**< StatusInt */
1625 QM_RW uint32_t status_int_high; /**< StatusInt */
1626 } qm_dma_int_reg_t;
1627
1628 /* DMA interrupt status register bits. */
1629 #define QM_DMA_INT_STATUS_TFR BIT(0)
1630 #define QM_DMA_INT_STATUS_BLOCK BIT(1)
1631 #define QM_DMA_INT_STATUS_ERR BIT(4)
1632
1633 /** DMA miscellaneous register map. */
1634 typedef struct {
1635 QM_RW uint32_t cfg_low; /**< DmaCfgReg */
1636 QM_RW uint32_t cfg_high; /**< DmaCfgReg */
1637 QM_RW uint32_t chan_en_low; /**< ChEnReg */
1638 QM_RW uint32_t chan_en_high; /**< ChEnReg */
1639 QM_RW uint32_t id_low; /**< DmaIdReg */
1640 QM_RW uint32_t id_high; /**< DmaIdReg */
1641 QM_RW uint32_t test_low; /**< DmaTestReg */
1642 QM_RW uint32_t test_high; /**< DmaTestReg */
1643 QM_RW uint32_t reserved[4]; /**< Reserved */
1644 } qm_dma_misc_reg_t;
1645
1646 /* Channel write enable in the misc channel enable register. */
1647 #define QM_DMA_MISC_CHAN_EN_WE_OFFSET (8)
1648
1649 /* Controller enable bit in the misc config register. */
1650 #define QM_DMA_MISC_CFG_DMA_EN BIT(0)
1651
1652 typedef struct {
1653 QM_RW qm_dma_chan_reg_t chan_reg[8]; /**< Channel Register */
1654 QM_RW qm_dma_int_reg_t int_reg; /**< Interrupt Register */
1655 QM_RW uint32_t reserved[12]; /**< Reserved (SW HS) */
1656 QM_RW qm_dma_misc_reg_t misc_reg; /**< Miscellaneous Register */
1657 } qm_dma_reg_t;
1658
1659 #if (UNIT_TEST)
1660 qm_dma_reg_t test_dma_instance[QM_DMA_NUM];
1661 qm_dma_reg_t *test_dma[QM_DMA_NUM];
1662 #define QM_DMA test_dma
1663 #else
1664 #define QM_DMA_BASE (0xB0700000)
1665 extern qm_dma_reg_t *qm_dma[QM_DMA_NUM];
1666 #define QM_DMA qm_dma
1667 #endif
1668
1669 /** @} */
1670
1671 /**
1672 * @name Hardware Fixes
1673 * @{
1674 */
1675
1676 /* Refer to "HARDWARE_ISSUES.rst" for fix description. */
1677 #define FIX_1 (1)
1678 #define FIX_2 (0)
1679 #define FIX_3 (1)
1680
1681 /** @} */
1682
1683 /**
1684 * @name Versioning
1685 * @{
1686 */
1687
1688 #if (UNIT_TEST)
1689 uint32_t test_rom_version;
1690 #define ROM_VERSION_ADDRESS &test_rom_version;
1691 #else
1692 #define ROM_VERSION_ADDRESS \
1693 (BL_DATA_FLASH_REGION_BASE + \
1694 (BL_DATA_SECTION_BASE_PAGE * QM_FLASH_PAGE_SIZE_BYTES) + \
1695 sizeof(qm_flash_data_trim_t))
1696 #endif
1697
1698 /** @} */
1699
1700 /** @} */
1701
1702 #endif /* __REGISTERS_H__ */
qm_gpio_reg_t::gpio_inten
QM_RW uint32_t gpio_inten
Interrupt Enable.
Definition: qm_soc_regs.h:1021
qm_flash_reg_t::flash_stts
QM_RW uint32_t flash_stts
FLASH_STTS.
Definition: qm_soc_regs.h:1150
qm_dma_chan_reg_t::src_sg_high
QM_RW uint32_t src_sg_high
SGR.
Definition: qm_soc_regs.h:1527
qm_uart_reg_t::de_en
QM_RW uint32_t de_en
Driver Output Enable Register.
Definition: qm_soc_regs.h:674
qm_mvic_reg_t::eoi
QM_RW mvic_reg_pad_t eoi
End of interrupt.
Definition: qm_soc_regs.h:1419
QM_FPR_0
FPR 0.
Definition: qm_soc_regs.h:1266
qm_i2c_reg_t::ic_fs_spklen
QM_RW uint32_t ic_fs_spklen
SS and FS Spike Suppression Limit.
Definition: qm_soc_regs.h:911
qm_dma_chan_reg_t::cfg_low
QM_RW uint32_t cfg_low
CFG.
Definition: qm_soc_regs.h:1524
CLK_PERIPH_UARTA_REGISTER
UARTA Clock Gate Enable.
Definition: qm_soc_regs.h:1384
qm_aonc_reg_t::aonpt_ctrl
QM_RW uint32_t aonpt_ctrl
Always-on periodic timer control.
Definition: qm_soc_regs.h:264
qm_i2c_reg_t::ic_status
QM_RW uint32_t ic_status
Status.
Definition: qm_soc_regs.h:899
qm_scss_info_reg_t::cotps
QM_RW uint32_t cotps
Code OTP Size Register.
Definition: qm_soc_regs.h:362
qm_scss_ccu_reg_t::ccu_sys_clk_ctl
QM_RW uint32_t ccu_sys_clk_ctl
System Clock Control Register.
Definition: qm_soc_regs.h:49
qm_scss_ccu_reg_t::osc1_stat0
QM_RW uint32_t osc1_stat0
RTC Oscillator status 0.
Definition: qm_soc_regs.h:34
qm_wdt_reg_t::wdt_torr
QM_RW uint32_t wdt_torr
Timeout Range Register.
Definition: qm_soc_regs.h:472
qm_dma_chan_reg_t::dst_stat_addr_low
QM_RW uint32_t dst_stat_addr_low
DSTATAR.
Definition: qm_soc_regs.h:1522
qm_dma_int_reg_t
DMA interrupt register map.
Definition: qm_soc_regs.h:1583
qm_uart_reg_t::tar
QM_RW uint32_t tar
Transmit Address Register.
Definition: qm_soc_regs.h:680
qm_adc_reg_t::adc_fifo_count
QM_RW uint32_t adc_fifo_count
ADC FIFO Count Register.
Definition: qm_soc_regs.h:1083
qm_mpr_id_t
qm_mpr_id_t
Definition: qm_soc_regs.h:1286
qm_pwm_channel_t::intstatus
QM_RW uint32_t intstatus
Interrupt Status.
Definition: qm_soc_regs.h:394
qm_dma_chan_reg_t::ctrl_low
QM_RW uint32_t ctrl_low
CTL.
Definition: qm_soc_regs.h:1514
qm_spi_reg_t::dmardlr
QM_RW uint32_t dmardlr
DMA Receive Data Level.
Definition: qm_soc_regs.h:737
qm_spi_reg_t::isr
QM_RW uint32_t isr
Interrupt Status Register.
Definition: qm_soc_regs.h:725
qm_scss_ccu_reg_t::ccu_mlayer_ahb_ctl
QM_RW uint32_t ccu_mlayer_ahb_ctl
AHB Control Register.
Definition: qm_soc_regs.h:48
qm_i2c_reg_t::ic_hs_scl_hcnt
QM_RW uint32_t ic_hs_scl_hcnt
High Speed I2C Clock SCL High Count.
Definition: qm_soc_regs.h:878
qm_scss_pmux_reg_t
Pin MUX register map.
Definition: qm_soc_regs.h:324
qm_wdt_reg_t::wdt_comp_version
QM_RW uint32_t wdt_comp_version
Component Version Register.
Definition: qm_soc_regs.h:483
qm_spi_reg_t::txftlr
QM_RW uint32_t txftlr
Transmit FIFO Threshold Level.
Definition: qm_soc_regs.h:719
qm_adc_reg_t::adc_seq6
QM_RW uint32_t adc_seq6
ADC Channel Sequence Table Entry 6.
Definition: qm_soc_regs.h:1076
qm_spi_reg_t::rx_sample_dly
QM_RW uint32_t rx_sample_dly
RX Sample Delay Register.
Definition: qm_soc_regs.h:741
qm_dma_int_reg_t::raw_src_trans_low
QM_RW uint32_t raw_src_trans_low
RawSrcTran.
Definition: qm_soc_regs.h:1588
qm_scss_gp_reg_t::gp2
QM_RW uint32_t gp2
General Purpose Scratchpad Register 2.
Definition: qm_soc_regs.h:152
QM_FPR_2
FPR 2.
Definition: qm_soc_regs.h:1268
qm_spi_reg_t::dmacr
QM_RW uint32_t dmacr
DMA Control Register.
Definition: qm_soc_regs.h:735
qm_adc_reg_t::adc_op_mode
QM_RW uint32_t adc_op_mode
ADC Operating Mode Register.
Definition: qm_soc_regs.h:1084
qm_i2c_reg_t::ic_intr_stat
QM_RW uint32_t ic_intr_stat
Interrupt Status.
Definition: qm_soc_regs.h:881
qm_i2c_reg_t::ic_comp_param_1
QM_RW uint32_t ic_comp_param_1
Configuration Parameters.
Definition: qm_soc_regs.h:916
qm_scss_info_reg_t::id
QM_RW uint32_t id
Identification Register.
Definition: qm_soc_regs.h:358
qm_scss_ccu_reg_t::osc0_cfg0
QM_RW uint32_t osc0_cfg0
Hybrid Oscillator Configuration 0.
Definition: qm_soc_regs.h:31
qm_dma_chan_reg_t::dar_high
QM_RW uint32_t dar_high
DAR.
Definition: qm_soc_regs.h:1511
qm_dma_chan_reg_t::src_stat_low
QM_RW uint32_t src_stat_low
SSTAT.
Definition: qm_soc_regs.h:1516
qm_i2c_reg_t
I2C register map.
Definition: qm_soc_regs.h:864
DMA_HW_IF_SPI_MASTER_0_RX
SPI_Master_0_RX.
Definition: qm_soc_regs.h:1499
DMA_HW_IF_SPI_SLAVE_TX
SPI_Slave_TX.
Definition: qm_soc_regs.h:1500
qm_dma_int_reg_t::status_src_trans_low
QM_RW uint32_t status_src_trans_low
StatusSrcTran.
Definition: qm_soc_regs.h:1598
qm_dma_int_reg_t::mask_tfr_high
QM_RW uint32_t mask_tfr_high
MaskTfr.
Definition: qm_soc_regs.h:1605
qm_adc_reg_t::adc_seq3
QM_RW uint32_t adc_seq3
ADC Channel Sequence Table Entry 3.
Definition: qm_soc_regs.h:1073
qm_dma_int_reg_t::raw_block_low
QM_RW uint32_t raw_block_low
RawBlock.
Definition: qm_soc_regs.h:1586
CLK_PERIPH_GPIO_DB
GPIO Debounce Clock Enable.
Definition: qm_soc_regs.h:1375
qm_i2c_reg_t::ic_clr_intr
QM_RW uint32_t ic_clr_intr
Clear Combined and Individual Interrupt.
Definition: qm_soc_regs.h:887
qm_dma_int_reg_t::status_err_high
QM_RW uint32_t status_err_high
StatusErr.
Definition: qm_soc_regs.h:1603
qm_dma_int_reg_t::clear_dst_trans_high
QM_RW uint32_t clear_dst_trans_high
ClearDstTran.
Definition: qm_soc_regs.h:1621
qm_rtc_reg_t::rtc_clr
QM_RW uint32_t rtc_clr
Counter Load Register.
Definition: qm_soc_regs.h:824
qm_scss_ccu_reg_t::wake_mask
QM_RW uint32_t wake_mask
Wake Mask register.
Definition: qm_soc_regs.h:47
qm_spi_reg_t::ctrlr1
QM_RW uint32_t ctrlr1
Control Register 1.
Definition: qm_soc_regs.h:714
qm_adc_reg_t::adc_intr_status
QM_RW uint32_t adc_intr_status
ADC Interrupt Status Register.
Definition: qm_soc_regs.h:1079
qm_i2c_reg_t::ic_clr_rx_under
QM_RW uint32_t ic_clr_rx_under
Clear RX_UNDER Interrupt.
Definition: qm_soc_regs.h:888
DMA_HW_IF_UART_B_RX
UART_B_RX.
Definition: qm_soc_regs.h:1497
qm_spi_reg_t::baudr
QM_RW uint32_t baudr
Baud Rate Select.
Definition: qm_soc_regs.h:718
qm_gpio_reg_t::gpio_config_reg2
QM_RW uint32_t gpio_config_reg2
GPIO Configuration Register 2.
Definition: qm_soc_regs.h:1035
qm_i2c_reg_t::ic_hs_spklen
QM_RW uint32_t ic_hs_spklen
HS spike suppression limit.
Definition: qm_soc_regs.h:912
qm_scss_ccu_reg_t::soc_ctrl_lock
QM_RW uint32_t soc_ctrl_lock
SoC Control Register Lock.
Definition: qm_soc_regs.h:52
qm_gpio_reg_t::gpio_config_reg1
QM_RW uint32_t gpio_config_reg1
GPIO Configuration Register 1.
Definition: qm_soc_regs.h:1036
qm_scss_gp_reg_t::gp1
QM_RW uint32_t gp1
General Purpose Scratchpad Register 1.
Definition: qm_soc_regs.h:151
qm_dma_t
qm_dma_t
DMA instances.
Definition: qm_soc_regs.h:1480
qm_i2c_reg_t::ic_clr_rx_over
QM_RW uint32_t ic_clr_rx_over
Clear RX_OVER Interrupt.
Definition: qm_soc_regs.h:889
qm_mpr_reg_t::mpr_vdata
QM_RW uint32_t mpr_vdata
MPR_VDATA.
Definition: qm_soc_regs.h:1297
DMA_HW_IF_UART_B_TX
UART_B_TX.
Definition: qm_soc_regs.h:1496
pic_timer_reg_pad_t
PIC timer register structure.
Definition: qm_soc_regs.h:1335
qm_adc_reg_t::adc_seq1
QM_RW uint32_t adc_seq1
ADC Channel Sequence Table Entry 1.
Definition: qm_soc_regs.h:1071
qm_scss_info_reg_t::fs
QM_RW uint32_t fs
Flash Size Register.
Definition: qm_soc_regs.h:360
qm_dma_int_reg_t::raw_tfr_low
QM_RW uint32_t raw_tfr_low
RawTfr.
Definition: qm_soc_regs.h:1584
qm_i2c_reg_t::ic_ss_scl_lcnt
QM_RW uint32_t ic_ss_scl_lcnt
Standard Speed Clock SCL Low Count.
Definition: qm_soc_regs.h:873
qm_i2c_reg_t::ic_sda_setup
QM_RW uint32_t ic_sda_setup
SDA Setup.
Definition: qm_soc_regs.h:908
qm_dma_int_reg_t::status_block_high
QM_RW uint32_t status_block_high
StatusBlock.
Definition: qm_soc_regs.h:1597
qm_rtc_reg_t::rtc_ccr
QM_RW uint32_t rtc_ccr
Counter Control Register.
Definition: qm_soc_regs.h:825
qm_dma_chan_reg_t::src_stat_addr_high
QM_RW uint32_t src_stat_addr_high
SSTATAR.
Definition: qm_soc_regs.h:1521
qm_adc_t
qm_adc_t
Number of ADC controllers.
Definition: qm_soc_regs.h:1066
qm_uart_reg_t::dlf
QM_RW uint32_t dlf
Divisor Latch Fraction.
Definition: qm_soc_regs.h:678
qm_dma_misc_reg_t::cfg_high
QM_RW uint32_t cfg_high
DmaCfgReg.
Definition: qm_soc_regs.h:1636
qm_uart_reg_t::lcr
QM_RW uint32_t lcr
Line Control.
Definition: qm_soc_regs.h:663
qm_flash_t
qm_flash_t
Number of Flash controllers.
Definition: qm_soc_regs.h:1141
qm_scss_cmp_reg_t::cmp_ref_sel
QM_RW uint32_t cmp_ref_sel
Comparator reference select.
Definition: qm_soc_regs.h:183
CLK_PERIPH_PWM_REGISTER
PWM Clock Gate Enable.
Definition: qm_soc_regs.h:1378
qm_i2c_reg_t::ic_enable
QM_RW uint32_t ic_enable
Enable.
Definition: qm_soc_regs.h:898
qm_i2c_reg_t::ic_dma_rdlr
QM_RW uint32_t ic_dma_rdlr
I2C Receive Data Level Register.
Definition: qm_soc_regs.h:907
qm_flash_reg_t::flash_wr_ctrl
QM_RW uint32_t flash_wr_ctrl
FLASH_WR_CTRL.
Definition: qm_soc_regs.h:1148
qm_mvic_reg_t::sivr
QM_RW mvic_reg_pad_t sivr
Spurious vector.
Definition: qm_soc_regs.h:1421
qm_dma_int_reg_t::raw_err_low
QM_RW uint32_t raw_err_low
RawErr.
Definition: qm_soc_regs.h:1592
qm_dma_int_reg_t::status_tfr_high
QM_RW uint32_t status_tfr_high
StatusTfr.
Definition: qm_soc_regs.h:1595
QM_DMA_CHANNEL_NUM
Number of DMA channels.
Definition: qm_soc_regs.h:1489
qm_spi_reg_t::ssienr
QM_RW uint32_t ssienr
SSI Enable Register.
Definition: qm_soc_regs.h:715
qm_uart_reg_t::mcr
QM_RW uint32_t mcr
MODEM Control.
Definition: qm_soc_regs.h:664
qm_gpio_reg_t::gpio_swporta_ddr
QM_RW uint32_t gpio_swporta_ddr
Port A Data Direction.
Definition: qm_soc_regs.h:1019
qm_i2c_reg_t::ic_clr_rx_done
QM_RW uint32_t ic_clr_rx_done
Clear RX_DONE Interrupt.
Definition: qm_soc_regs.h:893
qm_i2c_reg_t::ic_tx_tl
QM_RW uint32_t ic_tx_tl
Transmit FIFO Threshold Level.
Definition: qm_soc_regs.h:885
qm_i2c_reg_t::ic_fs_scl_lcnt
QM_RW uint32_t ic_fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
Definition: qm_soc_regs.h:876
QM_FPR_1
FPR 1.
Definition: qm_soc_regs.h:1267
QM_MPR_NUM
Number of Memory Protection Regions.
Definition: qm_soc_regs.h:1291
qm_dma_chan_reg_t::dst_stat_low
QM_RW uint32_t dst_stat_low
DSTAT.
Definition: qm_soc_regs.h:1518
qm_scss_gp_reg_t::wo_sp
QM_RW uint32_t wo_sp
Write-One-to-Set Scratchpad Register.
Definition: qm_soc_regs.h:155
qm_dma_int_reg_t::status_dst_trans_low
QM_RW uint32_t status_dst_trans_low
StatusDstTran.
Definition: qm_soc_regs.h:1600
qm_i2c_reg_t::ic_clr_tx_abrt
QM_RW uint32_t ic_clr_tx_abrt
Clear TX_ABRT Interrupt.
Definition: qm_soc_regs.h:892
qm_scss_peripheral_reg_t::cfg_lock
QM_RW uint32_t cfg_lock
Configuration Lock.
Definition: qm_soc_regs.h:304
qm_i2c_reg_t::ic_data_cmd
QM_RW uint32_t ic_data_cmd
Data Buffer and Command.
Definition: qm_soc_regs.h:869
qm_dma_int_reg_t::mask_src_trans_low
QM_RW uint32_t mask_src_trans_low
MaskSrcTran.
Definition: qm_soc_regs.h:1608
qm_i2c_reg_t::ic_clr_stop_det
QM_RW uint32_t ic_clr_stop_det
Clear STOP_DET Interrupt.
Definition: qm_soc_regs.h:895
CLK_PERIPH_ALL
Quark D2000 peripherals Enable.
Definition: qm_soc_regs.h:1390
qm_spi_reg_t::txoicr
QM_RW uint32_t txoicr
Tx FIFO Overflow Interrupt Clear Register.
Definition: qm_soc_regs.h:728
CLK_PERIPH_RTC_REGISTER
RTC Clock Gate Enable.
Definition: qm_soc_regs.h:1377
QM_DMA_CHANNEL_1
DMA channel id for channel 1.
Definition: qm_soc_regs.h:1488
qm_adc_reg_t::adc_calibration
QM_RW uint32_t adc_calibration
ADC Calibration Data Register.
Definition: qm_soc_regs.h:1082
qm_uart_reg_t
UART register map.
Definition: qm_soc_regs.h:658
qm_scss_pmu_reg_t::rsts
QM_RW uint32_t rsts
Reset Status.
Definition: qm_soc_regs.h:218
qm_uart_reg_t::re_en
QM_RW uint32_t re_en
Receiver Output Enable Register.
Definition: qm_soc_regs.h:675
qm_dma_int_reg_t::mask_dst_trans_high
QM_RW uint32_t mask_dst_trans_high
MaskDstTran.
Definition: qm_soc_regs.h:1611
qm_flash_reg_t::mpr_vdata
QM_RW uint32_t mpr_vdata
MPR Violation Data Value Register.
Definition: qm_soc_regs.h:1156
qm_dma_int_reg_t::mask_err_low
QM_RW uint32_t mask_err_low
MaskErr.
Definition: qm_soc_regs.h:1612
qm_uart_reg_t::det
QM_RW uint32_t det
Driver Output Enable Timing Register.
Definition: qm_soc_regs.h:676
qm_uart_t
qm_uart_t
Number of UART controllers.
Definition: qm_soc_regs.h:655
QM_MPR_0
Memory Protection Region 0.
Definition: qm_soc_regs.h:1287
QM_MPR_3
Memory Protection Region 3.
Definition: qm_soc_regs.h:1290
qm_aonc_reg_t::aonc_cnt
QM_RW uint32_t aonc_cnt
Always-on counter register.
Definition: qm_soc_regs.h:259
qm_uart_reg_t::rbr_thr_dll
QM_RW uint32_t rbr_thr_dll
Rx Buffer/ Tx Holding/ Div Latch Low.
Definition: qm_soc_regs.h:660
qm_gpio_reg_t::gpio_debounce
QM_RW uint32_t gpio_debounce
Debounce Enable.
Definition: qm_soc_regs.h:1027
qm_dma_int_reg_t::clear_tfr_low
QM_RW uint32_t clear_tfr_low
ClearTfr.
Definition: qm_soc_regs.h:1614
CLK_PERIPH_CLK
Peripheral Clock Enable.
Definition: qm_soc_regs.h:1370
qm_rtc_reg_t::rtc_stat
QM_RW uint32_t rtc_stat
Interrupt Status Register.
Definition: qm_soc_regs.h:826
qm_scss_gp_reg_t::gps3
QM_RW uint32_t gps3
General Purpose Sticky Register 3.
Definition: qm_soc_regs.h:148
qm_scss_ccu_reg_t::ccu_gpio_db_clk_ctl
QM_RW uint32_t ccu_gpio_db_clk_ctl
Peripheral Clock Divider Control 1.
Definition: qm_soc_regs.h:42
qm_dma_int_reg_t::mask_tfr_low
QM_RW uint32_t mask_tfr_low
MaskTfr.
Definition: qm_soc_regs.h:1604
qm_pwm_channel_t::loadcount
QM_RW uint32_t loadcount
Load Coun.t.
Definition: qm_soc_regs.h:390
qm_dma_int_reg_t::raw_dst_trans_high
QM_RW uint32_t raw_dst_trans_high
RawDstTran.
Definition: qm_soc_regs.h:1591
CLK_PERIPH_REGISTER
Peripheral Clock Gate Enable.
Definition: qm_soc_regs.h:1369
qm_scss_pmux_reg_t::pmux_slew_lock
QM_RW uint32_t pmux_slew_lock
Pin Mux Slew Rate Lock.
Definition: qm_soc_regs.h:334
qm_gpio_reg_t::gpio_swporta_dr
QM_RW uint32_t gpio_swporta_dr
Port A Data.
Definition: qm_soc_regs.h:1018
qm_dma_int_reg_t::mask_block_high
QM_RW uint32_t mask_block_high
MaskBlock.
Definition: qm_soc_regs.h:1607
QM_FPR_3
FPR 3.
Definition: qm_soc_regs.h:1269
qm_mvic_reg_t
MVIC register map.
Definition: qm_soc_regs.h:1415
qm_scss_pmu_reg_t::p_sts
QM_RW uint32_t p_sts
Processor Status.
Definition: qm_soc_regs.h:215
qm_mvic_reg_t::isr
QM_RW mvic_reg_pad_t isr
In-service.
Definition: qm_soc_regs.h:1423
qm_scss_ccu_reg_t::osc_lock_0
QM_RW uint32_t osc_lock_0
Clocks Lock Register.
Definition: qm_soc_regs.h:50
qm_dma_int_reg_t::status_src_trans_high
QM_RW uint32_t status_src_trans_high
StatusSrcTran.
Definition: qm_soc_regs.h:1599
qm_spi_controllers
qm_spi_reg_t * qm_spi_controllers[QM_SPI_NUM]
Extern qm_spi_reg_t* array declared at qm_soc_regs.h .
Definition: qm_spi.c:66
qm_uart_reg_t::rar
QM_RW uint32_t rar
Receive Address Register.
Definition: qm_soc_regs.h:679
qm_i2c_reg_t::ic_rxflr
QM_RW uint32_t ic_rxflr
Receive FIFO Level.
Definition: qm_soc_regs.h:901
qm_wdt_reg_t::wdt_comp_type
QM_RW uint32_t wdt_comp_type
Component Type Register.
Definition: qm_soc_regs.h:484
qm_pwm_reg_t
PWM / Timer register map.
Definition: qm_soc_regs.h:398
qm_spi_reg_t::mwcr
QM_RW uint32_t mwcr
Microwire Control Register.
Definition: qm_soc_regs.h:716
qm_scss_ccu_reg_t::osc0_stat1
QM_RW uint32_t osc0_stat1
Hybrid Oscillator status 1.
Definition: qm_soc_regs.h:32
qm_i2c_reg_t::ic_clr_tx_over
QM_RW uint32_t ic_clr_tx_over
Clear TX_OVER Interrupt.
Definition: qm_soc_regs.h:890
qm_dma_chan_reg_t::src_sg_low
QM_RW uint32_t src_sg_low
SGR.
Definition: qm_soc_regs.h:1526
qm_i2c_reg_t::ic_raw_intr_stat
QM_RW uint32_t ic_raw_intr_stat
Raw Interrupt Status.
Definition: qm_soc_regs.h:883
CLK_PERIPH_SPI_M0
SPI Master 0 Clock Enable.
Definition: qm_soc_regs.h:1373
qm_dma_int_reg_t::clear_block_low
QM_RW uint32_t clear_block_low
ClearBlock.
Definition: qm_soc_regs.h:1616
qm_scss_pmu_reg_t::aon_vr
QM_RW uint32_t aon_vr
AON Voltage Regulator.
Definition: qm_soc_regs.h:211
qm_aonc_reg_t::aonpt_cnt
QM_RW uint32_t aonpt_cnt
Always-on periodic timer.
Definition: qm_soc_regs.h:261
qm_dma_chan_reg_t::src_stat_high
QM_RW uint32_t src_stat_high
SSTAT.
Definition: qm_soc_regs.h:1517
CLK_PERIPH_WDT_REGISTER
Watchdog Clock Enable.
Definition: qm_soc_regs.h:1376
qm_dma_misc_reg_t
DMA miscellaneous register map.
Definition: qm_soc_regs.h:1634
qm_rtc_reg_t::rtc_rstat
QM_RW uint32_t rtc_rstat
Interrupt Raw Status Register.
Definition: qm_soc_regs.h:827
qm_scss_info_reg_t
Information register map.
Definition: qm_soc_regs.h:357
qm_gpio_reg_t::gpio_intstatus
QM_RW uint32_t gpio_intstatus
Interrupt Status.
Definition: qm_soc_regs.h:1025
qm_dma_int_reg_t::clear_dst_trans_low
QM_RW uint32_t clear_dst_trans_low
ClearDstTran.
Definition: qm_soc_regs.h:1620
qm_dma_chan_reg_t::dst_stat_addr_high
QM_RW uint32_t dst_stat_addr_high
DSTATAR.
Definition: qm_soc_regs.h:1523
qm_pic_timer_reg_t::timer_icr
QM_RW pic_timer_reg_pad_t timer_icr
Initial Count Register.
Definition: qm_soc_regs.h:1344
qm_flash_reg_t::tmg_ctrl
QM_RW uint32_t tmg_ctrl
TMG_CTRL.
Definition: qm_soc_regs.h:1145
CLK_PERIPH_GPIO_REGISTER
GPIO Clock Gate Enable.
Definition: qm_soc_regs.h:1379
qm_adc_reg_t::adc_seq7
QM_RW uint32_t adc_seq7
ADC Channel Sequence Table Entry 7.
Definition: qm_soc_regs.h:1077
qm_scss_ccu_reg_t
System Core register map.
Definition: qm_soc_regs.h:30
qm_flash_reg_t::ctrl
QM_RW uint32_t ctrl
CTRL.
Definition: qm_soc_regs.h:1151
qm_scss_pmu_reg_t::pm_wait
QM_RW uint32_t pm_wait
Power Management Wait.
Definition: qm_soc_regs.h:213
qm_dma_misc_reg_t::id_low
QM_RW uint32_t id_low
DmaIdReg.
Definition: qm_soc_regs.h:1639
qm_dma_int_reg_t::clear_tfr_high
QM_RW uint32_t clear_tfr_high
ClearTfr.
Definition: qm_soc_regs.h:1615
qm_dma_chan_reg_t::dst_sg_high
QM_RW uint32_t dst_sg_high
DSR.
Definition: qm_soc_regs.h:1529
DMA_HW_IF_UART_A_RX
UART_A_RX.
Definition: qm_soc_regs.h:1495
qm_rtc_reg_t
RTC register map.
Definition: qm_soc_regs.h:821
qm_rtc_reg_t::rtc_ccvr
QM_RW uint32_t rtc_ccvr
Current Counter Value Register.
Definition: qm_soc_regs.h:822
qm_uart_reg_t::dmasa
QM_RW uint32_t dmasa
DMA Software Acknowledge.
Definition: qm_soc_regs.h:672
qm_scss_cmp_reg_t::cmp_pwr
QM_RW uint32_t cmp_pwr
Comparator power enable register.
Definition: qm_soc_regs.h:186
qm_dma_chan_reg_t::src_stat_addr_low
QM_RW uint32_t src_stat_addr_low
SSTATAR.
Definition: qm_soc_regs.h:1520
qm_aonc_reg_t
Always-on Counter Controller register map.
Definition: qm_soc_regs.h:258
qm_mvic_reg_t::icr
QM_RW mvic_reg_pad_t icr
Timer initial count.
Definition: qm_soc_regs.h:1429
qm_rtc_reg_t::rtc_comp_version
QM_RW uint32_t rtc_comp_version
End of Interrupt Register.
Definition: qm_soc_regs.h:829
CLK_PERIPH_ADC_REGISTER
ADC Clock Gate Enable.
Definition: qm_soc_regs.h:1389
qm_flash_reg_t::rom_wr_data
QM_RW uint32_t rom_wr_data
ROM_WR_DATA.
Definition: qm_soc_regs.h:1147
qm_scss_cmp_reg_t::cmp_stat_clr
QM_RW uint32_t cmp_stat_clr
Comparator clear register.
Definition: qm_soc_regs.h:188
qm_uart_reg_t::lcr_ext
QM_RW uint32_t lcr_ext
Line Extended Control Register.
Definition: qm_soc_regs.h:681
qm_adc_reg_t::adc_seq0
QM_RW uint32_t adc_seq0
ADC Channel Sequence Table Entry 0.
Definition: qm_soc_regs.h:1070
qm_wdt_reg_t::wdt_comp_param_2
QM_RW uint32_t wdt_comp_param_2
Component Parameters.
Definition: qm_soc_regs.h:480
qm_i2c_reg_t::ic_sda_hold
QM_RW uint32_t ic_sda_hold
SDA Hold.
Definition: qm_soc_regs.h:902
qm_scss_gp_reg_t
General Purpose register map.
Definition: qm_soc_regs.h:144
qm_flash_reg_t::rom_wr_ctrl
QM_RW uint32_t rom_wr_ctrl
ROM_WR_CTRL.
Definition: qm_soc_regs.h:1146
qm_rtc_reg_t::rtc_eoi
QM_RW uint32_t rtc_eoi
End of Interrupt Register.
Definition: qm_soc_regs.h:828
qm_dma_int_reg_t::mask_err_high
QM_RW uint32_t mask_err_high
MaskErr.
Definition: qm_soc_regs.h:1613
qm_scss_ccu_reg_t::ccu_lp_clk_ctl
QM_RW uint32_t ccu_lp_clk_ctl
System Low Power Clock Control.
Definition: qm_soc_regs.h:46
qm_spi_reg_t::rxflr
QM_RW uint32_t rxflr
Receive FIFO Level Register.
Definition: qm_soc_regs.h:722
qm_uart_reg_t::tcr
QM_RW uint32_t tcr
Transceiver Control Register.
Definition: qm_soc_regs.h:673
qm_i2c_reg_t::ic_dma_cr
QM_RW uint32_t ic_dma_cr
SDA Setup.
Definition: qm_soc_regs.h:905
qm_dma_int_reg_t::status_int_high
QM_RW uint32_t status_int_high
StatusInt.
Definition: qm_soc_regs.h:1625
qm_pwm_reg_t::timersintstatus
QM_RW uint32_t timersintstatus
Timers Interrupt Status.
Definition: qm_soc_regs.h:401
qm_dma_chan_reg_t::llp_low
QM_RW uint32_t llp_low
LLP.
Definition: qm_soc_regs.h:1512
qm_spi_reg_t::rxuicr
QM_RW uint32_t rxuicr
Rx FIFO Underflow Interrupt Clear Register.
Definition: qm_soc_regs.h:732
qm_dma_misc_reg_t::chan_en_low
QM_RW uint32_t chan_en_low
ChEnReg.
Definition: qm_soc_regs.h:1637
qm_dma_misc_reg_t::cfg_low
QM_RW uint32_t cfg_low
DmaCfgReg.
Definition: qm_soc_regs.h:1635
qm_spi_reg_t
SPI register map.
Definition: qm_soc_regs.h:712
qm_spi_t
qm_spi_t
Number of SPI controllers.
Definition: qm_soc_regs.h:709
qm_spi_reg_t::risr
QM_RW uint32_t risr
Raw Interrupt Status Register.
Definition: qm_soc_regs.h:726
qm_i2c_reg_t::ic_fs_scl_hcnt
QM_RW uint32_t ic_fs_scl_hcnt
Fast Speed Clock SCL High Count.
Definition: qm_soc_regs.h:874
qm_pwm_channel_t::currentvalue
QM_RW uint32_t currentvalue
Current Value.
Definition: qm_soc_regs.h:391
qm_gpio_reg_t::gpio_ext_porta
QM_RW uint32_t gpio_ext_porta
Port A External Port.
Definition: qm_soc_regs.h:1029
qm_adc_reg_t::adc_sample
QM_RW uint32_t adc_sample
ADC Sample Register.
Definition: qm_soc_regs.h:1081
qm_flash_reg_t
Flash register map.
Definition: qm_soc_regs.h:1144
qm_pwm_reg_t::timersrawintstatus
QM_RW uint32_t timersrawintstatus
Timers Raw Interrupt Status.
Definition: qm_soc_regs.h:403
qm_uart_reg_t::htx
QM_RW uint32_t htx
Halt Transmission.
Definition: qm_soc_regs.h:671
qm_rtc_t
qm_rtc_t
Number of RTC controllers.
Definition: qm_soc_regs.h:818
qm_mvic_reg_t::ppr
QM_RW mvic_reg_pad_t ppr
Processor priority.
Definition: qm_soc_regs.h:1418
qm_scss_ccu_reg_t::osc0_cfg1
QM_RW uint32_t osc0_cfg1
Hybrid Oscillator configuration 1.
Definition: qm_soc_regs.h:33
qm_uart_reg_t::lsr
QM_RW uint32_t lsr
Line Status.
Definition: qm_soc_regs.h:665
qm_scss_ccu_reg_t::ccu_ext_clock_ctl
QM_RW uint32_t ccu_ext_clock_ctl
External Clock Control Register.
Definition: qm_soc_regs.h:44
qm_dma_misc_reg_t::id_high
QM_RW uint32_t id_high
DmaIdReg.
Definition: qm_soc_regs.h:1640
qm_i2c_reg_t::ic_comp_type
QM_RW uint32_t ic_comp_type
Component Type.
Definition: qm_soc_regs.h:918
qm_gpio_reg_t
GPIO register map.
Definition: qm_soc_regs.h:1017
qm_pic_timer_reg_t::lvttimer
QM_RW pic_timer_reg_pad_t lvttimer
Local Vector Table Timer.
Definition: qm_soc_regs.h:1342
qm_dma_int_reg_t::mask_block_low
QM_RW uint32_t mask_block_low
MaskBlock.
Definition: qm_soc_regs.h:1606
qm_rtc_reg_t::rtc_cmr
QM_RW uint32_t rtc_cmr
Current Match Register.
Definition: qm_soc_regs.h:823
qm_i2c_reg_t::ic_clr_start_det
QM_RW uint32_t ic_clr_start_det
Clear START_DET Interrupt.
Definition: qm_soc_regs.h:896
qm_gpio_reg_t::gpio_intmask
QM_RW uint32_t gpio_intmask
Interrupt Mask.
Definition: qm_soc_regs.h:1022
qm_mvic_reg_t::lvttimer
QM_RW mvic_reg_pad_t lvttimer
Timer vector.
Definition: qm_soc_regs.h:1427
qm_scss_ccu_reg_t::soc_ctrl
QM_RW uint32_t soc_ctrl
SoC Control Register.
Definition: qm_soc_regs.h:51
CLK_PERIPH_ADC
ADC Clock Enable.
Definition: qm_soc_regs.h:1388
QM_DMA_0
DMA controller id.
Definition: qm_soc_regs.h:1481
qm_aonc_reg_t::aonpt_stat
QM_RW uint32_t aonpt_stat
Always-on periodic timer status register.
Definition: qm_soc_regs.h:263
qm_spi_reg_t::ssi_comp_version
QM_RW uint32_t ssi_comp_version
coreKit Version ID register.
Definition: qm_soc_regs.h:739
qm_wdt_reg_t::wdt_comp_param_1
QM_RW uint32_t wdt_comp_param_1
Component Parameters Register 1.
Definition: qm_soc_regs.h:482
qm_adc_reg_t::adc_intr_enable
QM_RW uint32_t adc_intr_enable
ADC Interrupt Enable Register.
Definition: qm_soc_regs.h:1080
qm_scss_gp_reg_t::wo_st
QM_RW uint32_t wo_st
Write-One-to-Set Sticky Scratchpad Register.
Definition: qm_soc_regs.h:157
qm_flash_reg_t::mpr_vsts
QM_RW uint32_t mpr_vsts
Protection Status Register.
Definition: qm_soc_regs.h:1155
qm_dma_chan_reg_t::ctrl_high
QM_RW uint32_t ctrl_high
CTL.
Definition: qm_soc_regs.h:1515
qm_spi_reg_t::msticr
QM_RW uint32_t msticr
Multi-Master Interrupt Clear Register.
Definition: qm_soc_regs.h:733
qm_dma_int_reg_t::raw_block_high
QM_RW uint32_t raw_block_high
RawBlock.
Definition: qm_soc_regs.h:1587
qm_wdt_reg_t::wdt_eoi
QM_RW uint32_t wdt_eoi
Interrupt Clear Register.
Definition: qm_soc_regs.h:476
qm_gpio
qm_gpio_reg_t * qm_gpio[QM_GPIO_NUM]
GPIO register block.
Definition: qm_gpio.c:14
CLK_PERIPH_UARTB_REGISTER
UARTB Clock Gate Enable.
Definition: qm_soc_regs.h:1385
qm_gpio_reg_t::gpio_int_polarity
QM_RW uint32_t gpio_int_polarity
Interrupt Polarity.
Definition: qm_soc_regs.h:1024
qm_dma_int_reg_t::raw_dst_trans_low
QM_RW uint32_t raw_dst_trans_low
RawDstTran.
Definition: qm_soc_regs.h:1590
qm_wdt_reg_t::wdt_crr
QM_RW uint32_t wdt_crr
Current Restart Register.
Definition: qm_soc_regs.h:474
qm_scss_gp_reg_t::gp3
QM_RW uint32_t gp3
General Purpose Scratchpad Register 3.
Definition: qm_soc_regs.h:153
qm_i2c_reg_t::ic_ss_scl_hcnt
QM_RW uint32_t ic_ss_scl_hcnt
Standard Speed Clock SCL High Count.
Definition: qm_soc_regs.h:871
qm_wdt_reg_t::wdt_cr
QM_RW uint32_t wdt_cr
Control Register.
Definition: qm_soc_regs.h:471
qm_i2c_reg_t::ic_clr_activity
QM_RW uint32_t ic_clr_activity
Clear ACTIVITY Interrupt.
Definition: qm_soc_regs.h:894
qm_pwm_id_t
qm_pwm_id_t
PWM ID type.
Definition: qm_soc_regs.h:386
qm_wdt_reg_t::wdt_comp_param_4
QM_RW uint32_t wdt_comp_param_4
Component Parameters.
Definition: qm_soc_regs.h:478
qm_dma_int_reg_t::status_err_low
QM_RW uint32_t status_err_low
StatusErr.
Definition: qm_soc_regs.h:1602
qm_uart_reg_t::ier_dlh
QM_RW uint32_t ier_dlh
Interrupt Enable / Divisor Latch High.
Definition: qm_soc_regs.h:661
DMA_HW_IF_UART_A_TX
UART_A_TX.
Definition: qm_soc_regs.h:1494
qm_i2c_reg_t::ic_dma_tdlr
QM_RW uint32_t ic_dma_tdlr
DMA Transmit Data Level Register.
Definition: qm_soc_regs.h:906
qm_aonc_reg_t::aonpt_cfg
QM_RW uint32_t aonpt_cfg
Always-on periodic timer configuration register.
Definition: qm_soc_regs.h:266
qm_flash_reg_t::flash_wr_data
QM_RW uint32_t flash_wr_data
FLASH_WR_DATA.
Definition: qm_soc_regs.h:1149
qm_scss_gp_reg_t::gps0
QM_RW uint32_t gps0
General Purpose Sticky Register 0.
Definition: qm_soc_regs.h:145
qm_spi_reg_t::idr
QM_RW uint32_t idr
Identification Register.
Definition: qm_soc_regs.h:738
DMA_HW_IF_I2C_MASTER_0_RX
I2C_Master_0_RX.
Definition: qm_soc_regs.h:1503
qm_scss_cmp_reg_t
Comparator register map.
Definition: qm_soc_regs.h:181
qm_flash_reg_t::mpr_wr_cfg
QM_RW uint32_t mpr_wr_cfg
Flash Write Protection Control Register.
Definition: qm_soc_regs.h:1154
qm_i2c_reg_t::ic_sar
QM_RW uint32_t ic_sar
Slave Address.
Definition: qm_soc_regs.h:867
qm_i2c_reg_t::ic_hs_maddr
QM_RW uint32_t ic_hs_maddr
High Speed Master ID.
Definition: qm_soc_regs.h:868
QM_DMA_NUM
Number of DMA controllers.
Definition: qm_soc_regs.h:1482
QM_DMA_CHANNEL_0
DMA channel id for channel 0.
Definition: qm_soc_regs.h:1487
DMA_HW_IF_I2C_MASTER_0_TX
I2C_Master_0_TX.
Definition: qm_soc_regs.h:1502
CLK_PERIPH_I2C_M0_REGISTER
I2C Master 0 Clock Gate Enable.
Definition: qm_soc_regs.h:1386
qm_scss_pmux_reg_t::pmux_sel_0_lock
QM_RW uint32_t pmux_sel_0_lock
Pin Mux Select Lock 0.
Definition: qm_soc_regs.h:335
qm_spi_reg_t::sr
QM_RW uint32_t sr
Status Register.
Definition: qm_soc_regs.h:723
qm_dma_chan_reg_t::dst_stat_high
QM_RW uint32_t dst_stat_high
DSTAT.
Definition: qm_soc_regs.h:1519
CLK_PERIPH_SPI_S_REGISTER
SPI Slave Clock Gate Enable.
Definition: qm_soc_regs.h:1382
qm_dma_chan_reg_t::sar_low
QM_RW uint32_t sar_low
SAR.
Definition: qm_soc_regs.h:1508
qm_dma_int_reg_t::clear_block_high
QM_RW uint32_t clear_block_high
ClearBlock.
Definition: qm_soc_regs.h:1617
qm_gpio_reg_t::gpio_porta_eoi
QM_RW uint32_t gpio_porta_eoi
Clear Interrupt.
Definition: qm_soc_regs.h:1028
qm_i2c_reg_t::ic_clr_gen_call
QM_RW uint32_t ic_clr_gen_call
Clear GEN_CALL Interrupt.
Definition: qm_soc_regs.h:897
CLK_PERIPH_I2C_M0
I2C Master 0 Clock Enable.
Definition: qm_soc_regs.h:1371
qm_dma_int_reg_t::raw_src_trans_high
QM_RW uint32_t raw_src_trans_high
RawSrcTran.
Definition: qm_soc_regs.h:1589
qm_dma_chan_reg_t::dar_low
QM_RW uint32_t dar_low
DAR.
Definition: qm_soc_regs.h:1510
qm_spi_reg_t::imr
QM_RW uint32_t imr
Interrupt Mask Register.
Definition: qm_soc_regs.h:724
qm_pwm_channel_t::controlreg
QM_RW uint32_t controlreg
Control.
Definition: qm_soc_regs.h:392
qm_pwm_reg_t::timerscompversion
QM_RW uint32_t timerscompversion
Timers Component Version.
Definition: qm_soc_regs.h:404
qm_mvic_reg_t::ccr
QM_RW mvic_reg_pad_t ccr
Timer current count.
Definition: qm_soc_regs.h:1430
qm_uart_reg_t::usr
QM_RW uint32_t usr
UART Status.
Definition: qm_soc_regs.h:669
qm_adc_reg_t::adc_seq2
QM_RW uint32_t adc_seq2
ADC Channel Sequence Table Entry 2.
Definition: qm_soc_regs.h:1072
QM_MPR_2
Memory Protection Region 2.
Definition: qm_soc_regs.h:1289
qm_wdt_reg_t::wdt_ccvr
QM_RW uint32_t wdt_ccvr
Current Counter Value Register.
Definition: qm_soc_regs.h:473
qm_dma_chan_reg_t::cfg_high
QM_RW uint32_t cfg_high
CFG.
Definition: qm_soc_regs.h:1525
qm_pic_timer_reg_t::timer_ccr
QM_RW pic_timer_reg_pad_t timer_ccr
Current Count Register.
Definition: qm_soc_regs.h:1345
qm_dma_int_reg_t::status_tfr_low
QM_RW uint32_t status_tfr_low
StatusTfr.
Definition: qm_soc_regs.h:1594
qm_dma_misc_reg_t::chan_en_high
QM_RW uint32_t chan_en_high
ChEnReg.
Definition: qm_soc_regs.h:1638
qm_spi_reg_t::rxoicr
QM_RW uint32_t rxoicr
Rx FIFO Overflow Interrupt Clear Register.
Definition: qm_soc_regs.h:730
qm_scss_info_reg_t::dotps
QM_RW uint32_t dotps
Data OTP Size Register.
Definition: qm_soc_regs.h:363
qm_adc_reg_t::adc_seq5
QM_RW uint32_t adc_seq5
ADC Channel Sequence Table Entry 5.
Definition: qm_soc_regs.h:1075
qm_mpr_reg_t::mpr_vsts
QM_RW uint32_t mpr_vsts
MPR_VSTS.
Definition: qm_soc_regs.h:1298
qm_dma_chan_reg_t::dst_sg_low
QM_RW uint32_t dst_sg_low
DSR.
Definition: qm_soc_regs.h:1528
qm_spi_reg_t::ser
QM_RW uint32_t ser
Slave Enable Register.
Definition: qm_soc_regs.h:717
qm_dma_int_reg_t::clear_err_high
QM_RW uint32_t clear_err_high
ClearErr.
Definition: qm_soc_regs.h:1623
CLK_PERIPH_SPI_M0_REGISTER
SPI Master 0 Clock Gate Enable.
Definition: qm_soc_regs.h:1380
qm_uart_reg_t::iir_fcr
QM_RW uint32_t iir_fcr
Interrupt Identification / FIFO Control.
Definition: qm_soc_regs.h:662
qm_i2c_reg_t::ic_intr_mask
QM_RW uint32_t ic_intr_mask
Interrupt Mask.
Definition: qm_soc_regs.h:882
qm_dma_int_reg_t::raw_tfr_high
QM_RW uint32_t raw_tfr_high
RawTfr.
Definition: qm_soc_regs.h:1585
qm_gpio_t
qm_gpio_t
Number of GPIO controllers.
Definition: qm_soc_regs.h:1014
qm_fpr_id_t
qm_fpr_id_t
FPR register map.
Definition: qm_soc_regs.h:1265
qm_adc_reg_t::adc_seq4
QM_RW uint32_t adc_seq4
ADC Channel Sequence Table Entry 4.
Definition: qm_soc_regs.h:1074
mvic_reg_pad_t
MVIC register structure.
Definition: qm_soc_regs.h:1409
qm_dma_chan_reg_t
DMA channel register map.
Definition: qm_soc_regs.h:1507
qm_i2c_t
qm_i2c_t
Number of I2C controllers.
Definition: qm_soc_regs.h:861
qm_gpio_reg_t::gpio_ls_sync
QM_RW uint32_t gpio_ls_sync
Synchronization Level.
Definition: qm_soc_regs.h:1031
qm_pic_timer_reg_t
PIC timer register map.
Definition: qm_soc_regs.h:1341
qm_scss_pmux_reg_t::pmux_in_en_lock
QM_RW uint32_t pmux_in_en_lock
Pin Mux Slew Rate Lock.
Definition: qm_soc_regs.h:337
qm_adc_reg_t::adc_cmd
QM_RW uint32_t adc_cmd
ADC Command Register.
Definition: qm_soc_regs.h:1078
qm_i2c
qm_i2c_reg_t * qm_i2c[QM_I2C_NUM]
I2C register block.
Definition: qm_i2c.c:20
qm_i2c_reg_t::ic_tx_abrt_source
QM_RW uint32_t ic_tx_abrt_source
Transmit Abort Source.
Definition: qm_soc_regs.h:903
qm_scss_cmp_reg_t::cmp_en
QM_RW uint32_t cmp_en
Comparator enable.
Definition: qm_soc_regs.h:182
qm_scss_pmu_reg_t::rstc
QM_RW uint32_t rstc
Reset Control.
Definition: qm_soc_regs.h:217
qm_pwm_channel_t::eoi
QM_RW uint32_t eoi
End Of Interrupt.
Definition: qm_soc_regs.h:393
qm_spi_reg_t::ctrlr0
QM_RW uint32_t ctrlr0
Control Register 0.
Definition: qm_soc_regs.h:713
DMA_HW_IF_SPI_MASTER_0_TX
SPI_Master_0_TX.
Definition: qm_soc_regs.h:1498
qm_uart_reg_t::scr
QM_RW uint32_t scr
Scratchpad.
Definition: qm_soc_regs.h:667
qm_gpio_reg_t::gpio_ver_id_code
QM_RW uint32_t gpio_ver_id_code
GPIO Component Version.
Definition: qm_soc_regs.h:1034
qm_scss_ccu_reg_t::ccu_periph_clk_div_ctl0
QM_RW uint32_t ccu_periph_clk_div_ctl0
Peripheral Clock Divider Control 0.
Definition: qm_soc_regs.h:40
qm_mpr_reg_t
Memory Protection Region register map.
Definition: qm_soc_regs.h:1295
qm_scss_pmu_reg_t::pm_lock
QM_RW uint32_t pm_lock
Power Management Lock.
Definition: qm_soc_regs.h:220
qm_scss_gp_reg_t::gps1
QM_RW uint32_t gps1
General Purpose Sticky Register 1.
Definition: qm_soc_regs.h:146
qm_gpio_reg_t::gpio_raw_intstatus
QM_RW uint32_t gpio_raw_intstatus
Raw Interrupt Status.
Definition: qm_soc_regs.h:1026
DMA_HW_IF_SPI_SLAVE_RX
SPI_Slave_RX.
Definition: qm_soc_regs.h:1501
qm_gpio_reg_t::gpio_inttype_level
QM_RW uint32_t gpio_inttype_level
Interrupt Type.
Definition: qm_soc_regs.h:1023
qm_uart_reg_t::msr
QM_RW uint32_t msr
MODEM Status.
Definition: qm_soc_regs.h:666
qm_pwm_t
qm_pwm_t
Number of PWM / Timer controllers.
Definition: qm_soc_regs.h:383
qm_wdt_reg_t::wdt_comp_param_3
QM_RW uint32_t wdt_comp_param_3
Component Parameters.
Definition: qm_soc_regs.h:479
qm_scss_info_reg_t::rev
QM_RW uint32_t rev
Revision Register.
Definition: qm_soc_regs.h:359
qm_scss_gp_reg_t::gps2
QM_RW uint32_t gps2
General Purpose Sticky Register 2.
Definition: qm_soc_regs.h:147
qm_dma_int_reg_t::raw_err_high
QM_RW uint32_t raw_err_high
RawErr.
Definition: qm_soc_regs.h:1593
qm_scss_ccu_reg_t::ccu_periph_clk_gate_ctl
QM_RW uint32_t ccu_periph_clk_gate_ctl
Peripheral Clock Gate Control.
Definition: qm_soc_regs.h:38
qm_dma_int_reg_t::status_block_low
QM_RW uint32_t status_block_low
StatusBlock.
Definition: qm_soc_regs.h:1596
qm_uart_reg_t::tat
QM_RW uint32_t tat
TurnAround Timing Register.
Definition: qm_soc_regs.h:677
qm_dma_chan_reg_t::llp_high
QM_RW uint32_t llp_high
LLP.
Definition: qm_soc_regs.h:1513
qm_mvic_reg_t::irr
QM_RW mvic_reg_pad_t irr
Interrupt request.
Definition: qm_soc_regs.h:1425
qm_wdt_reg_t::wdt_comp_param_5
QM_RW uint32_t wdt_comp_param_5
Component Parameters.
Definition: qm_soc_regs.h:477
qm_dma_int_reg_t::status_dst_trans_high
QM_RW uint32_t status_dst_trans_high
StatusDstTran.
Definition: qm_soc_regs.h:1601
QM_MPR_1
Memory Protection Region 1.
Definition: qm_soc_regs.h:1288
qm_scss_cmp_reg_t::cmp_ref_pol
QM_RW uint32_t cmp_ref_pol
Comparator reference polarity select register.
Definition: qm_soc_regs.h:185
qm_scss_pmux_reg_t::pmux_pullup_lock
QM_RW uint32_t pmux_pullup_lock
Pin Mux Pullup Lock.
Definition: qm_soc_regs.h:333
qm_dma_channel_id_t
qm_dma_channel_id_t
DMA channel IDs.
Definition: qm_soc_regs.h:1486
qm_i2c_reg_t::ic_hs_scl_lcnt
QM_RW uint32_t ic_hs_scl_lcnt
High Speed I2C Clock SCL Low Count.
Definition: qm_soc_regs.h:880
clk_periph_t
clk_periph_t
Peripheral clock register map.
Definition: qm_soc_regs.h:1368
qm_scss_pmu_reg_t
Power Management register map.
Definition: qm_soc_regs.h:210
qm_gpio_reg_t::gpio_id_code
QM_RW uint32_t gpio_id_code
GPIO ID code.
Definition: qm_soc_regs.h:1032
qm_spi_reg_t::txflr
QM_RW uint32_t txflr
Transmit FIFO Level Register.
Definition: qm_soc_regs.h:721
qm_adc_reg_t
ADC register map.
Definition: qm_soc_regs.h:1069
qm_dma_handshake_interface_t
qm_dma_handshake_interface_t
DMA hardware handshake interfaces.
Definition: qm_soc_regs.h:1493
qm_dma_int_reg_t::status_int_low
QM_RW uint32_t status_int_low
StatusInt.
Definition: qm_soc_regs.h:1624
qm_scss_gp_reg_t::gp0
QM_RW uint32_t gp0
General Purpose Scratchpad Register 0.
Definition: qm_soc_regs.h:150
qm_mvic_reg_t::tpr
QM_RW mvic_reg_pad_t tpr
Task priority.
Definition: qm_soc_regs.h:1416
qm_i2c_reg_t::ic_enable_status
QM_RW uint32_t ic_enable_status
Enable Status.
Definition: qm_soc_regs.h:910
qm_wdt_reg_t::wdt_stat
QM_RW uint32_t wdt_stat
Interrupt Status Register.
Definition: qm_soc_regs.h:475
qm_dma_misc_reg_t::test_low
QM_RW uint32_t test_low
DmaTestReg.
Definition: qm_soc_regs.h:1641
qm_scss_ccu_reg_t::osc1_cfg0
QM_RW uint32_t osc1_cfg0
RTC Oscillator Configuration 0.
Definition: qm_soc_regs.h:35
qm_pwm_channel_t
PWM / Timer channel register map.
Definition: qm_soc_regs.h:389
qm_dma_int_reg_t::mask_src_trans_high
QM_RW uint32_t mask_src_trans_high
MaskSrcTran.
Definition: qm_soc_regs.h:1609
CLK_PERIPH_SPI_S
SPI Slave Clock Enable.
Definition: qm_soc_regs.h:1372
qm_dma_int_reg_t::clear_src_trans_low
QM_RW uint32_t clear_src_trans_low
ClearSrcTran.
Definition: qm_soc_regs.h:1618
qm_pwm_reg_t::timerseoi
QM_RW uint32_t timerseoi
Timers End Of Interrupt.
Definition: qm_soc_regs.h:402
qm_wdt_t
qm_wdt_t
Number of WDT controllers.
Definition: qm_soc_regs.h:467
qm_dma_int_reg_t::mask_dst_trans_low
QM_RW uint32_t mask_dst_trans_low
MaskDstTran.
Definition: qm_soc_regs.h:1610
qm_spi_reg_t::dmatdlr
QM_RW uint32_t dmatdlr
DMA Transmit Data Level.
Definition: qm_soc_regs.h:736
qm_i2c_reg_t::ic_con
QM_RW uint32_t ic_con
Control Register.
Definition: qm_soc_regs.h:865
qm_i2c_reg_t::ic_comp_version
QM_RW uint32_t ic_comp_version
Component Version.
Definition: qm_soc_regs.h:917
qm_i2c_reg_t::ic_tar
QM_RW uint32_t ic_tar
Master Target Address.
Definition: qm_soc_regs.h:866
qm_wdt_reg_t
Watchdog timer register map.
Definition: qm_soc_regs.h:470
qm_i2c_reg_t::ic_clr_restart_det
QM_RW uint32_t ic_clr_restart_det
clear the RESTART_DET interrupt.
Definition: qm_soc_regs.h:914
qm_i2c_reg_t::ic_rx_tl
QM_RW uint32_t ic_rx_tl
Receive FIFO Threshold Level.
Definition: qm_soc_regs.h:884
qm_i2c_reg_t::ic_ack_general_call
QM_RW uint32_t ic_ack_general_call
General Call Ack.
Definition: qm_soc_regs.h:909
qm_dma_int_reg_t::clear_src_trans_high
QM_RW uint32_t clear_src_trans_high
ClearSrcTran.
Definition: qm_soc_regs.h:1619
qm_aonc_reg_t::aonc_cfg
QM_RW uint32_t aonc_cfg
Always-on counter enable.
Definition: qm_soc_regs.h:260
qm_scss_info_reg_t::rs
QM_RW uint32_t rs
RAM Size Register.
Definition: qm_soc_regs.h:361
qm_scss_peripheral_reg_t
Peripheral Registers register map.
Definition: qm_soc_regs.h:301
qm_spi_reg_t::icr
QM_RW uint32_t icr
Interrupt Clear Register.
Definition: qm_soc_regs.h:734
qm_i2c_reg_t::ic_txflr
QM_RW uint32_t ic_txflr
Transmit FIFO Level.
Definition: qm_soc_regs.h:900
qm_dma_int_reg_t::clear_err_low
QM_RW uint32_t clear_err_low
ClearErr.
Definition: qm_soc_regs.h:1622
qm_dma_misc_reg_t::test_high
QM_RW uint32_t test_high
DmaTestReg.
Definition: qm_soc_regs.h:1642
qm_scss_peripheral_reg_t::periph_cfg0
QM_RW uint32_t periph_cfg0
Peripheral Configuration.
Definition: qm_soc_regs.h:302
qm_i2c_reg_t::ic_clr_rd_req
QM_RW uint32_t ic_clr_rd_req
Clear RD_REQ Interrupt.
Definition: qm_soc_regs.h:891
qm_aonc_t
qm_aonc_t
Number of Always-on counter controllers.
Definition: qm_soc_regs.h:255
qm_dma_chan_reg_t::sar_high
QM_RW uint32_t sar_high
SAR.
Definition: qm_soc_regs.h:1509
qm_spi_reg_t::rxftlr
QM_RW uint32_t rxftlr
Receive FIFO Threshold Level.
Definition: qm_soc_regs.h:720
CLK_PERIPH_GPIO_INTERRUPT
GPIO Interrupt Clock Enable.
Definition: qm_soc_regs.h:1374
qm_gpio_reg_t::gpio_int_bothedge
QM_RW uint32_t gpio_int_bothedge
Interrupt both edge type.
Definition: qm_soc_regs.h:1033