Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_ss_i2c.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __QM_SS_I2C_H__
6 #define __QM_SS_I2C_H__
7
8 #include "qm_common.h"
9 #include "qm_sensor_regs.h"
10
11 /**
12 * I2C driver for Sensor Subsystem.
13 *
14 * @defgroup groupSSI2C SS I2C
15 * @{
16 */
17
18 /* Standard speed High/low period for 50% duty cycle bus clock (in nanosecs). */
19 #define QM_I2C_SS_50_DC_NS (5000)
20 /* Fast Speed High/low period for 50% duty cycle bus clock (in nanosecs). */
21 #define QM_I2C_FS_50_DC_NS (1250)
22 /* High Speed High/low period for 50% duty cycle bus clock (in nanosecs). */
23 #define QM_I2C_FSP_50_DC_NS (500)
24
25 /*
26 * Standard speed minimum low period to meet timing requirements (in nanosecs).
27 */
28 #define QM_I2C_MIN_SS_NS (4700)
29 /* Fast speed minimum low period to meet timing requirements (in nanosecs). */
30 #define QM_I2C_MIN_FS_NS (1300)
31 /* High speed minimum low period to meet timing requirements (in nanosecs). */
32 #define QM_I2C_MIN_FSP_NS (500)
33
34 /**
35 * QM SS I2C addressing type.
36 */
37 typedef enum {
38 QM_SS_I2C_7_BIT = 0, /**< 7-bit mode. */
39 QM_SS_I2C_10_BIT /**< 10-bit mode. */
40 } qm_ss_i2c_addr_t;
41
42 /**
43 * QM SS I2C speed type.
44 */
45 typedef enum {
46 QM_SS_I2C_SPEED_STD = 1, /**< Standard mode (100 Kbps). */
47 QM_SS_I2C_SPEED_FAST = 2, /**< Fast mode (400 Kbps). */
48 #if HAS_SS_I2C_FAST_PLUS_SPEED
49 QM_SS_I2C_SPEED_FAST_PLUS = 3 /**< Fast plus mode (1 Mbps). */
50 #endif /* HAS_SS_I2C_FAST_PLUS_SPEED */
51 } qm_ss_i2c_speed_t;
52
53 /**
54 * QM SS I2C status type.
55 */
56 typedef enum {
57 QM_SS_I2C_IDLE = 0, /**< Controller idle. */
58 QM_SS_I2C_TX_ABRT_7B_ADDR_NOACK = BIT(0), /**< 7-bit address noack. */
59 QM_SS_I2C_TX_ABRT_10ADDR1_NOACK = BIT(1), /**< 10-bit address noack. */
60 QM_SS_I2C_TX_ABRT_10ADDR2_NOACK = BIT(2), /**< 10-bit address noack. */
61 QM_SS_I2C_TX_ABRT_TXDATA_NOACK = BIT(3), /**< Tx data noack. */
62 QM_SS_I2C_TX_ABRT_GCALL_NOACK = BIT(4), /**< General call noack. */
63
64 /**< General call configured as read. */
65 QM_SS_I2C_TX_ABRT_GCALL_READ = BIT(5),
66 QM_SS_I2C_TX_ABRT_SBYTE_ACKDET = BIT(7), /**< Start ACK. */
67 QM_SS_I2C_TX_ABRT_NORSTRT = BIT(9), /**< Restart disabled. */
68 QM_SS_I2C_TX_ABRT_10B_RD_NORSTRT = BIT(10), /**< Restart disabled. */
69 QM_SS_I2C_TX_ABRT_MASTER_DIS = BIT(11), /**< Master disabled. */
70 QM_SS_I2C_TX_ARB_LOST = BIT(12), /**< Master lost arbitration. */
71
72 /**< Slave flush tx FIFO. */
73 QM_SS_I2C_TX_ABRT_SLVFLUSH_TXFIFO = BIT(13),
74 QM_SS_I2C_TX_ABRT_SLV_ARBLOST = BIT(14), /**< Slave lost bus. */
75 QM_SS_I2C_TX_ABRT_SLVRD_INTX = BIT(15), /**< Slave read completion. */
76 QM_SS_I2C_TX_ABRT_USER_ABRT = BIT(16), /**< User abort. */
77 QM_SS_I2C_BUSY = BIT(17), /**< Controller busy. */
78 QM_SS_I2C_TX_ABORT = BIT(18), /**< Tx abort. */
79 QM_SS_I2C_TX_OVER = BIT(19), /**< Tx overflow. */
80 QM_SS_I2C_RX_OVER = BIT(20), /**< Rx overflow. */
81 QM_SS_I2C_RX_UNDER = BIT(21) /**< Rx underflow. */
82 } qm_ss_i2c_status_t;
83
84 /**
85 * QM SS I2C configuration type.
86 */
87 typedef struct {
88 qm_ss_i2c_speed_t speed; /**< Standard, fast or fast plus mode. */
89 qm_ss_i2c_addr_t address_mode; /**< 7 or 10 bit addressing. */
90 } qm_ss_i2c_config_t;
91
92 /**
93 * QM SS I2C transfer type.
94 * - if tx_len is 0: perform receive-only transaction.
95 * - if rx_len is 0: perform transmit-only transaction.
96 * - both tx and rx len not 0: perform a transmit-then-receive
97 * combined transaction.
98 */
99 typedef struct {
100 uint8_t *tx; /**< Write data. */
101 uint32_t tx_len; /**< Write data length. */
102 uint8_t *rx; /**< Read data. */
103 uint32_t rx_len; /**< Read buffer length. */
104 bool stop; /**< Generate master STOP. */
105
106 /**
107 * User callback.
108 *
109 * @param[in] data User defined data.
110 * @param[in] rc 0 on success.
111 * Negative @ref errno for possible error codes.
112 * @param[in] status I2C status.
113 * @param[in] len Length of the transfer if successful, 0 otherwise.
114 */
115 void (*callback)(void *data, int rc, qm_ss_i2c_status_t status,
116 uint32_t len);
117 void *callback_data; /**< User callback data. */
118 } qm_ss_i2c_transfer_t;
119
120 /**
121 * Set SS I2C configuration.
122 *
123 * @param[in] i2c Which I2C to set the configuration of.
124 * @param[in] cfg I2C configuration. This must not be NULL.
125 *
126 * @return Standard errno return type for QMSI.
127 * @retval 0 on success.
128 * @retval Negative @ref errno for possible error codes.
129 */
130 int qm_ss_i2c_set_config(const qm_ss_i2c_t i2c,
131 const qm_ss_i2c_config_t *const cfg);
132
133 /**
134 * Set I2C speed.
135 *
136 * Fine tune SS I2C clock speed.
137 * This will set the SCL low count and the SCL hi count cycles
138 * to achieve any required speed.
139 *
140 * @param[in] i2c I2C index.
141 * @param[in] speed Bus speed (Standard or Fast. Fast includes Fast+ mode).
142 * @param[in] lo_cnt SCL low count.
143 * @param[in] hi_cnt SCL high count.
144 *
145 * @return Standard errno return type for QMSI.
146 * @retval 0 on success.
147 * @retval Negative @ref errno for possible error codes.
148 */
149 int qm_ss_i2c_set_speed(const qm_ss_i2c_t i2c, const qm_ss_i2c_speed_t speed,
150 const uint16_t lo_cnt, const uint16_t hi_cnt);
151
152 /**
153 * Retrieve SS I2C status.
154 *
155 * @param[in] i2c Which I2C to read the status of.
156 * @param[out] status Get I2C status. This must not be NULL.
157 *
158 * @return Standard errno return type for QMSI.
159 * @retval 0 on success.
160 * @retval Negative @ref errno for possible error codes.
161 */
162 int qm_ss_i2c_get_status(const qm_ss_i2c_t i2c,
163 qm_ss_i2c_status_t *const status);
164
165 /**
166 * Master write on I2C.
167 *
168 * Perform a master write on the SS I2C bus.
169 * This is a blocking synchronous call.
170 *
171 * @param[in] i2c Which I2C to write to.
172 * @param[in] slave_addr Address of slave to write to.
173 * @param[in] data Pre-allocated buffer of data to write.
174 * This must not be NULL.
175 * @param[in] len Length of data to write.
176 * @param[in] stop Generate a STOP condition at the end of tx.
177 * @param[out] status Get I2C status.
178 *
179 * @return Standard errno return type for QMSI.
180 * @retval 0 on success.
181 * @retval Negative @ref errno for possible error codes.
182 */
183 int qm_ss_i2c_master_write(const qm_ss_i2c_t i2c, const uint16_t slave_addr,
184 const uint8_t *const data, uint32_t len,
185 const bool stop, qm_ss_i2c_status_t *const status);
186
187 /**
188 * Master read of I2C.
189 *
190 * Perform a single byte master read from the SS I2C. This is a blocking call.
191 *
192 * @param[in] i2c Which I2C to read from.
193 * @param[in] slave_addr Address of slave device to read from.
194 * @param[out] data Pre-allocated buffer to populate with data.
195 * This must not be NULL.
196 * @param[in] len Length of data to read from slave.
197 * @param[in] stop Generate a STOP condition at the end of rx.
198 * @param[out] status Get I2C status.
199 *
200 * @return Standard errno return type for QMSI.
201 * @retval 0 on success.
202 * @retval Negative @ref errno for possible error codes.
203 */
204 int qm_ss_i2c_master_read(const qm_ss_i2c_t i2c, const uint16_t slave_addr,
205 uint8_t *const data, uint32_t len, const bool stop,
206 qm_ss_i2c_status_t *const status);
207
208 /**
209 * Interrupt based master transfer on I2C.
210 *
211 * Perform an interrupt based master transfer on the SS I2C bus. The function
212 * will replenish/empty TX/RX FIFOs on I2C empty/full interrupts.
213 *
214 * @param[in] i2c Which I2C to transfer from.
215 * @param[in] xfer Transfer structure includes write / read data and length,
216 * user callback function and the callback context.
217 * The structure must not be NULL and must be kept valid until
218 * the transfer is complete.
219 * @param[in] slave_addr Address of slave to transfer data with.
220 *
221 * @return Standard errno return type for QMSI.
222 * @retval 0 on success.
223 * @retval Negative @ref errno for possible error codes.
224 */
225 int qm_ss_i2c_master_irq_transfer(const qm_ss_i2c_t i2c,
226 const qm_ss_i2c_transfer_t *const xfer,
227 const uint16_t slave_addr);
228
229 /**
230 * Terminate I2C IRQ/DMA transfer.
231 *
232 * Terminate the current IRQ transfer on the SS I2C bus.
233 * This will cause the user callback to be called with status
234 * QM_SS_I2C_TX_ABRT_USER_ABRT.
235 *
236 * @param[in] i2c I2C register block pointer.
237 *
238 * @return Standard errno return type for QMSI.
239 * @retval 0 on success.
240 * @retval Negative @ref errno for possible error codes.
241 */
242 int qm_ss_i2c_irq_transfer_terminate(const qm_ss_i2c_t i2c);
243
244 /**
245 * Save SS I2C context.
246 *
247 * Saves the configuration of the specified SS I2C peripheral
248 * before entering sleep. The slave operations need to be disabled before
249 * being able to save the context as otherwise we could be interrupted by
250 * an I2C transfer while saving registers.
251 *
252 * @param[in] i2c I2C port index.
253 * @param[out] ctx I2C context structure. This must not be NULL.
254 *
255 * @return Standard errno return type for QMSI.
256 * @retval 0 on success.
257 * @retval Negative @ref errno for possible error codes.
258 */
259 int qm_ss_i2c_save_context(const qm_ss_i2c_t i2c,
260 qm_ss_i2c_context_t *const ctx);
261
262 /**
263 * Restore SS I2C context.
264 *
265 * Restore the configuration of the specified SS I2C peripheral
266 * after exiting sleep.
267 *
268 * @param[in] i2c I2C port index.
269 * @param[in] ctx I2C context structure. This must not be NULL.
270 *
271 * @return Standard errno return type for QMSI.
272 * @retval 0 on success.
273 * @retval Negative @ref errno for possible error codes.
274 */
275 int qm_ss_i2c_restore_context(const qm_ss_i2c_t i2c,
276 const qm_ss_i2c_context_t *const ctx);
277
278 /**
279 * @}
280 */
281
282 #endif /* __QM_SS_I2C_H__ */
QM_SS_I2C_SPEED_FAST
Fast mode (400 Kbps).
Definition: qm_ss_i2c.h:47
qm_ss_i2c_speed_t
qm_ss_i2c_speed_t
QM SS I2C speed type.
Definition: qm_ss_i2c.h:45
QM_SS_I2C_TX_ABRT_NORSTRT
Restart disabled.
Definition: qm_ss_i2c.h:67
QM_SS_I2C_TX_ABRT_MASTER_DIS
Master disabled.
Definition: qm_ss_i2c.h:69
QM_SS_I2C_TX_ABRT_TXDATA_NOACK
Tx data noack.
Definition: qm_ss_i2c.h:61
qm_ss_i2c_transfer_t
QM SS I2C transfer type.
Definition: qm_ss_i2c.h:99
qm_ss_i2c_master_write
int qm_ss_i2c_master_write(const qm_ss_i2c_t i2c, const uint16_t slave_addr, const uint8_t *const data, uint32_t len, const bool stop, qm_ss_i2c_status_t *const status)
Master write on I2C.
Definition: qm_ss_i2c.c:526
qm_ss_i2c_master_irq_transfer
int qm_ss_i2c_master_irq_transfer(const qm_ss_i2c_t i2c, const qm_ss_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Interrupt based master transfer on I2C.
Definition: qm_ss_i2c.c:675
qm_ss_i2c_transfer_t::rx
uint8_t * rx
Read data.
Definition: qm_ss_i2c.h:102
qm_ss_i2c_save_context
int qm_ss_i2c_save_context(const qm_ss_i2c_t i2c, qm_ss_i2c_context_t *const ctx)
Save SS I2C context.
Definition: qm_ss_i2c.c:782
QM_SS_I2C_IDLE
Controller idle.
Definition: qm_ss_i2c.h:57
QM_SS_I2C_TX_ABORT
Tx abort.
Definition: qm_ss_i2c.h:78
QM_SS_I2C_TX_ARB_LOST
Master lost arbitration.
Definition: qm_ss_i2c.h:70
QM_SS_I2C_TX_ABRT_SLVRD_INTX
Slave read completion.
Definition: qm_ss_i2c.h:75
qm_ss_i2c_t
qm_ss_i2c_t
Sensor Subsystem I2C.
Definition: qm_sensor_regs.h:532
qm_ss_i2c_transfer_t::tx
uint8_t * tx
Write data.
Definition: qm_ss_i2c.h:100
qm_ss_i2c_transfer_t::rx_len
uint32_t rx_len
Read buffer length.
Definition: qm_ss_i2c.h:103
QM_SS_I2C_TX_ABRT_7B_ADDR_NOACK
7-bit address noack.
Definition: qm_ss_i2c.h:58
QM_SS_I2C_TX_ABRT_USER_ABRT
User abort.
Definition: qm_ss_i2c.h:76
QM_SS_I2C_TX_ABRT_GCALL_NOACK
General call noack.
Definition: qm_ss_i2c.h:62
QM_SS_I2C_7_BIT
7-bit mode.
Definition: qm_ss_i2c.h:38
qm_ss_i2c_get_status
int qm_ss_i2c_get_status(const qm_ss_i2c_t i2c, qm_ss_i2c_status_t *const status)
Retrieve SS I2C status.
Definition: qm_ss_i2c.c:505
QM_SS_I2C_TX_ABRT_10ADDR2_NOACK
10-bit address noack.
Definition: qm_ss_i2c.h:60
QM_SS_I2C_SPEED_STD
Standard mode (100 Kbps).
Definition: qm_ss_i2c.h:46
QM_SS_I2C_TX_OVER
Tx overflow.
Definition: qm_ss_i2c.h:79
QM_SS_I2C_BUSY
Controller busy.
Definition: qm_ss_i2c.h:77
qm_ss_i2c_transfer_t::stop
bool stop
Generate master STOP.
Definition: qm_ss_i2c.h:104
qm_ss_i2c_status_t
qm_ss_i2c_status_t
QM SS I2C status type.
Definition: qm_ss_i2c.h:56
QM_SS_I2C_TX_ABRT_SBYTE_ACKDET
Start ACK.
Definition: qm_ss_i2c.h:66
qm_ss_i2c_transfer_t::callback_data
void * callback_data
User callback data.
Definition: qm_ss_i2c.h:117
QM_SS_I2C_TX_ABRT_10ADDR1_NOACK
10-bit address noack.
Definition: qm_ss_i2c.h:59
qm_ss_i2c_master_read
int qm_ss_i2c_master_read(const qm_ss_i2c_t i2c, const uint16_t slave_addr, uint8_t *const data, uint32_t len, const bool stop, qm_ss_i2c_status_t *const status)
Master read of I2C.
Definition: qm_ss_i2c.c:598
QM_SS_I2C_RX_OVER
Rx overflow.
Definition: qm_ss_i2c.h:80
QM_SS_I2C_TX_ABRT_10B_RD_NORSTRT
Restart disabled.
Definition: qm_ss_i2c.h:68
qm_ss_i2c_set_speed
int qm_ss_i2c_set_speed(const qm_ss_i2c_t i2c, const qm_ss_i2c_speed_t speed, const uint16_t lo_cnt, const uint16_t hi_cnt)
Set I2C speed.
Definition: qm_ss_i2c.c:450
qm_ss_i2c_addr_t
qm_ss_i2c_addr_t
QM SS I2C addressing type.
Definition: qm_ss_i2c.h:37
qm_ss_i2c_config_t::speed
qm_ss_i2c_speed_t speed
Standard, fast or fast plus mode.
Definition: qm_ss_i2c.h:88
qm_ss_i2c_config_t
QM SS I2C configuration type.
Definition: qm_ss_i2c.h:87
qm_ss_i2c_restore_context
int qm_ss_i2c_restore_context(const qm_ss_i2c_t i2c, const qm_ss_i2c_context_t *const ctx)
Restore SS I2C context.
Definition: qm_ss_i2c.c:799
QM_SS_I2C_TX_ABRT_SLV_ARBLOST
Slave lost bus.
Definition: qm_ss_i2c.h:74
qm_ss_i2c_set_config
int qm_ss_i2c_set_config(const qm_ss_i2c_t i2c, const qm_ss_i2c_config_t *const cfg)
Set SS I2C configuration.
Definition: qm_ss_i2c.c:347
qm_ss_i2c_context_t
SS I2C context type.
Definition: qm_sensor_regs.h:235
QM_SS_I2C_10_BIT
10-bit mode.
Definition: qm_ss_i2c.h:39
qm_ss_i2c_transfer_t::tx_len
uint32_t tx_len
Write data length.
Definition: qm_ss_i2c.h:101
QM_SS_I2C_RX_UNDER
Rx underflow.
Definition: qm_ss_i2c.h:81
QM_SS_I2C_SPEED_FAST_PLUS
Fast plus mode (1 Mbps).
Definition: qm_ss_i2c.h:49
qm_ss_i2c_irq_transfer_terminate
int qm_ss_i2c_irq_transfer_terminate(const qm_ss_i2c_t i2c)
Terminate I2C IRQ/DMA transfer.
Definition: qm_ss_i2c.c:761
qm_ss_i2c_config_t::address_mode
qm_ss_i2c_addr_t address_mode
7 or 10 bit addressing.
Definition: qm_ss_i2c.h:89