Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_soc_regs.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __REGISTERS_H__
6 #define __REGISTERS_H__
7
8 #include "qm_common.h"
9 #include "qm_soc_interrupts.h"
10 #include "qm_interrupt_router_regs.h"
11 #include "flash_layout.h"
12
13 /**
14 * Quark SE SoC Registers.
15 *
16 * @defgroup groupQUARKSESEREG SoC Registers (SE)
17 * @{
18 */
19
20 #define QUARK_SE (1)
21 #define HAS_4_TIMERS (1)
22 #define HAS_AON_GPIO (1)
23 #define HAS_MAILBOX (1)
24 #define HAS_USB (1)
25
26 #if !defined(QM_SENSOR)
27 #define HAS_APIC (1)
28 #endif
29
30 /**
31 * @name System Core
32 * @{
33 */
34
35 /** System Core register map. */
36 typedef struct {
37 QM_RW uint32_t osc0_cfg0; /**< Hybrid Oscillator Configuration 0. */
38 QM_RW uint32_t osc0_stat1; /**< Hybrid Oscillator status 1. */
39 QM_RW uint32_t osc0_cfg1; /**< Hybrid Oscillator configuration 1. */
40 QM_RW uint32_t osc1_stat0; /**< RTC Oscillator status 0. */
41 QM_RW uint32_t osc1_cfg0; /**< RTC Oscillator Configuration 0. */
42 QM_RW uint32_t usb_pll_cfg0; /**< USB Phase lock look configuration. */
43 QM_RW uint32_t
44 ccu_periph_clk_gate_ctl; /**< Peripheral Clock Gate Control. */
45 QM_RW uint32_t
46 ccu_periph_clk_div_ctl0; /**< Peripheral Clock Divider Control. 0 */
47 QM_RW uint32_t
48 ccu_gpio_db_clk_ctl; /**< Peripheral Clock Divider Control 1. */
49 QM_RW uint32_t
50 ccu_ext_clock_ctl; /**< External Clock Control Register. */
51 /** Sensor Subsystem peripheral clock gate control. */
52 QM_RW uint32_t ccu_ss_periph_clk_gate_ctl;
53 QM_RW uint32_t ccu_lp_clk_ctl; /**< System Low Power Clock Control. */
54 QM_RW uint32_t reserved;
55 QM_RW uint32_t ccu_mlayer_ahb_ctl; /**< AHB Control Register. */
56 QM_RW uint32_t ccu_sys_clk_ctl; /**< System Clock Control Register. */
57 QM_RW uint32_t osc_lock_0; /**< Clocks Lock Register. */
58 } qm_scss_ccu_reg_t;
59
60 #if (UNIT_TEST)
61 qm_scss_ccu_reg_t test_scss_ccu;
62 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)(&test_scss_ccu))
63
64 #else
65 #define QM_SCSS_CCU_BASE (0xB0800000)
66 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)QM_SCSS_CCU_BASE)
67 #endif
68
69 /* Hybrid oscillator output select select (0=Silicon, 1=Crystal) */
70 #define QM_OSC0_MODE_SEL BIT(3)
71 #define QM_OSC0_PD BIT(2)
72 #define QM_OSC1_PD BIT(1)
73
74 /* Enable Crystal oscillator. */
75 #define QM_OSC0_EN_CRYSTAL BIT(0)
76
77 /* Crystal oscillator parameters. */
78 #define OSC0_CFG1_OSC0_FADJ_XTAL_MASK (0x000F0000)
79 #define OSC0_CFG1_OSC0_FADJ_XTAL_OFFS (16)
80 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_MASK (0x00600000)
81 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_OFFS (21)
82
83 /* Silicon Oscillator parameters. */
84 #define OSC0_CFG1_FTRIMOTP_MASK (0x3FF00000)
85 #define OSC0_CFG1_FTRIMOTP_OFFS (20)
86 #define OSC0_CFG1_SI_FREQ_SEL_MASK (0x00000300)
87 #define OSC0_CFG1_SI_FREQ_SEL_OFFS (8)
88
89 #define QM_OSC0_MODE_SEL BIT(3)
90 #define QM_OSC0_LOCK_SI BIT(0)
91 #define QM_OSC0_LOCK_XTAL BIT(1)
92 #define QM_OSC0_EN_SI_OSC BIT(1)
93
94 #define QM_SI_OSC_1V2_MODE BIT(0)
95
96 /* Peripheral clock divider control. */
97 #define QM_CCU_PERIPH_PCLK_DIV_OFFSET (1)
98 #define QM_CCU_PERIPH_PCLK_DIV_EN BIT(0)
99
100 /* Clock enable / disable register. */
101 #define QM_CCU_MLAYER_AHB_CTL (REG_VAL(0xB0800034))
102
103 /* System clock control */
104 #define QM_CCU_SYS_CLK_SEL BIT(0)
105 #define QM_SCSS_CCU_SYS_CLK_SEL BIT(0)
106 #define QM_SCSS_CCU_C2_LP_EN BIT(1)
107 #define QM_SCSS_CCU_SS_LPS_EN BIT(0)
108 #define QM_CCU_RTC_CLK_EN BIT(1)
109 #define QM_CCU_RTC_CLK_DIV_EN BIT(2)
110 #define QM_CCU_SYS_CLK_DIV_EN BIT(7)
111 #define QM_CCU_SYS_CLK_DIV_MASK (0x00000300)
112
113 #define QM_OSC0_SI_FREQ_SEL_DEF_MASK (0xFFFFFCFF)
114 #define QM_CCU_GPIO_DB_DIV_OFFSET (2)
115 #define QM_CCU_GPIO_DB_CLK_DIV_EN BIT(1)
116 #define QM_CCU_GPIO_DB_CLK_EN BIT(0)
117 #define QM_CCU_RTC_CLK_DIV_OFFSET (3)
118 #define QM_CCU_SYS_CLK_DIV_OFFSET (8)
119 #define QM_CCU_DMA_CLK_EN BIT(6)
120
121 /** @} */
122
123 /**
124 * @name General Purpose
125 * @{
126 */
127
128 /** General Purpose register map. */
129 typedef struct {
130 QM_RW uint32_t gps0; /**< General Purpose Sticky Register 0 */
131 QM_RW uint32_t gps1; /**< General Purpose Sticky Register 1 */
132 QM_RW uint32_t gps2; /**< General Purpose Sticky Register 2 */
133 QM_RW uint32_t gps3; /**< General Purpose Sticky Register 3 */
134 QM_RW uint32_t reserved;
135 QM_RW uint32_t gp0; /**< General Purpose Scratchpad Register 0 */
136 QM_RW uint32_t gp1; /**< General Purpose Scratchpad Register 1 */
137 QM_RW uint32_t gp2; /**< General Purpose Scratchpad Register 2 */
138 QM_RW uint32_t gp3; /**< General Purpose Scratchpad Register 3 */
139 QM_RW uint32_t reserved1;
140 QM_RW uint32_t id; /**< Identification Register */
141 QM_RW uint32_t rev; /**< Revision Register */
142 QM_RW uint32_t wo_sp; /**< Write-One-to-Set Scratchpad Register */
143 QM_RW uint32_t
144 wo_st; /**< Write-One-to-Set Sticky Scratchpad Register */
145 } qm_scss_gp_reg_t;
146
147 #if (UNIT_TEST)
148 qm_scss_gp_reg_t test_scss_gp;
149 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)(&test_scss_gp))
150
151 #else
152 #define QM_SCSS_GP_BASE (0xB0800100)
153 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)QM_SCSS_GP_BASE)
154 #endif
155
156 /* The GPS0 register usage. */
157 #define QM_GPS0_BIT_FM (0) /**< Start Firmware Manager. */
158 #define QM_GPS0_BIT_X86_WAKEUP (1) /**< Lakemont core reset type. */
159 #define QM_GPS0_BIT_SENSOR_WAKEUP (2) /**< Sensor core reset type. */
160
161 /** @} */
162
163 /**
164 * @name Memory Control
165 * @{
166 */
167
168 /** Memory Control register map. */
169 typedef struct {
170 QM_RW uint32_t mem_ctrl; /**< Memory control */
171 } qm_scss_mem_reg_t;
172
173 #if (UNIT_TEST)
174 qm_scss_mem_reg_t test_scss_mem;
175 #define QM_SCSS_MEM ((qm_scss_mem_reg_t *)(&test_scss_mem))
176
177 #else
178 #define QM_SCSS_MEM_BASE (0xB0800200)
179 #define QM_SCSS_MEM ((qm_scss_mem_reg_t *)QM_SCSS_MEM_BASE)
180 #endif
181
182 /** @} */
183
184 /**
185 * @name Comparator
186 * @{
187 */
188
189 /** Comparator register map. */
190 typedef struct {
191 QM_RW uint32_t cmp_en; /**< Comparator enable. */
192 QM_RW uint32_t cmp_ref_sel; /**< Comparator reference select. */
193 QM_RW uint32_t
194 cmp_ref_pol; /**< Comparator reference polarity select register. */
195 QM_RW uint32_t cmp_pwr; /**< Comparator power enable register. */
196 QM_RW uint32_t reserved[6];
197 QM_RW uint32_t cmp_stat_clr; /**< Comparator clear register. */
198 } qm_scss_cmp_reg_t;
199
200 #if (UNIT_TEST)
201 qm_scss_cmp_reg_t test_scss_cmp;
202 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)(&test_scss_cmp))
203
204 #else
205 #define QM_SCSS_CMP_BASE (0xB0800300)
206 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)QM_SCSS_CMP_BASE)
207 #endif
208
209 #define QM_AC_HP_COMPARATORS_MASK (0x7FFC0)
210
211 /** @} */
212
213 /**
214 * @name APIC
215 * @{
216 */
217
218 typedef struct {
219 QM_RW uint32_t reg;
220 QM_RW uint32_t pad[3];
221 } apic_reg_pad_t;
222
223 /** APIC register block type. */
224 typedef struct {
225 QM_RW apic_reg_pad_t reserved0[2];
226 QM_RW apic_reg_pad_t id; /**< LAPIC ID */
227 QM_RW apic_reg_pad_t version; /**< LAPIC version*/
228 QM_RW apic_reg_pad_t reserved1[4];
229 QM_RW apic_reg_pad_t tpr; /**< Task priority*/
230 QM_RW apic_reg_pad_t apr; /**< Arbitration priority */
231 QM_RW apic_reg_pad_t ppr; /**< Processor priority */
232 QM_RW apic_reg_pad_t eoi; /**< End of interrupt */
233 QM_RW apic_reg_pad_t rrd; /**< Remote read */
234 QM_RW apic_reg_pad_t ldr; /**< Logical destination */
235 QM_RW apic_reg_pad_t dfr; /**< Destination format */
236 QM_RW apic_reg_pad_t svr; /**< Spurious vector */
237 QM_RW apic_reg_pad_t isr[8]; /**< In-service */
238 QM_RW apic_reg_pad_t tmr[8]; /**< Trigger mode */
239 QM_RW apic_reg_pad_t irr[8]; /**< Interrupt request */
240 QM_RW apic_reg_pad_t esr; /**< Error status */
241 QM_RW apic_reg_pad_t reserved2[6];
242 QM_RW apic_reg_pad_t lvtcmci; /**< Corrected Machine Check vector */
243 QM_RW apic_reg_pad_t icr[2]; /**< Interrupt command */
244 QM_RW apic_reg_pad_t lvttimer; /**< Timer vector */
245 QM_RW apic_reg_pad_t lvtts; /**< Thermal sensor vector */
246 QM_RW apic_reg_pad_t lvtpmcr; /**< Perfmon counter vector */
247 QM_RW apic_reg_pad_t lvtlint0; /**< Local interrupt 0 vector */
248 QM_RW apic_reg_pad_t lvtlint1; /**< Local interrupt 1 vector */
249 QM_RW apic_reg_pad_t lvterr; /**< Error vector */
250 QM_RW apic_reg_pad_t timer_icr; /**< Timer initial count */
251 QM_RW apic_reg_pad_t timer_ccr; /**< Timer current count */
252 QM_RW apic_reg_pad_t reserved3[4];
253 QM_RW apic_reg_pad_t timer_dcr; /**< Timer divide configuration */
254 } qm_lapic_reg_t;
255
256 #if (HAS_APIC)
257 /*
258 * The size of IOAPIC redirection table, as returned by _ioapic_get_redtbl_size
259 * function.
260 */
261 #define QM_IOAPIC_NUM_RTES (32)
262
263 /**
264 * IRQ context type.
265 *
266 * Applications should not modify the content.
267 * This structure is only intended to be used by
268 * qm_irq_save_context and qm_irq_restore_context functions.
269 */
270 typedef struct {
271 /** Redirection Table Entries. */
272 uint32_t redtbl_entries[QM_IOAPIC_NUM_RTES];
273 } qm_irq_context_t;
274 #endif
275
276 /**
277 * PIC TIMER context type.
278 *
279 * Applications should not modify the content.
280 * This structure is only intended to be used by the qm_pic_timer_save_context
281 * and qm_pic_timer_restore_context functions.
282 */
283 typedef struct {
284 uint32_t timer_icr; /**< Initial Count Register. */
285 uint32_t timer_dcr; /**< Divide Configuration Register. */
286 uint32_t lvttimer; /**< Timer Entry in Local Vector Table. */
287 } qm_pic_timer_context_t;
288
289 #if (UNIT_TEST)
290 qm_lapic_reg_t test_lapic;
291 #define QM_LAPIC ((qm_lapic_reg_t *)(&test_lapic))
292
293 #else
294 /* Local APIC. */
295 #define QM_LAPIC_BASE (0xFEE00000)
296 #define QM_LAPIC ((qm_lapic_reg_t *)QM_LAPIC_BASE)
297 #endif
298
299 #define QM_INT_CONTROLLER QM_LAPIC
300
301 /*
302 * Quark SE has a HW limitation that prevents a LAPIC EOI from being broadcast
303 * into IOAPIC. To trigger this manually we must write the vector number being
304 * serviced into the IOAPIC EOI register.
305 */
306 #if defined(ENABLE_EXTERNAL_ISR_HANDLING) || defined(QM_SENSOR)
307 #define QM_ISR_EOI(vector)
308 #else
309 #define QM_ISR_EOI(vector) \
310 do { \
311 QM_INT_CONTROLLER->eoi.reg = 0; \
312 QM_IOAPIC->eoi.reg = vector; \
313 } while (0)
314 #endif
315
316 typedef struct {
317 QM_RW apic_reg_pad_t ioregsel; /**< Register selector. */
318 QM_RW apic_reg_pad_t iowin; /**< Register window. */
319 QM_RW apic_reg_pad_t reserved[2];
320 QM_RW apic_reg_pad_t eoi; /**< EOI register. */
321 } qm_ioapic_reg_t;
322
323 #define QM_IOAPIC_REG_VER (0x01) /* IOAPIC version. */
324 #define QM_IOAPIC_REG_REDTBL (0x10) /* Redirection table base. */
325
326 #if (UNIT_TEST)
327 qm_ioapic_reg_t test_ioapic;
328 #define QM_IOAPIC ((qm_ioapic_reg_t *)(&test_ioapic))
329
330 #else
331 /* IO / APIC base address. */
332 #define QM_IOAPIC_BASE (0xFEC00000)
333 #define QM_IOAPIC ((qm_ioapic_reg_t *)QM_IOAPIC_BASE)
334 #endif
335
336 /** @} */
337
338 /**
339 * @name Power Management
340 * @{
341 */
342
343 /** Power Management register map. */
344 typedef struct {
345 QM_RW uint32_t p_lvl2; /**< Processor level 2 */
346 QM_RW uint32_t reserved[4];
347 QM_RW uint32_t pm1c; /**< Power management 1 control */
348 QM_RW uint32_t reserved1[9];
349 QM_RW uint32_t aon_vr; /**< AON Voltage Regulator */
350 QM_RW uint32_t plat3p3_vr; /**< Platform 3p3 voltage regulator */
351 QM_RW uint32_t plat1p8_vr; /**< Platform 1p8 voltage regulator */
352 QM_RW uint32_t host_vr; /**< Host Voltage Regulator */
353 QM_RW uint32_t slp_cfg; /**< Sleeping Configuration */
354 /** Power Management Network (PMNet) Control and Status */
355 QM_RW uint32_t pmnetcs;
356 QM_RW uint32_t pm_wait; /**< Power Management Wait */
357 QM_RW uint32_t reserved2;
358 QM_RW uint32_t p_sts; /**< Processor Status */
359 QM_RW uint32_t reserved3[3];
360 QM_RW uint32_t rstc; /**< Reset Control */
361 QM_RW uint32_t rsts; /**< Reset Status */
362 QM_RW uint32_t reserved4[6];
363 QM_RW uint32_t vr_lock; /**< Voltage regulator lock */
364 QM_RW uint32_t pm_lock; /**< Power Management Lock */
365 } qm_scss_pmu_reg_t;
366
367 #if (UNIT_TEST)
368 qm_scss_pmu_reg_t test_scss_pmu;
369 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)(&test_scss_pmu))
370
371 #else
372 #define QM_SCSS_PMU_BASE (0xB0800504)
373 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)QM_SCSS_PMU_BASE)
374 #endif
375
376 #define QM_SS_CFG_ARC_RUN_REQ_A BIT(24)
377 #define QM_P_STS_HALT_INTERRUPT_REDIRECTION BIT(26)
378 #define QM_P_STS_ARC_HALT BIT(14)
379
380 #define QM_AON_VR_VSEL_MASK (0xFFE0)
381 #define QM_AON_VR_VSEL_1V2 (0x8)
382 #define QM_AON_VR_VSEL_1V35 (0xB)
383 #define QM_AON_VR_VSEL_1V8 (0x10)
384 #define QM_AON_VR_EN BIT(7)
385 #define QM_AON_VR_VSTRB BIT(5)
386
387 #define QM_SCSS_SLP_CFG_LPMODE_EN BIT(8)
388 #define QM_SCSS_SLP_CFG_RTC_DIS BIT(7)
389 #define QM_SCSS_PM1C_SLPEN BIT(13)
390 #define QM_SCSS_HOST_VR_EN BIT(7)
391 #define QM_SCSS_PLAT3P3_VR_EN BIT(7)
392 #define QM_SCSS_PLAT1P8_VR_EN BIT(7)
393 #define QM_SCSS_HOST_VR_VREG_SEL BIT(6)
394 #define QM_SCSS_PLAT3P3_VR_VREG_SEL BIT(6)
395 #define QM_SCSS_PLAT1P8_VR_VREG_SEL BIT(6)
396 #define QM_SCSS_VR_ROK BIT(10)
397 #define QM_SCSS_VR_EN BIT(7)
398 #define QM_SCSS_VR_VREG_SEL BIT(6)
399
400 /** @} */
401
402 /**
403 * @name Sensor Subsystem
404 * @{
405 */
406
407 /** Sensor Subsystem register map. */
408 typedef struct {
409 QM_RW uint32_t ss_cfg; /**< Sensor Subsystem Configuration */
410 QM_RW uint32_t ss_sts; /**< Sensor Subsystem status */
411 } qm_scss_ss_reg_t;
412
413 #if (UNIT_TEST)
414 qm_scss_ss_reg_t test_scss_ss;
415 #define QM_SCSS_SS ((qm_scss_ss_reg_t *)(&test_scss_ss))
416
417 #else
418 #define QM_SCSS_SS_BASE (0xB0800600)
419 #define QM_SCSS_SS ((qm_scss_ss_reg_t *)QM_SCSS_SS_BASE)
420 #endif
421
422 #define QM_SS_STS_HALT_INTERRUPT_REDIRECTION BIT(26)
423
424 /** @} */
425
426 /**
427 * @name Always-on Counters.
428 * @{
429 */
430
431 /** Number of Always-on counter controllers. */
432 typedef enum { QM_AONC_0 = 0, QM_AONC_NUM } qm_aonc_t;
433
434 /** Always-on Counter Controller register map. */
435 typedef struct {
436 QM_RW uint32_t aonc_cnt; /**< Always-on counter register. */
437 QM_RW uint32_t aonc_cfg; /**< Always-on counter enable. */
438 QM_RW uint32_t aonpt_cnt; /**< Always-on periodic timer. */
439 QM_RW uint32_t
440 aonpt_stat; /**< Always-on periodic timer status register. */
441 QM_RW uint32_t aonpt_ctrl; /**< Always-on periodic timer control. */
442 QM_RW uint32_t
443 aonpt_cfg; /**< Always-on periodic timer configuration register. */
444 } qm_aonc_reg_t;
445
446 /* Nothing to save for aonc on Quark SE. */
447 #define qm_aonc_context_t uint8_t
448
449 #define HAS_AONPT_BUSY_BIT (0)
450
451 #define QM_AONC_ENABLE (BIT(0))
452 #define QM_AONC_DISABLE (~QM_AONC_ENABLE)
453
454 #define QM_AONPT_INTERRUPT (BIT(0))
455
456 #define QM_AONPT_CLR (BIT(0))
457 #define QM_AONPT_RST (BIT(1))
458
459 #if (UNIT_TEST)
460
461 qm_aonc_reg_t test_aonc_instance[QM_AONC_NUM];
462 qm_aonc_reg_t *test_aonc[QM_AONC_NUM];
463
464 #define QM_AONC test_aonc
465
466 #else
467 extern qm_aonc_reg_t *qm_aonc[QM_AONC_NUM];
468 #define QM_AONC_0_BASE (0xB0800700)
469 #define QM_AONC qm_aonc
470 #endif
471
472 /** @} */
473
474 /**
475 * @name Peripheral Registers
476 * @{
477 */
478
479 /** Peripheral Registers register map. */
480 typedef struct {
481 QM_RW uint32_t usb_phy_cfg0; /**< USB Configuration */
482 QM_RW uint32_t periph_cfg0; /**< Peripheral Configuration */
483 QM_RW uint32_t reserved[2];
484 QM_RW uint32_t cfg_lock; /**< Configuration Lock */
485 } qm_scss_peripheral_reg_t;
486
487 #if (UNIT_TEST)
488 qm_scss_peripheral_reg_t test_scss_peripheral;
489 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)(&test_scss_peripheral))
490
491 #else
492 #define QM_SCSS_PERIPHERAL_BASE (0xB0800800)
493 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)QM_SCSS_PERIPHERAL_BASE)
494 #endif
495
496 /* SS code protection region Lock bit. */
497 #define QM_SCSS_CFG_LOCK_PROT_RANGE_LOCK BIT(10)
498
499 /** @} */
500
501 /**
502 * @name Pin MUX
503 * @{
504 */
505
506 /** Pin MUX register map. */
507 typedef struct {
508 QM_RW uint32_t pmux_pullup[4]; /**< Pin Mux Pullup */
509 QM_RW uint32_t pmux_slew[4]; /**< Pin Mux Slew Rate */
510 QM_RW uint32_t pmux_in_en[4]; /**< Pin Mux Input Enable */
511 QM_RW uint32_t pmux_sel[5]; /**< Pin Mux Select */
512 QM_RW uint32_t reserved[2];
513 QM_RW uint32_t pmux_pullup_lock; /**< Pin Mux Pullup Lock */
514 QM_RW uint32_t pmux_slew_lock; /**< Pin Mux Slew Rate Lock */
515 QM_RW uint32_t pmux_sel_lock[3]; /**< Pin Mux Select Lock */
516 QM_RW uint32_t pmux_in_en_lock; /**< Pin Mux Slew Rate Lock */
517 } qm_scss_pmux_reg_t;
518
519 #if (UNIT_TEST)
520 qm_scss_pmux_reg_t test_scss_pmux;
521 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)(&test_scss_pmux))
522
523 #else
524 #define QM_SCSS_PMUX_BASE (0xB0800900)
525 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)QM_SCSS_PMUX_BASE)
526 #endif
527
528 /* Pin MUX slew rate registers and settings */
529 #define QM_PMUX_SLEW_4MA_DRIVER (0xFFFFFFFF)
530 #define QM_PMUX_SLEW0 (REG_VAL(0xB0800910))
531 #define QM_PMUX_SLEW1 (REG_VAL(0xB0800914))
532 #define QM_PMUX_SLEW2 (REG_VAL(0xB0800918))
533 #define QM_PMUX_SLEW3 (REG_VAL(0xB080091C))
534
535 /** @} */
536
537 /**
538 * @name ID
539 * @{
540 */
541
542 /** Information register map. */
543 typedef struct {
544 QM_RW uint32_t id;
545 } qm_scss_info_reg_t;
546
547 #if (UNIT_TEST)
548 qm_scss_info_reg_t test_scss_info;
549 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)(&test_scss_info))
550
551 #else
552 #define QM_SCSS_INFO_BASE (0xB0801000)
553 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)QM_SCSS_INFO_BASE)
554 #endif
555
556 /** @} */
557
558 /**
559 * @name Mailbox
560 * @{
561 */
562
563 #define HAS_MAILBOX (1)
564 #define NUM_MAILBOXES (8)
565
566 #define HAS_MAILBOX_LAKEMONT_DEST (1)
567 #define HAS_MAILBOX_SENSOR_SUB_SYSTEM_DEST (1)
568
569 /**
570 * Mailbox MBOX_CH_CTRL_N Mailbox Channel Control Word Register
571 *
572 * 31 RW/1S/V MBOX_CH_CTRL_INT Mailbox Channel Control Word interrupt
573 * 30:0 RW MBOX_CH_CTRL Mailbox Channel Control Word
574 */
575 #define QM_MBOX_CH_CTRL_INT BIT(31)
576 #define QM_MBOX_CH_CTRL_MASK (0x7FFFFFFF)
577 #define QM_MBOX_CH_CTRL_SHIFT (0)
578
579 /*
580 * Mailbox Channel Status MBOX_CH_STS_N
581 *
582 * 31:2 RO reserved
583 * 1 RW/1C/V MBOX_CH_STS_CTRL_INT Mailbox Channel Interrupt Status
584 * - Bit set when message sent, indicates pending interrupt
585 * - Bit set when a mailbox channel interrupt is pending..
586 * - Bit cleared by writing 1
587 * - Bit should be cleared by the receivers isr
588 * 0 RW/1C/V MBOX_CH_STS Mailbox Channel Status
589 * - Bit set when message sent, indicates pending data
590 * - Bit cleared by writing 1
591 * - Bit should be cleared by the receiver after
592 * consuming the message.
593 */
594 #define QM_MBOX_CH_STS_CTRL_INT BIT(1)
595 #define QM_MBOX_CH_STS BIT(0)
596
597 #define QM_MBOX_STATUS_MASK (QM_MBOX_CH_STS | QM_MBOX_CH_STS_CTRL_INT)
598
599 /**
600 * Mailbox MBOX_CHALL_STS Channel Status Bits Register
601 *
602 * 31:16 RO reserved
603 * 15:0 RO/V MBOX_CHALL_STS Channel Status Bits
604 */
605 #define QM_MBOX_CHALL_STS(N) BIT((N * 2))
606 #define QM_MBOX_CHALL_INT_STS(N) BIT((N * 2) + 1)
607
608 /**
609 * Mailbox interrupt routing mask register INT_MAILBOX_MASK
610 *
611 * There is only 1 Mailbox interrupt mask register.
612 * The register contains masks for all 8 mailbox channels.
613 *
614 * Note that the Mailbox interrupt mask register does not follow
615 * the same layout as most other interrupt mask registers in the SCSS.
616 *
617 * Mask bit positions for INT_MAILBOX_MASK are listed here:
618 *
619 * 31:24 RW/P/L INT_MAILBOX_SS_HALT_MASK Mailbox SS Halt interrupt mask
620 * 23:16 RW/P/L INT_MAILBOX_HOST_HALT_MASK Mailbox Host Halt interrupt mask
621 * 15:8 RW/P/L INT_MAILBOX_SS_MASK Mailbox SS interrupt mask
622 * 7:0 RW/P/L INT_MAILBOX_HOST_MASK Mailbox Host interrupt mask
623 */
624 #define QM_MBOX_SS_HALT_MASK_OFFSET (24)
625 #define QM_MBOX_SS_HALT_MASK_MASK (0xFF000000)
626 #define QM_MBOX_HOST_HALT_MASK_OFFSET (16)
627 #define QM_MBOX_HOST_HALT_MASK_MASK (0x00FF0000)
628 #define QM_MBOX_SS_MASK_OFFSET (8)
629 #define QM_MBOX_SS_MASK_MASK (0x0000FF00)
630 #define QM_MBOX_HOST_MASK_OFFSET (0)
631 #define QM_MBOX_HOST_MASK_MASK (0x000000FF)
632
633 /** Mailbox register structure. */
634 typedef struct {
635 QM_RW uint32_t ch_ctrl; /**< Channel Control Word */
636 QM_RW uint32_t ch_data[4]; /**< Channel Payload Data Word 0 */
637 QM_RW uint32_t ch_sts; /**< Channel status */
638 } qm_mailbox_t;
639
640 /** Mailbox register map. */
641 typedef struct {
642 qm_mailbox_t mbox[NUM_MAILBOXES]; /**< 8 Mailboxes */
643 QM_RW uint32_t mbox_chall_sts; /**< All channel status */
644 } qm_mailbox_reg_t;
645
646 #if (UNIT_TEST)
647 qm_mailbox_reg_t test_mailbox;
648 #define QM_MAILBOX ((qm_mailbox_reg_t *)(&test_mailbox))
649
650 #else
651 #define QM_MAILBOX_BASE (0xB0800A00)
652 #define QM_MAILBOX ((qm_mailbox_reg_t *)QM_MAILBOX_BASE)
653 #endif
654
655 /** @} */
656
657 /**
658 * @name PWM / Timer
659 * @{
660 */
661
662 /** Number of PWM / Timer controllers. */
663 typedef enum { QM_PWM_0 = 0, QM_PWM_NUM } qm_pwm_t;
664
665 /** PWM ID type. */
666 typedef enum {
667 QM_PWM_ID_0 = 0,
668 QM_PWM_ID_1,
669 QM_PWM_ID_2,
670 QM_PWM_ID_3,
671 QM_PWM_ID_NUM
672 } qm_pwm_id_t;
673
674 /** PWM / Timer channel register map. */
675 typedef struct {
676 QM_RW uint32_t loadcount; /**< Load Count */
677 QM_RW uint32_t currentvalue; /**< Current Value */
678 QM_RW uint32_t controlreg; /**< Control */
679 QM_RW uint32_t eoi; /**< End Of Interrupt */
680 QM_RW uint32_t intstatus; /**< Interrupt Status */
681 } qm_pwm_channel_t;
682
683 /** PWM / Timer register map. */
684 typedef struct {
685 qm_pwm_channel_t timer[QM_PWM_ID_NUM]; /**< 4 Timers */
686 QM_RW uint32_t reserved[20];
687 QM_RW uint32_t timersintstatus; /**< Timers Interrupt Status */
688 QM_RW uint32_t timerseoi; /**< Timers End Of Interrupt */
689 QM_RW uint32_t timersrawintstatus; /**< Timers Raw Interrupt Status */
690 QM_RW uint32_t timerscompversion; /**< Timers Component Version */
691 QM_RW uint32_t
692 timer_loadcount2[QM_PWM_ID_NUM]; /**< Timer Load Count 2 */
693 } qm_pwm_reg_t;
694
695 /**
696 * PWM context type.
697 *
698 * Applications should not modify the content.
699 * This structure is only intended to be used by
700 * the qm_pwm_save_context and qm_pwm_restore_context functions.
701 */
702 typedef struct {
703 struct {
704 uint32_t loadcount; /**< Load Count 1. */
705 uint32_t loadcount2; /**< Load Count 2. */
706 uint32_t controlreg; /**< Control Register. */
707 } channel[QM_PWM_ID_NUM];
708 } qm_pwm_context_t;
709
710 #if (UNIT_TEST)
711 qm_pwm_reg_t test_pwm_instance[QM_PWM_NUM];
712 qm_pwm_reg_t *test_pwm[QM_PWM_NUM];
713 #define QM_PWM test_pwm
714
715 #else
716 extern qm_pwm_reg_t *qm_pwm[QM_PWM_NUM];
717 /* PWM register base address. */
718 #define QM_PWM_BASE (0xB0000800)
719 /* PWM register block. */
720 #define QM_PWM qm_pwm
721 #endif
722
723 #define PWM_START (1)
724
725 #define QM_PWM_CONF_MODE_MASK (0xA)
726 #define QM_PWM_CONF_INT_EN_MASK (0x4)
727
728 #define QM_PWM_INTERRUPT_MASK_OFFSET (0x2)
729
730 #define NUM_PWM_CONTROLLER_INTERRUPTS (1)
731
732 /**
733 * Timer N Control (TimerNControlReg)
734 *
735 * 31:4 RO reserved
736 * 3 RW Timer PWM
737 * 1 - PWM Mode
738 * 0 - Timer Mode
739 * 2 RW Timer Interrupt Mask, set to 1b to mask interrupt.
740 * 1 RW Timer Mode
741 * 1 - user-defined count mode
742 * 0 - free-running mode
743 * 0 RW Timer Enable
744 * 0 - Disable PWM/Timer
745 * 1 - Enable PWM/Timer
746 */
747
748 #define QM_PWM_TIMERNCONTROLREG_TIMER_ENABLE (BIT(0))
749 #define QM_PWM_TIMERNCONTROLREG_TIMER_MODE (BIT(1))
750 #define QM_PWM_TIMERNCONTROLREG_TIMER_INTERRUPT_MASK (BIT(2))
751 #define QM_PWM_TIMERNCONTROLREG_TIMER_PWM (BIT(3))
752
753 #define QM_PWM_MODE_TIMER_FREE_RUNNING_VALUE (0)
754 #define QM_PWM_MODE_TIMER_COUNT_VALUE (QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
755 #define QM_PWM_MODE_PWM_VALUE \
756 (QM_PWM_TIMERNCONTROLREG_TIMER_PWM | QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
757
758 /** @} */
759
760 /**
761 * @name WDT
762 * @{
763 */
764
765 /** Number of WDT controllers. */
766 typedef enum { QM_WDT_0 = 0, QM_WDT_NUM } qm_wdt_t;
767
768 /** Watchdog timer register map. */
769 typedef struct {
770 QM_RW uint32_t wdt_cr; /**< Control Register */
771 QM_RW uint32_t wdt_torr; /**< Timeout Range Register */
772 QM_RW uint32_t wdt_ccvr; /**< Current Counter Value Register */
773 QM_RW uint32_t wdt_crr; /**< Current Restart Register */
774 QM_RW uint32_t wdt_stat; /**< Interrupt Status Register */
775 QM_RW uint32_t wdt_eoi; /**< Interrupt Clear Register */
776 QM_RW uint32_t wdt_comp_param_5; /**< Component Parameters */
777 QM_RW uint32_t wdt_comp_param_4; /**< Component Parameters */
778 QM_RW uint32_t wdt_comp_param_3; /**< Component Parameters */
779 QM_RW uint32_t wdt_comp_param_2; /**< Component Parameters */
780 QM_RW uint32_t
781 wdt_comp_param_1; /**< Component Parameters Register 1 */
782 QM_RW uint32_t wdt_comp_version; /**< Component Version Register */
783 QM_RW uint32_t wdt_comp_type; /**< Component Type Register */
784 } qm_wdt_reg_t;
785
786 /*
787 * WDT context type.
788 *
789 * Application should not modify the content.
790 * This structure is only intended to be used by the qm_wdt_save_context and
791 * qm_wdt_restore_context functions.
792 */
793 typedef struct {
794 uint32_t wdt_cr; /**< Control Register. */
795 uint32_t wdt_torr; /**< Timeout Range Register. */
796 } qm_wdt_context_t;
797
798 #if (UNIT_TEST)
799 qm_wdt_reg_t test_wdt_instance[QM_WDT_NUM];
800 qm_wdt_reg_t *test_wdt[QM_WDT_NUM];
801 #define QM_WDT test_wdt
802
803 #else
804 extern qm_wdt_reg_t *qm_wdt[QM_WDT_NUM];
805 /* WDT register base address. */
806 #define QM_WDT_0_BASE (0xB0000000)
807
808 /* WDT register block. */
809 #define QM_WDT qm_wdt
810 #endif
811
812 /* Watchdog enable. */
813 #define QM_WDT_CR_WDT_ENABLE (BIT(0))
814 /* Watchdog mode. */
815 #define QM_WDT_CR_RMOD (BIT(1))
816 /* Watchdog mode offset. */
817 #define QM_WDT_CR_RMOD_OFFSET (1)
818 /* Watchdog Timeout Mask. */
819 #define QM_WDT_TORR_TOP_MASK (0xF)
820 /* Watchdog reload special value. */
821 #define QM_WDT_RELOAD_VALUE (0x76)
822 /* Number of WDT controllers. */
823 #define NUM_WDT_CONTROLLERS (1)
824 /* Watchdog does not have pause enable. */
825 #define HAS_WDT_PAUSE (0)
826 /* Software SoC watch required. */
827 #define HAS_SW_SOCWATCH (1)
828 /* Peripheral WDT clock enable mask. */
829 #define QM_WDT_CLOCK_EN_MASK (BIT(1))
830 /* Required to enable WDT clock on start. */
831 #define HAS_WDT_CLOCK_ENABLE (1)
832
833 /**
834 * WDT timeout table (in clock cycles):
835 * Each table entry corresponds with the value loaded
836 * into the WDT at the time of a WDT reload for the
837 * corresponding timeout range register value.
838 *
839 * TORR | Timeout (Clock Cycles)
840 * 0. | 2^16 (65536)
841 * 1. | 2^17 (131072)
842 * 2. | 2^18 (262144)
843 * 3. | 2^19 (524288)
844 * 4. | 2^20 (1048576)
845 * 5. | 2^21 (2097152)
846 * 6. | 2^22 (4194304)
847 * 7. | 2^23 (8388608)
848 * 8. | 2^24 (16777216)
849 * 9. | 2^25 (33554432)
850 * 10. | 2^26 (67108864)
851 * 11. | 2^27 (134217728)
852 * 12. | 2^28 (268435456)
853 * 13. | 2^29 (536870912)
854 * 14. | 2^30 (1073741824)
855 * 15. | 2^31 (2147483648)
856 */
857
858 /** @} */
859
860 /**
861 * @name UART
862 * @{
863 */
864
865 /* Break character Bit. */
866 #define QM_UART_LCR_BREAK BIT(6)
867 /* Divisor Latch Access Bit. */
868 #define QM_UART_LCR_DLAB BIT(7)
869
870 /* Request to Send Bit. */
871 #define QM_UART_MCR_RTS BIT(1)
872 /* Loopback Enable Bit. */
873 #define QM_UART_MCR_LOOPBACK BIT(4)
874 /* Auto Flow Control Enable Bit. */
875 #define QM_UART_MCR_AFCE BIT(5)
876
877 /* FIFO Enable Bit. */
878 #define QM_UART_FCR_FIFOE BIT(0)
879 /* Reset Receive FIFO. */
880 #define QM_UART_FCR_RFIFOR BIT(1)
881 /* Reset Transmit FIFO. */
882 #define QM_UART_FCR_XFIFOR BIT(2)
883
884 /* Default FIFO RX & TX Thresholds, half full for both. */
885 #define QM_UART_FCR_DEFAULT_TX_RX_THRESHOLD (0xB0)
886 /* Change TX Threshold to empty, keep RX Threshold to default. */
887 #define QM_UART_FCR_TX_0_RX_1_2_THRESHOLD (0x80)
888
889 /* Transmit Holding Register Empty. */
890 #define QM_UART_IIR_THR_EMPTY (0x02)
891 /* Received Data Available. */
892 #define QM_UART_IIR_RECV_DATA_AVAIL (0x04)
893 /* Receiver Line Status. */
894 #define QM_UART_IIR_RECV_LINE_STATUS (0x06)
895 /* Character Timeout. */
896 #define QM_UART_IIR_CHAR_TIMEOUT (0x0C)
897 /* Interrupt ID Mask. */
898 #define QM_UART_IIR_IID_MASK (0x0F)
899
900 /* Data Ready Bit. */
901 #define QM_UART_LSR_DR BIT(0)
902 /* Overflow Error Bit. */
903 #define QM_UART_LSR_OE BIT(1)
904 /* Parity Error Bit. */
905 #define QM_UART_LSR_PE BIT(2)
906 /* Framing Error Bit. */
907 #define QM_UART_LSR_FE BIT(3)
908 /* Break Interrupt Bit. */
909 #define QM_UART_LSR_BI BIT(4)
910 /* Transmit Holding Register Empty Bit. */
911 #define QM_UART_LSR_THRE BIT(5)
912 /* Transmitter Empty Bit. */
913 #define QM_UART_LSR_TEMT BIT(6)
914 /* Receiver FIFO Error Bit. */
915 #define QM_UART_LSR_RFE BIT(7)
916
917 /* Enable Received Data Available Interrupt. */
918 #define QM_UART_IER_ERBFI BIT(0)
919 /* Enable Transmit Holding Register Empty Interrupt. */
920 #define QM_UART_IER_ETBEI BIT(1)
921 /* Enable Receiver Line Status Interrupt. */
922 #define QM_UART_IER_ELSI BIT(2)
923 /* Programmable THRE Interrupt Mode. */
924 #define QM_UART_IER_PTIME BIT(7)
925
926 /* Line Status Errors. */
927 #define QM_UART_LSR_ERROR_BITS \
928 (QM_UART_LSR_OE | QM_UART_LSR_PE | QM_UART_LSR_FE | QM_UART_LSR_BI)
929
930 /* FIFO Depth. */
931 #define QM_UART_FIFO_DEPTH (16)
932 /* FIFO Half Depth. */
933 #define QM_UART_FIFO_HALF_DEPTH (QM_UART_FIFO_DEPTH / 2)
934
935 /* Divisor Latch High Offset. */
936 #define QM_UART_CFG_BAUD_DLH_OFFS 16
937 /* Divisor Latch Low Offset. */
938 #define QM_UART_CFG_BAUD_DLL_OFFS 8
939 /* Divisor Latch Fraction Offset. */
940 #define QM_UART_CFG_BAUD_DLF_OFFS 0
941 /* Divisor Latch High Mask. */
942 #define QM_UART_CFG_BAUD_DLH_MASK (0xFF << QM_UART_CFG_BAUD_DLH_OFFS)
943 /* Divisor Latch Low Mask. */
944 #define QM_UART_CFG_BAUD_DLL_MASK (0xFF << QM_UART_CFG_BAUD_DLL_OFFS)
945 /* Divisor Latch Fraction Mask. */
946 #define QM_UART_CFG_BAUD_DLF_MASK (0xFF << QM_UART_CFG_BAUD_DLF_OFFS)
947
948 /* Divisor Latch Packing Helper. */
949 #define QM_UART_CFG_BAUD_DL_PACK(dlh, dll, dlf) \
950 (dlh << QM_UART_CFG_BAUD_DLH_OFFS | dll << QM_UART_CFG_BAUD_DLL_OFFS | \
951 dlf << QM_UART_CFG_BAUD_DLF_OFFS)
952
953 /* Divisor Latch High Unpacking Helper. */
954 #define QM_UART_CFG_BAUD_DLH_UNPACK(packed) \
955 ((packed & QM_UART_CFG_BAUD_DLH_MASK) >> QM_UART_CFG_BAUD_DLH_OFFS)
956 /* Divisor Latch Low Unpacking Helper. */
957 #define QM_UART_CFG_BAUD_DLL_UNPACK(packed) \
958 ((packed & QM_UART_CFG_BAUD_DLL_MASK) >> QM_UART_CFG_BAUD_DLL_OFFS)
959 /* Divisor Latch Fraction Unpacking Helper. */
960 #define QM_UART_CFG_BAUD_DLF_UNPACK(packed) \
961 ((packed & QM_UART_CFG_BAUD_DLF_MASK) >> QM_UART_CFG_BAUD_DLF_OFFS)
962
963 /** Number of UART controllers. */
964 typedef enum { QM_UART_0 = 0, QM_UART_1, QM_UART_NUM } qm_uart_t;
965
966 /** UART register map. */
967 typedef struct {
968 QM_RW uint32_t rbr_thr_dll; /**< Rx Buffer/ Tx Holding/ Div Latch Low */
969 QM_RW uint32_t ier_dlh; /**< Interrupt Enable / Divisor Latch High */
970 QM_RW uint32_t iir_fcr; /**< Interrupt Identification / FIFO Control */
971 QM_RW uint32_t lcr; /**< Line Control */
972 QM_RW uint32_t mcr; /**< MODEM Control */
973 QM_RW uint32_t lsr; /**< Line Status */
974 QM_RW uint32_t msr; /**< MODEM Status */
975 QM_RW uint32_t scr; /**< Scratchpad */
976 QM_RW uint32_t reserved[23];
977 QM_RW uint32_t usr; /**< UART Status */
978 QM_RW uint32_t reserved1[9];
979 QM_RW uint32_t htx; /**< Halt Transmission */
980 QM_RW uint32_t dmasa; /**< DMA Software Acknowledge */
981 QM_RW uint32_t reserved2[5];
982 QM_RW uint32_t dlf; /**< Divisor Latch Fraction */
983 QM_RW uint32_t padding[0xCF]; /* (0x400 - 0xC4) / 4 */
984 } qm_uart_reg_t;
985
986 /**
987 * UART context to be saved between sleep/resume.
988 *
989 * Application should not modify the content.
990 * This structure is only intended to be used by the qm_uart_save_context and
991 * qm_uart_restore_context functions.
992 */
993 typedef struct {
994 uint32_t ier; /**< Interrupt Enable Register. */
995 uint32_t dlh; /**< Divisor Latch High. */
996 uint32_t dll; /**< Divisor Latch Low. */
997 uint32_t lcr; /**< Line Control. */
998 uint32_t mcr; /**< Modem Control. */
999 uint32_t scr; /**< Scratchpad. */
1000 uint32_t htx; /**< Halt Transmission. */
1001 uint32_t dlf; /**< Divisor Latch Fraction. */
1002 } qm_uart_context_t;
1003
1004 #if (UNIT_TEST)
1005 qm_uart_reg_t test_uart_instance;
1006 qm_uart_reg_t *test_uart[QM_UART_NUM];
1007 #define QM_UART test_uart
1008
1009 #else
1010 /* UART register base address. */
1011 #define QM_UART_0_BASE (0xB0002000)
1012 #define QM_UART_1_BASE (0xB0002400)
1013 /* UART register block. */
1014 extern qm_uart_reg_t *qm_uart[QM_UART_NUM];
1015 #define QM_UART qm_uart
1016 #endif
1017
1018 /** @} */
1019
1020 /**
1021 * @name SPI
1022 * @{
1023 */
1024
1025 /** Number of SPI controllers. */
1026 typedef enum {
1027 QM_SPI_MST_0 = 0,
1028 QM_SPI_MST_1,
1029 QM_SPI_SLV_0,
1030 QM_SPI_NUM
1031 } qm_spi_t;
1032
1033 /** SPI register map. */
1034 typedef struct {
1035 QM_RW uint32_t ctrlr0; /**< Control Register 0 */
1036 QM_RW uint32_t ctrlr1; /**< Control Register 1 */
1037 QM_RW uint32_t ssienr; /**< SSI Enable Register */
1038 QM_RW uint32_t mwcr; /**< Microwire Control Register */
1039 QM_RW uint32_t ser; /**< Slave Enable Register */
1040 QM_RW uint32_t baudr; /**< Baud Rate Select */
1041 QM_RW uint32_t txftlr; /**< Transmit FIFO Threshold Level */
1042 QM_RW uint32_t rxftlr; /**< Receive FIFO Threshold Level */
1043 QM_RW uint32_t txflr; /**< Transmit FIFO Level Register */
1044 QM_RW uint32_t rxflr; /**< Receive FIFO Level Register */
1045 QM_RW uint32_t sr; /**< Status Register */
1046 QM_RW uint32_t imr; /**< Interrupt Mask Register */
1047 QM_RW uint32_t isr; /**< Interrupt Status Register */
1048 QM_RW uint32_t risr; /**< Raw Interrupt Status Register */
1049 QM_RW uint32_t txoicr; /**< Tx FIFO Overflow Interrupt Clear Register*/
1050 QM_RW uint32_t rxoicr; /**< Rx FIFO Overflow Interrupt Clear Register */
1051 QM_RW uint32_t rxuicr; /**< Rx FIFO Underflow Interrupt Clear Register*/
1052 QM_RW uint32_t msticr; /**< Multi-Master Interrupt Clear Register */
1053 QM_RW uint32_t icr; /**< Interrupt Clear Register */
1054 QM_RW uint32_t dmacr; /**< DMA Control Register */
1055 QM_RW uint32_t dmatdlr; /**< DMA Transmit Data Level */
1056 QM_RW uint32_t dmardlr; /**< DMA Receive Data Level */
1057 QM_RW uint32_t idr; /**< Identification Register */
1058 QM_RW uint32_t ssi_comp_version; /**< coreKit Version ID register */
1059 QM_RW uint32_t dr[36]; /**< Data Register */
1060 QM_RW uint32_t rx_sample_dly; /**< RX Sample Delay Register */
1061 QM_RW uint32_t padding[0xC4]; /* (0x400 - 0xF0) / 4 */
1062 } qm_spi_reg_t;
1063
1064 /**
1065 * SPI context type.
1066 *
1067 * Applications should not modify the content.
1068 * This structure is only intended to be used by
1069 * the qm_spi_save_context and qm_spi_restore_context functions.
1070 */
1071 typedef struct {
1072 uint32_t ctrlr0; /**< Control Register 0. */
1073 uint32_t ser; /**< Slave Enable Register. */
1074 uint32_t baudr; /**< Baud Rate Select. */
1075 } qm_spi_context_t;
1076
1077 #if (UNIT_TEST)
1078 qm_spi_reg_t test_spi;
1079 qm_spi_reg_t *test_spi_controllers[QM_SPI_NUM];
1080
1081 #define QM_SPI test_spi_controllers
1082
1083 #else
1084 /* SPI Master register base address. */
1085 #define QM_SPI_MST_0_BASE (0xB0001000)
1086 #define QM_SPI_MST_1_BASE (0xB0001400)
1087 extern qm_spi_reg_t *qm_spi_controllers[QM_SPI_NUM];
1088 #define QM_SPI qm_spi_controllers
1089
1090 /* SPI Slave register base address. */
1091 #define QM_SPI_SLV_BASE (0xB0001800)
1092 #endif
1093
1094 /* SPI Ctrlr0 register. */
1095 #define QM_SPI_CTRLR0_DFS_32_MASK (0x001F0000)
1096 #define QM_SPI_CTRLR0_TMOD_MASK (0x00000300)
1097 #define QM_SPI_CTRLR0_SCPOL_SCPH_MASK (0x000000C0)
1098 #define QM_SPI_CTRLR0_FRF_MASK (0x00000030)
1099 #define QM_SPI_CTRLR0_DFS_32_OFFSET (16)
1100 #define QM_SPI_CTRLR0_TMOD_OFFSET (8)
1101 #define QM_SPI_CTRLR0_SCPOL_SCPH_OFFSET (6)
1102 #define QM_SPI_CTRLR0_FRF_OFFSET (4)
1103 #define QM_SPI_CTRLR0_SLV_OE BIT(10)
1104
1105 /* SPI SSI Enable register. */
1106 #define QM_SPI_SSIENR_SSIENR BIT(0)
1107
1108 /* SPI Status register. */
1109 #define QM_SPI_SR_BUSY BIT(0)
1110 #define QM_SPI_SR_TFNF BIT(1)
1111 #define QM_SPI_SR_TFE BIT(2)
1112 #define QM_SPI_SR_RFNE BIT(3)
1113 #define QM_SPI_SR_RFF BIT(4)
1114
1115 /* SPI Interrupt Mask register. */
1116 #define QM_SPI_IMR_MASK_ALL (0x00)
1117 #define QM_SPI_IMR_TXEIM BIT(0)
1118 #define QM_SPI_IMR_TXOIM BIT(1)
1119 #define QM_SPI_IMR_RXUIM BIT(2)
1120 #define QM_SPI_IMR_RXOIM BIT(3)
1121 #define QM_SPI_IMR_RXFIM BIT(4)
1122
1123 /* SPI Interrupt Status register. */
1124 #define QM_SPI_ISR_TXEIS BIT(0)
1125 #define QM_SPI_ISR_TXOIS BIT(1)
1126 #define QM_SPI_ISR_RXUIS BIT(2)
1127 #define QM_SPI_ISR_RXOIS BIT(3)
1128 #define QM_SPI_ISR_RXFIS BIT(4)
1129
1130 /* SPI Raw Interrupt Status register. */
1131 #define QM_SPI_RISR_TXEIR BIT(0)
1132 #define QM_SPI_RISR_TXOIR BIT(1)
1133 #define QM_SPI_RISR_RXUIR BIT(2)
1134 #define QM_SPI_RISR_RXOIR BIT(3)
1135 #define QM_SPI_RISR_RXFIR BIT(4)
1136
1137 /* SPI DMA control. */
1138 #define QM_SPI_DMACR_RDMAE BIT(0)
1139 #define QM_SPI_DMACR_TDMAE BIT(1)
1140
1141 /** @} */
1142
1143 /**
1144 * @name RTC
1145 * @{
1146 */
1147
1148 /** Number of RTC controllers. */
1149 typedef enum { QM_RTC_0 = 0, QM_RTC_NUM } qm_rtc_t;
1150
1151 /** RTC register map. */
1152 typedef struct {
1153 QM_RW uint32_t rtc_ccvr; /**< Current Counter Value Register */
1154 QM_RW uint32_t rtc_cmr; /**< Current Match Register */
1155 QM_RW uint32_t rtc_clr; /**< Counter Load Register */
1156 QM_RW uint32_t rtc_ccr; /**< Counter Control Register */
1157 QM_RW uint32_t rtc_stat; /**< Interrupt Status Register */
1158 QM_RW uint32_t rtc_rstat; /**< Interrupt Raw Status Register */
1159 QM_RW uint32_t rtc_eoi; /**< End of Interrupt Register */
1160 QM_RW uint32_t rtc_comp_version; /**< End of Interrupt Register */
1161 } qm_rtc_reg_t;
1162
1163 /* Nothing to save for rtc on Quark SE. */
1164 #define qm_rtc_context_t uint8_t
1165
1166 #define QM_RTC_CCR_INTERRUPT_ENABLE BIT(0)
1167 #define QM_RTC_CCR_INTERRUPT_MASK BIT(1)
1168 #define QM_RTC_CCR_ENABLE BIT(2)
1169
1170 #if (UNIT_TEST)
1171 qm_rtc_reg_t test_rtc_instance[QM_RTC_NUM];
1172 qm_rtc_reg_t *test_rtc[QM_RTC_NUM];
1173
1174 #define QM_RTC test_rtc
1175
1176 #else
1177 extern qm_rtc_reg_t *qm_rtc[QM_RTC_NUM];
1178 /* RTC register base address. */
1179 #define QM_RTC_BASE (0xB0000400)
1180
1181 /* RTC register block. */
1182 #define QM_RTC qm_rtc
1183 #endif
1184
1185 /** @} */
1186
1187 /**
1188 * @name I2C
1189 * @{
1190 */
1191
1192 /** Number of I2C controllers. */
1193 typedef enum { QM_I2C_0 = 0, QM_I2C_1, QM_I2C_NUM } qm_i2c_t;
1194
1195 /** I2C register map. */
1196 typedef struct {
1197 QM_RW uint32_t ic_con; /**< Control Register */
1198 QM_RW uint32_t ic_tar; /**< Master Target Address */
1199 QM_RW uint32_t ic_sar; /**< Slave Address */
1200 QM_RW uint32_t ic_hs_maddr; /**< High Speed Master ID */
1201 QM_RW uint32_t ic_data_cmd; /**< Data Buffer and Command */
1202 QM_RW uint32_t
1203 ic_ss_scl_hcnt; /**< Standard Speed Clock SCL High Count */
1204 QM_RW uint32_t
1205 ic_ss_scl_lcnt; /**< Standard Speed Clock SCL Low Count */
1206 QM_RW uint32_t ic_fs_scl_hcnt; /**< Fast Speed Clock SCL High Count */
1207 QM_RW uint32_t
1208 ic_fs_scl_lcnt; /**< Fast Speed I2C Clock SCL Low Count */
1209 QM_RW uint32_t
1210 ic_hs_scl_hcnt; /**< High Speed I2C Clock SCL High Count */
1211 QM_RW uint32_t
1212 ic_hs_scl_lcnt; /**< High Speed I2C Clock SCL Low Count */
1213 QM_RW uint32_t ic_intr_stat; /**< Interrupt Status */
1214 QM_RW uint32_t ic_intr_mask; /**< Interrupt Mask */
1215 QM_RW uint32_t ic_raw_intr_stat; /**< Raw Interrupt Status */
1216 QM_RW uint32_t ic_rx_tl; /**< Receive FIFO Threshold Level */
1217 QM_RW uint32_t ic_tx_tl; /**< Transmit FIFO Threshold Level */
1218 QM_RW uint32_t
1219 ic_clr_intr; /**< Clear Combined and Individual Interrupt */
1220 QM_RW uint32_t ic_clr_rx_under; /**< Clear RX_UNDER Interrupt */
1221 QM_RW uint32_t ic_clr_rx_over; /**< Clear RX_OVER Interrupt */
1222 QM_RW uint32_t ic_clr_tx_over; /**< Clear TX_OVER Interrupt */
1223 QM_RW uint32_t ic_clr_rd_req; /**< Clear RD_REQ Interrupt */
1224 QM_RW uint32_t ic_clr_tx_abrt; /**< Clear TX_ABRT Interrupt */
1225 QM_RW uint32_t ic_clr_rx_done; /**< Clear RX_DONE Interrupt */
1226 QM_RW uint32_t ic_clr_activity; /**< Clear ACTIVITY Interrupt */
1227 QM_RW uint32_t ic_clr_stop_det; /**< Clear STOP_DET Interrupt */
1228 QM_RW uint32_t ic_clr_start_det; /**< Clear START_DET Interrupt */
1229 QM_RW uint32_t ic_clr_gen_call; /**< Clear GEN_CALL Interrupt */
1230 QM_RW uint32_t ic_enable; /**< Enable */
1231 QM_RW uint32_t ic_status; /**< Status */
1232 QM_RW uint32_t ic_txflr; /**< Transmit FIFO Level */
1233 QM_RW uint32_t ic_rxflr; /**< Receive FIFO Level */
1234 QM_RW uint32_t ic_sda_hold; /**< SDA Hold */
1235 QM_RW uint32_t ic_tx_abrt_source; /**< Transmit Abort Source */
1236 QM_RW uint32_t reserved;
1237 QM_RW uint32_t ic_dma_cr; /**< DMA Control Register for Tx and Rx
1238 Handshaking Interface */
1239 QM_RW uint32_t ic_dma_tdlr; /**< DMA Transmit Data Level Register */
1240 QM_RW uint32_t ic_dma_rdlr; /**< I2C Receive Data Level Register */
1241 QM_RW uint32_t ic_sda_setup; /**< SDA Setup */
1242 QM_RW uint32_t ic_ack_general_call; /**< General Call Ack */
1243 QM_RW uint32_t ic_enable_status; /**< Enable Status */
1244 QM_RW uint32_t ic_fs_spklen; /**< SS and FS Spike Suppression Limit */
1245 QM_RW uint32_t ic_hs_spklen; /**< HS spike suppression limit */
1246 QM_RW uint32_t reserved1[19];
1247 QM_RW uint32_t ic_comp_param_1; /**< Configuration Parameters */
1248 QM_RW uint32_t ic_comp_version; /**< Component Version */
1249 QM_RW uint32_t ic_comp_type; /**< Component Type */
1250 QM_RW uint32_t padding[0xC0]; /* Padding (0x400-0xFC)/4 */
1251 } qm_i2c_reg_t;
1252
1253 /**
1254 * I2C context to be saved between sleep/resume.
1255 *
1256 * Application should not modify the content.
1257 * This structure is only intended to be used by the qm_i2c_save_context and
1258 * qm_i2c_restore_context functions.
1259 */
1260 typedef struct {
1261 uint32_t con; /**< Control Register. */
1262 uint32_t sar; /**< Slave Address. */
1263 uint32_t ss_scl_hcnt; /**< Standard Speed Clock SCL High Count. */
1264 uint32_t ss_scl_lcnt; /**< Standard Speed Clock SCL Low Count. */
1265 uint32_t fs_scl_hcnt; /**< Fast Speed Clock SCL High Count. */
1266 uint32_t fs_scl_lcnt; /**< Fast Speed I2C Clock SCL Low Count. */
1267 uint32_t enable; /**< Enable. */
1268 uint32_t fs_spklen; /**< SS and FS Spike Suppression Limit. */
1269 uint32_t ic_intr_mask; /**< I2C Interrupt Mask. */
1270 uint32_t rx_tl; /** Receive FIFO threshold register. */
1271 uint32_t tx_tl; /** Transmit FIFO threshold register. */
1272 } qm_i2c_context_t;
1273
1274 #if (UNIT_TEST)
1275 qm_i2c_reg_t test_i2c_instance[QM_I2C_NUM];
1276 qm_i2c_reg_t *test_i2c[QM_I2C_NUM];
1277
1278 #define QM_I2C test_i2c
1279
1280 #else
1281 /* I2C Master register base address. */
1282 #define QM_I2C_0_BASE (0xB0002800)
1283 #define QM_I2C_1_BASE (0xB0002C00)
1284
1285 /** I2C register block. */
1286 extern qm_i2c_reg_t *qm_i2c[QM_I2C_NUM];
1287 #define QM_I2C qm_i2c
1288 #endif
1289
1290 #define QM_I2C_IC_ENABLE_CONTROLLER_EN BIT(0)
1291 #define QM_I2C_IC_ENABLE_CONTROLLER_ABORT BIT(1)
1292 #define QM_I2C_IC_ENABLE_STATUS_IC_EN BIT(0)
1293 #define QM_I2C_IC_CON_MASTER_MODE BIT(0)
1294 #define QM_I2C_IC_CON_SLAVE_DISABLE BIT(6)
1295 #define QM_I2C_IC_CON_10BITADDR_MASTER BIT(4)
1296 #define QM_I2C_IC_CON_10BITADDR_MASTER_OFFSET (4)
1297 #define QM_I2C_IC_CON_10BITADDR_SLAVE BIT(3)
1298 #define QM_I2C_IC_CON_10BITADDR_SLAVE_OFFSET (3)
1299 #define QM_I2C_IC_CON_SPEED_OFFSET (1)
1300 #define QM_I2C_IC_CON_SPEED_SS BIT(1)
1301 #define QM_I2C_IC_CON_SPEED_FS_FSP BIT(2)
1302 #define QM_I2C_IC_CON_SPEED_MASK (0x06)
1303 #define QM_I2C_IC_CON_RESTART_EN BIT(5)
1304 #define QM_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
1305 #define QM_I2C_IC_DATA_CMD_READ BIT(8)
1306 #define QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL BIT(9)
1307 #define QM_I2C_IC_DATA_CMD_LSB_MASK (0x000000FF)
1308 #define QM_I2C_IC_RAW_INTR_STAT_RX_FULL BIT(2)
1309 #define QM_I2C_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
1310 #define QM_I2C_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
1311 #define QM_I2C_IC_RAW_INTR_STAT_RESTART_DETECTED BIT(12)
1312 #define QM_I2C_IC_TX_ABRT_SOURCE_NAK_MASK (0x1F)
1313 #define QM_I2C_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
1314 #define QM_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
1315 #define QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK (0x1FFFF)
1316 #define QM_I2C_IC_STATUS_BUSY_MASK (0x00000060)
1317 #define QM_I2C_IC_STATUS_RFF BIT(4)
1318 #define QM_I2C_IC_STATUS_RFNE BIT(3)
1319 #define QM_I2C_IC_STATUS_TFE BIT(2)
1320 #define QM_I2C_IC_STATUS_TNF BIT(1)
1321 #define QM_I2C_IC_INTR_MASK_ALL (0x00)
1322 #define QM_I2C_IC_INTR_MASK_RX_UNDER BIT(0)
1323 #define QM_I2C_IC_INTR_MASK_RX_OVER BIT(1)
1324 #define QM_I2C_IC_INTR_MASK_RX_FULL BIT(2)
1325 #define QM_I2C_IC_INTR_MASK_TX_OVER BIT(3)
1326 #define QM_I2C_IC_INTR_MASK_TX_EMPTY BIT(4)
1327 #define QM_I2C_IC_INTR_MASK_RD_REQ BIT(5)
1328 #define QM_I2C_IC_INTR_MASK_TX_ABORT BIT(6)
1329 #define QM_I2C_IC_INTR_MASK_RX_DONE BIT(7)
1330 #define QM_I2C_IC_INTR_MASK_ACTIVITY BIT(8)
1331 #define QM_I2C_IC_INTR_MASK_STOP_DETECTED BIT(9)
1332 #define QM_I2C_IC_INTR_MASK_START_DETECTED BIT(10)
1333 #define QM_I2C_IC_INTR_MASK_GEN_CALL_DETECTED BIT(11)
1334 #define QM_I2C_IC_INTR_MASK_RESTART_DETECTED BIT(12)
1335 #define QM_I2C_IC_INTR_STAT_RX_UNDER BIT(0)
1336 #define QM_I2C_IC_INTR_STAT_RX_OVER BIT(1)
1337 #define QM_I2C_IC_INTR_STAT_RX_FULL BIT(2)
1338 #define QM_I2C_IC_INTR_STAT_TX_OVER BIT(3)
1339 #define QM_I2C_IC_INTR_STAT_TX_EMPTY BIT(4)
1340 #define QM_I2C_IC_INTR_STAT_RD_REQ BIT(5)
1341 #define QM_I2C_IC_INTR_STAT_TX_ABRT BIT(6)
1342 #define QM_I2C_IC_INTR_STAT_RX_DONE BIT(7)
1343 #define QM_I2C_IC_INTR_STAT_STOP_DETECTED BIT(9)
1344 #define QM_I2C_IC_INTR_STAT_START_DETECTED BIT(10)
1345 #define QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED BIT(11)
1346 #define QM_I2C_IC_LCNT_MAX (65525)
1347 #define QM_I2C_IC_LCNT_MIN (8)
1348 #define QM_I2C_IC_HCNT_MAX (65525)
1349 #define QM_I2C_IC_HCNT_MIN (6)
1350 #define QM_I2C_IC_TAR_MASK (0x3FF)
1351
1352 #define QM_I2C_FIFO_SIZE (16)
1353
1354 /* I2C DMA */
1355 #define QM_I2C_IC_DMA_CR_RX_ENABLE BIT(0)
1356 #define QM_I2C_IC_DMA_CR_TX_ENABLE BIT(1)
1357
1358 /** @} */
1359
1360 /**
1361 * @name GPIO
1362 * @{
1363 */
1364
1365 /** Number of GPIO controllers. */
1366 typedef enum { QM_GPIO_0 = 0, QM_AON_GPIO_0 = 1, QM_GPIO_NUM } qm_gpio_t;
1367
1368 /** GPIO register map. */
1369 typedef struct {
1370 QM_RW uint32_t gpio_swporta_dr; /**< Port A Data */
1371 QM_RW uint32_t gpio_swporta_ddr; /**< Port A Data Direction */
1372 QM_RW uint32_t gpio_swporta_ctl; /**< Port A Data Source */
1373 QM_RW uint32_t reserved[9];
1374 QM_RW uint32_t gpio_inten; /**< Interrupt Enable */
1375 QM_RW uint32_t gpio_intmask; /**< Interrupt Mask */
1376 QM_RW uint32_t gpio_inttype_level; /**< Interrupt Type */
1377 QM_RW uint32_t gpio_int_polarity; /**< Interrupt Polarity */
1378 QM_RW uint32_t gpio_intstatus; /**< Interrupt Status */
1379 QM_RW uint32_t gpio_raw_intstatus; /**< Raw Interrupt Status */
1380 QM_RW uint32_t gpio_debounce; /**< Debounce Enable */
1381 QM_RW uint32_t gpio_porta_eoi; /**< Clear Interrupt */
1382 QM_RW uint32_t gpio_ext_porta; /**< Port A External Port */
1383 QM_RW uint32_t reserved1[3];
1384 QM_RW uint32_t gpio_ls_sync; /**< Synchronization Level */
1385 QM_RW uint32_t reserved2;
1386 QM_RW uint32_t gpio_int_bothedge; /**< Interrupt both edge type */
1387 QM_RW uint32_t reserved3;
1388 QM_RW uint32_t gpio_config_reg2; /**< GPIO Configuration Register 2 */
1389 QM_RW uint32_t gpio_config_reg1; /**< GPIO Configuration Register 1 */
1390 } qm_gpio_reg_t;
1391
1392 /**
1393 * GPIO context type.
1394 *
1395 * Application should not modify the content.
1396 * This structure is only intended to be used by the qm_gpio_save_context and
1397 * qm_gpio_restore_context functions.
1398 */
1399 typedef struct {
1400 uint32_t gpio_swporta_dr; /**< Port A Data. */
1401 uint32_t gpio_swporta_ddr; /**< Port A Data Direction. */
1402 uint32_t gpio_swporta_ctl; /**< Port A Data Source. */
1403 uint32_t gpio_inten; /**< Interrupt Enable. */
1404 uint32_t gpio_intmask; /**< Interrupt Mask. */
1405 uint32_t gpio_inttype_level; /**< Interrupt Type. */
1406 uint32_t gpio_int_polarity; /**< Interrupt Polarity. */
1407 uint32_t gpio_debounce; /**< Debounce Enable. */
1408 uint32_t gpio_ls_sync; /**< Synchronization Level. */
1409 uint32_t gpio_int_bothedge; /**< Interrupt both edge type. */
1410 } qm_gpio_context_t;
1411
1412 #define QM_NUM_GPIO_PINS (32)
1413 #define QM_NUM_AON_GPIO_PINS (6)
1414
1415 #if (UNIT_TEST)
1416 qm_gpio_reg_t test_gpio_instance;
1417 qm_gpio_reg_t *test_gpio[QM_GPIO_NUM];
1418
1419 #define QM_GPIO test_gpio
1420 #else
1421
1422 /* GPIO register base address */
1423 #define QM_GPIO_BASE (0xB0000C00)
1424 #define QM_AON_GPIO_BASE (QM_SCSS_CCU_BASE + 0xB00)
1425
1426 /** GPIO register block */
1427 extern qm_gpio_reg_t *qm_gpio[QM_GPIO_NUM];
1428 #define QM_GPIO qm_gpio
1429 #endif
1430
1431 /** @} */
1432
1433 /**
1434 * @name Flash
1435 * @{
1436 */
1437
1438 #define NUM_FLASH_CONTROLLERS (2)
1439 #define HAS_FLASH_WRITE_DISABLE (1)
1440
1441 /** Number of Flash controllers. */
1442 typedef enum { QM_FLASH_0 = 0, QM_FLASH_1, QM_FLASH_NUM } qm_flash_t;
1443
1444 /** Flash register map. */
1445 typedef struct {
1446 QM_RW uint32_t tmg_ctrl; /**< TMG_CTRL. */
1447 QM_RW uint32_t rom_wr_ctrl; /**< ROM_WR_CTRL. */
1448 QM_RW uint32_t rom_wr_data; /**< ROM_WR_DATA. */
1449 QM_RW uint32_t flash_wr_ctrl; /**< FLASH_WR_CTRL. */
1450 QM_RW uint32_t flash_wr_data; /**< FLASH_WR_DATA. */
1451 QM_RW uint32_t flash_stts; /**< FLASH_STTS. */
1452 QM_RW uint32_t ctrl; /**< CTRL. */
1453 QM_RW uint32_t fpr_rd_cfg[4]; /**< 4 FPR_RD_CFG registers. */
1454 QM_RW uint32_t
1455 mpr_wr_cfg; /**< Flash Write Protection Control Register. */
1456 QM_RW uint32_t mpr_vsts; /**< Protection Status Register. */
1457 } qm_flash_reg_t;
1458
1459 /**
1460 * Flash context type.
1461 *
1462 * Applications should not modify the content.
1463 * This structure is only intended to be used by the
1464 * qm_flash_save_context and qm_flash_restore_context functions.
1465 */
1466 typedef struct {
1467 /** Flash Timing Control Register. */
1468 uint32_t tmg_ctrl;
1469 /** Control Register. */
1470 uint32_t ctrl;
1471 } qm_flash_context_t;
1472
1473 #if (UNIT_TEST)
1474 qm_flash_reg_t test_flash_instance;
1475 qm_flash_reg_t *test_flash[QM_FLASH_NUM];
1476 uint8_t test_flash_page[0x800];
1477
1478 #define QM_FLASH test_flash
1479
1480 #define QM_FLASH_REGION_SYS_1_BASE (test_flash_page)
1481 #define QM_FLASH_REGION_SYS_0_BASE (test_flash_page)
1482 #define QM_FLASH_REGION_OTP_0_BASE (test_flash_page)
1483
1484 #define QM_FLASH_PAGE_MASK (0xCFF)
1485 #define QM_FLASH_MAX_ADDR (0xFFFFFFFF)
1486 #else
1487
1488 /* Flash physical address mappings */
1489
1490 #define QM_FLASH_REGION_SYS_1_BASE (0x40030000)
1491 #define QM_FLASH_REGION_SYS_0_BASE (0x40000000)
1492 #define QM_FLASH_REGION_OTP_0_BASE (0xFFFFE000)
1493
1494 #define QM_FLASH_PAGE_MASK (0x3F800)
1495 #define QM_FLASH_MAX_ADDR (0x30000)
1496
1497 /* Flash controller register base address. */
1498 #define QM_FLASH_BASE_0 (0xB0100000)
1499 #define QM_FLASH_BASE_1 (0xB0200000)
1500
1501 /* Flash controller register block. */
1502 extern qm_flash_reg_t *qm_flash[QM_FLASH_NUM];
1503 #define QM_FLASH qm_flash
1504
1505 #endif
1506
1507 #define QM_FLASH_REGION_DATA_BASE_OFFSET (0x00)
1508 #define QM_FLASH_MAX_WAIT_STATES (0xF)
1509 #define QM_FLASH_MAX_US_COUNT (0x3F)
1510 #define QM_FLASH_MAX_PAGE_NUM \
1511 (QM_FLASH_MAX_ADDR / (4 * QM_FLASH_PAGE_SIZE_DWORDS))
1512 #define QM_FLASH_CLK_SLOW BIT(14)
1513 #define QM_FLASH_LVE_MODE BIT(5)
1514
1515 /* Flash mask to clear timing. */
1516 #define QM_FLASH_TMG_DEF_MASK (0xFFFFFC00)
1517 /* Flash mask to clear micro seconds. */
1518 #define QM_FLASH_MICRO_SEC_COUNT_MASK (0x3F)
1519 /* Flash mask to clear wait state. */
1520 #define QM_FLASH_WAIT_STATE_MASK (0x3C0)
1521 /* Flash wait state offset bit. */
1522 #define QM_FLASH_WAIT_STATE_OFFSET (6)
1523 /* Flash write disable offset bit. */
1524 #define QM_FLASH_WRITE_DISABLE_OFFSET (4)
1525 /* Flash write disable value. */
1526 #define QM_FLASH_WRITE_DISABLE_VAL BIT(4)
1527
1528 /* Flash page erase request. */
1529 #define ER_REQ BIT(1)
1530 /* Flash page erase done. */
1531 #define ER_DONE (1)
1532 /* Flash page write request. */
1533 #define WR_REQ (1)
1534 /* Flash page write done. */
1535 #define WR_DONE BIT(1)
1536
1537 /* Flash write address offset. */
1538 #define WR_ADDR_OFFSET (2)
1539 /* Flash perform mass erase includes OTP region. */
1540 #define MASS_ERASE_INFO BIT(6)
1541 /* Flash perform mass erase. */
1542 #define MASS_ERASE BIT(7)
1543
1544 /* ROM read disable for upper 4k. */
1545 #define ROM_RD_DIS_U BIT(3)
1546 /* ROM read disable for lower 4k. */
1547 #define ROM_RD_DIS_L BIT(2)
1548 /* Flash prefetch buffer flush bit. */
1549 #define QM_FLASH_CTRL_PRE_FLUSH_MASK BIT(1)
1550 /* Flash prefetch enable bit. */
1551 #define QM_FLASH_CTRL_PRE_EN_MASK BIT(0)
1552
1553 #define QM_FLASH_ADDRESS_MASK (0x7FF)
1554 /* Increment by 4 bytes each time, but there is an offset of 2, so 0x10. */
1555 #define QM_FLASH_ADDR_INC (0x10)
1556
1557 /* Flash page size in dwords. */
1558 #define QM_FLASH_PAGE_SIZE_DWORDS (0x200)
1559 /* Flash page size in bytes. */
1560 #define QM_FLASH_PAGE_SIZE_BYTES (0x800)
1561 /* Flash page size in bits. */
1562 #define QM_FLASH_PAGE_SIZE_BITS (11)
1563 /* OTP ROM_PROG bit. */
1564 #define QM_FLASH_STTS_ROM_PROG BIT(2)
1565
1566 /** @} */
1567
1568 /**
1569 * @name Flash Protection Region
1570 * @{
1571 */
1572
1573 /**
1574 * FPR register map.
1575 */
1576 typedef enum {
1577 QM_FPR_0, /**< FPR 0. */
1578 QM_FPR_1, /**< FPR 1. */
1579 QM_FPR_2, /**< FPR 2. */
1580 QM_FPR_3, /**< FPR 3. */
1581 QM_FPR_NUM
1582 } qm_fpr_id_t;
1583
1584 /**
1585 * FPR context type.
1586 *
1587 * Applications should not modify the content.
1588 * This structure is only intended to be used by the
1589 * qm_fpr_save_context and qm_fpr_restore_context functions.
1590 */
1591 typedef struct {
1592 /** Flash Protection Region Read Control Register. */
1593 uint32_t fpr_rd_cfg[QM_FPR_NUM];
1594 } qm_fpr_context_t;
1595
1596 /* The addressing granularity of MPRs. */
1597 #define QM_FPR_GRANULARITY (1024)
1598
1599 /** @} */
1600
1601 /**
1602 * @name Memory Protection Region
1603 * @{
1604 */
1605
1606 /* MPR identifier */
1607 typedef enum {
1608 QM_MPR_0 = 0, /**< Memory Protection Region 0. */
1609 QM_MPR_1, /**< Memory Protection Region 1. */
1610 QM_MPR_2, /**< Memory Protection Region 2. */
1611 QM_MPR_3, /**< Memory Protection Region 3. */
1612 QM_MPR_NUM /**< Number of Memory Protection Regions. */
1613 } qm_mpr_id_t;
1614
1615 /** Memory Protection Region register map. */
1616 typedef struct {
1617 QM_RW uint32_t mpr_cfg[4]; /**< MPR CFG */
1618 QM_RW uint32_t mpr_vdata; /**< MPR_VDATA */
1619 QM_RW uint32_t mpr_vsts; /**< MPR_VSTS */
1620 } qm_mpr_reg_t;
1621
1622 /**
1623 * MPR context type.
1624 *
1625 * Application should not modify the content.
1626 * This structure is only intended to be used by the qm_mpr_save_context and
1627 * qm_mpr_restore_context functions.
1628 */
1629 typedef struct {
1630 uint32_t mpr_cfg[QM_MPR_NUM]; /**< MPR Configuration Register. */
1631 } qm_mpr_context_t;
1632
1633 /* The addressing granularity of MPRs. */
1634 #define QM_MPR_GRANULARITY (1024)
1635
1636 #if (UNIT_TEST)
1637 qm_mpr_reg_t test_mpr;
1638
1639 #define QM_MPR ((qm_mpr_reg_t *)(&test_mpr))
1640
1641 #else
1642
1643 #define QM_MPR_BASE (0xB0400000)
1644 #define QM_MPR ((qm_mpr_reg_t *)QM_MPR_BASE)
1645
1646 #endif
1647
1648 #define QM_MPR_UP_BOUND_OFFSET (10)
1649 #define QM_MPR_WR_EN_OFFSET (20)
1650 #define QM_MPR_WR_EN_MASK 0x700000
1651 #define QM_MPR_RD_EN_OFFSET (24)
1652 #define QM_MPR_RD_EN_MASK 0x7000000
1653 #define QM_MPR_EN_LOCK_OFFSET (30)
1654 #define QM_MPR_EN_LOCK_MASK 0xC0000000
1655 #define QM_MPR_VSTS_VALID BIT(31)
1656 /** @} */
1657
1658 #define QM_OSC0_PD BIT(2)
1659
1660 #define QM_CCU_EXTERN_DIV_OFFSET (3)
1661 #define QM_CCU_EXT_CLK_DIV_EN BIT(2)
1662
1663 /**
1664 * @name Peripheral Clock
1665 * @{
1666 */
1667
1668 /** Peripheral clock type. */
1669 typedef enum {
1670 CLK_PERIPH_REGISTER = BIT(0), /**< Peripheral Clock Gate Enable. */
1671 CLK_PERIPH_CLK = BIT(1), /**< Peripheral Clock Enable. */
1672 CLK_PERIPH_I2C_M0 = BIT(2), /**< I2C Master 0 Clock Enable. */
1673 CLK_PERIPH_I2C_M1 = BIT(3), /**< I2C Master 1 Clock Enable. */
1674 CLK_PERIPH_SPI_S = BIT(4), /**< SPI Slave Clock Enable. */
1675 CLK_PERIPH_SPI_M0 = BIT(5), /**< SPI Master 0 Clock Enable. */
1676 CLK_PERIPH_SPI_M1 = BIT(6), /**< SPI Master 1 Clock Enable. */
1677 CLK_PERIPH_GPIO_INTERRUPT = BIT(7), /**< GPIO Interrupt Clock Enable. */
1678 CLK_PERIPH_GPIO_DB = BIT(8), /**< GPIO Debounce Clock Enable. */
1679 CLK_PERIPH_I2S = BIT(9), /**< I2S Clock Enable. */
1680 CLK_PERIPH_WDT_REGISTER = BIT(10), /**< Watchdog Clock Enable. */
1681 CLK_PERIPH_RTC_REGISTER = BIT(11), /**< RTC Clock Gate Enable. */
1682 CLK_PERIPH_PWM_REGISTER = BIT(12), /**< PWM Clock Gate Enable. */
1683 CLK_PERIPH_GPIO_REGISTER = BIT(13), /**< GPIO Clock Gate Enable. */
1684 CLK_PERIPH_SPI_M0_REGISTER =
1685 BIT(14), /**< SPI Master 0 Clock Gate Enable. */
1686 CLK_PERIPH_SPI_M1_REGISTER =
1687 BIT(15), /**< SPI Master 1 Clock Gate Enable. */
1688 CLK_PERIPH_SPI_S_REGISTER =
1689 BIT(16), /**< SPI Slave Clock Gate Enable. */
1690 CLK_PERIPH_UARTA_REGISTER = BIT(17), /**< UARTA Clock Gate Enable. */
1691 CLK_PERIPH_UARTB_REGISTER = BIT(18), /**< UARTB Clock Gate Enable. */
1692 CLK_PERIPH_I2C_M0_REGISTER =
1693 BIT(19), /**< I2C Master 0 Clock Gate Enable. */
1694 CLK_PERIPH_I2C_M1_REGISTER =
1695 BIT(20), /**< I2C Master 1 Clock Gate Enable. */
1696 CLK_PERIPH_I2S_REGISTER = BIT(21), /**< I2S Clock Gate Enable. */
1697 CLK_PERIPH_ALL = 0x3FFFFF /**< Quark SE peripherals Mask. */
1698 } clk_periph_t;
1699
1700 /* Default mask values */
1701 #define CLK_EXTERN_DIV_DEF_MASK (0xFFFFFFE3)
1702 #define CLK_SYS_CLK_DIV_DEF_MASK (0xFFFFFC7F)
1703 #define CLK_RTC_DIV_DEF_MASK (0xFFFFFF83)
1704 #define CLK_GPIO_DB_DIV_DEF_MASK (0xFFFFFFE1)
1705 #define CLK_PERIPH_DIV_DEF_MASK (0xFFFFFFF9)
1706
1707 /** @} */
1708
1709 /**
1710 * @name DMA
1711 * @{
1712 */
1713
1714 /** DMA instances. */
1715 typedef enum {
1716 QM_DMA_0, /**< DMA controller id. */
1717 QM_DMA_NUM /**< Number of DMA controllers. */
1718 } qm_dma_t;
1719
1720 /** DMA channel IDs. */
1721 typedef enum {
1722 QM_DMA_CHANNEL_0 = 0, /**< DMA channel id for channel 0 */
1723 QM_DMA_CHANNEL_1, /**< DMA channel id for channel 1 */
1724 QM_DMA_CHANNEL_2, /**< DMA channel id for channel 2 */
1725 QM_DMA_CHANNEL_3, /**< DMA channel id for channel 3 */
1726 QM_DMA_CHANNEL_4, /**< DMA channel id for channel 4 */
1727 QM_DMA_CHANNEL_5, /**< DMA channel id for channel 5 */
1728 QM_DMA_CHANNEL_6, /**< DMA channel id for channel 6 */
1729 QM_DMA_CHANNEL_7, /**< DMA channel id for channel 7 */
1730 QM_DMA_CHANNEL_NUM /**< Number of DMA channels */
1731 } qm_dma_channel_id_t;
1732
1733 /** DMA hardware handshake interfaces. */
1734 typedef enum {
1735 DMA_HW_IF_UART_A_TX = 0x0, /**< UART_A_TX */
1736 DMA_HW_IF_UART_A_RX = 0x1, /**< UART_A_RX */
1737 DMA_HW_IF_UART_B_TX = 0x2, /**< UART_B_TX*/
1738 DMA_HW_IF_UART_B_RX = 0x3, /**< UART_B_RX */
1739 DMA_HW_IF_SPI_MASTER_0_TX = 0x4, /**< SPI_Master_0_TX */
1740 DMA_HW_IF_SPI_MASTER_0_RX = 0x5, /**< SPI_Master_0_RX */
1741 DMA_HW_IF_SPI_MASTER_1_TX = 0x6, /**< SPI_Master_1_TX */
1742 DMA_HW_IF_SPI_MASTER_1_RX = 0x7, /**< SPI_Master_1_RX */
1743 DMA_HW_IF_SPI_SLAVE_TX = 0x8, /**< SPI_Slave_TX */
1744 DMA_HW_IF_SPI_SLAVE_RX = 0x9, /**< SPI_Slave_RX */
1745 DMA_HW_IF_I2S_PLAYBACK = 0xa, /**< I2S_Playback channel */
1746 DMA_HW_IF_I2S_CAPTURE = 0xb, /**< I2S_Capture channel */
1747 DMA_HW_IF_I2C_MASTER_0_TX = 0xc, /**< I2C_Master_0_TX */
1748 DMA_HW_IF_I2C_MASTER_0_RX = 0xd, /**< I2C_Master_0_RX */
1749 DMA_HW_IF_I2C_MASTER_1_TX = 0xe, /**< I2C_Master_1_TX */
1750 DMA_HW_IF_I2C_MASTER_1_RX = 0xf, /**< I2C_Master_1_RX */
1751 } qm_dma_handshake_interface_t;
1752
1753 /** DMA channel register map. */
1754 typedef struct {
1755 QM_RW uint32_t sar_low; /**< SAR */
1756 QM_RW uint32_t sar_high; /**< SAR */
1757 QM_RW uint32_t dar_low; /**< DAR */
1758 QM_RW uint32_t dar_high; /**< DAR */
1759 QM_RW uint32_t llp_low; /**< LLP */
1760 QM_RW uint32_t llp_high; /**< LLP */
1761 QM_RW uint32_t ctrl_low; /**< CTL */
1762 QM_RW uint32_t ctrl_high; /**< CTL */
1763 QM_RW uint32_t src_stat_low; /**< SSTAT */
1764 QM_RW uint32_t src_stat_high; /**< SSTAT */
1765 QM_RW uint32_t dst_stat_low; /**< DSTAT */
1766 QM_RW uint32_t dst_stat_high; /**< DSTAT */
1767 QM_RW uint32_t src_stat_addr_low; /**< SSTATAR */
1768 QM_RW uint32_t src_stat_addr_high; /**< SSTATAR */
1769 QM_RW uint32_t dst_stat_addr_low; /**< DSTATAR */
1770 QM_RW uint32_t dst_stat_addr_high; /**< DSTATAR */
1771 QM_RW uint32_t cfg_low; /**< CFG */
1772 QM_RW uint32_t cfg_high; /**< CFG */
1773 QM_RW uint32_t src_sg_low; /**< SGR */
1774 QM_RW uint32_t src_sg_high; /**< SGR */
1775 QM_RW uint32_t dst_sg_low; /**< DSR */
1776 QM_RW uint32_t dst_sg_high; /**< DSR */
1777 } qm_dma_chan_reg_t;
1778
1779 /* DMA channel control register offsets and masks. */
1780 #define QM_DMA_CTL_L_INT_EN_MASK BIT(0)
1781 #define QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET (1)
1782 #define QM_DMA_CTL_L_DST_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET)
1783 #define QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET (4)
1784 #define QM_DMA_CTL_L_SRC_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET)
1785 #define QM_DMA_CTL_L_DINC_OFFSET (7)
1786 #define QM_DMA_CTL_L_DINC_MASK (0x3 << QM_DMA_CTL_L_DINC_OFFSET)
1787 #define QM_DMA_CTL_L_SINC_OFFSET (9)
1788 #define QM_DMA_CTL_L_SINC_MASK (0x3 << QM_DMA_CTL_L_SINC_OFFSET)
1789 #define QM_DMA_CTL_L_DEST_MSIZE_OFFSET (11)
1790 #define QM_DMA_CTL_L_DEST_MSIZE_MASK (0x7 << QM_DMA_CTL_L_DEST_MSIZE_OFFSET)
1791 #define QM_DMA_CTL_L_SRC_MSIZE_OFFSET (14)
1792 #define QM_DMA_CTL_L_SRC_MSIZE_MASK (0x7 << QM_DMA_CTL_L_SRC_MSIZE_OFFSET)
1793 #define QM_DMA_CTL_L_TT_FC_OFFSET (20)
1794 #define QM_DMA_CTL_L_TT_FC_MASK (0x7 << QM_DMA_CTL_L_TT_FC_OFFSET)
1795 #define QM_DMA_CTL_L_LLP_DST_EN_MASK BIT(27)
1796 #define QM_DMA_CTL_L_LLP_SRC_EN_MASK BIT(28)
1797 #define QM_DMA_CTL_H_BLOCK_TS_OFFSET (0)
1798 #define QM_DMA_CTL_H_BLOCK_TS_MASK (0xfff << QM_DMA_CTL_H_BLOCK_TS_OFFSET)
1799 #define QM_DMA_CTL_H_BLOCK_TS_MAX 4095
1800 #define QM_DMA_CTL_H_BLOCK_TS_MIN 1
1801
1802 /* DMA channel config register offsets and masks. */
1803 #define QM_DMA_CFG_L_CH_SUSP_MASK BIT(8)
1804 #define QM_DMA_CFG_L_FIFO_EMPTY_MASK BIT(9)
1805 #define QM_DMA_CFG_L_HS_SEL_DST_OFFSET 10
1806 #define QM_DMA_CFG_L_HS_SEL_DST_MASK BIT(QM_DMA_CFG_L_HS_SEL_DST_OFFSET)
1807 #define QM_DMA_CFG_L_HS_SEL_SRC_OFFSET 11
1808 #define QM_DMA_CFG_L_HS_SEL_SRC_MASK BIT(QM_DMA_CFG_L_HS_SEL_SRC_OFFSET)
1809 #define QM_DMA_CFG_L_DST_HS_POL_OFFSET 18
1810 #define QM_DMA_CFG_L_DST_HS_POL_MASK BIT(QM_DMA_CFG_L_DST_HS_POL_OFFSET)
1811 #define QM_DMA_CFG_L_SRC_HS_POL_OFFSET 19
1812 #define QM_DMA_CFG_L_SRC_HS_POL_MASK BIT(QM_DMA_CFG_L_SRC_HS_POL_OFFSET)
1813 #define QM_DMA_CFG_L_RELOAD_SRC_MASK BIT(30)
1814 #define QM_DMA_CFG_L_RELOAD_DST_MASK BIT(31)
1815 #define QM_DMA_CFG_H_DS_UPD_EN_OFFSET (5)
1816 #define QM_DMA_CFG_H_DS_UPD_EN_MASK BIT(QM_DMA_CFG_H_DS_UPD_EN_OFFSET)
1817 #define QM_DMA_CFG_H_SS_UPD_EN_OFFSET (6)
1818 #define QM_DMA_CFG_H_SS_UPD_EN_MASK BIT(QM_DMA_CFG_H_SS_UPD_EN_OFFSET)
1819 #define QM_DMA_CFG_H_SRC_PER_OFFSET (7)
1820 #define QM_DMA_CFG_H_SRC_PER_MASK (0xf << QM_DMA_CFG_H_SRC_PER_OFFSET)
1821 #define QM_DMA_CFG_H_DEST_PER_OFFSET (11)
1822 #define QM_DMA_CFG_H_DEST_PER_MASK (0xf << QM_DMA_CFG_H_DEST_PER_OFFSET)
1823
1824 #define QM_DMA_ENABLE_CLOCK(dma) \
1825 (QM_SCSS_CCU->ccu_mlayer_ahb_ctl |= QM_CCU_DMA_CLK_EN)
1826
1827 /** DMA interrupt register map. */
1828 typedef struct {
1829 QM_RW uint32_t raw_tfr_low; /**< RawTfr */
1830 QM_RW uint32_t raw_tfr_high; /**< RawTfr */
1831 QM_RW uint32_t raw_block_low; /**< RawBlock */
1832 QM_RW uint32_t raw_block_high; /**< RawBlock */
1833 QM_RW uint32_t raw_src_trans_low; /**< RawSrcTran */
1834 QM_RW uint32_t raw_src_trans_high; /**< RawSrcTran */
1835 QM_RW uint32_t raw_dst_trans_low; /**< RawDstTran */
1836 QM_RW uint32_t raw_dst_trans_high; /**< RawDstTran */
1837 QM_RW uint32_t raw_err_low; /**< RawErr */
1838 QM_RW uint32_t raw_err_high; /**< RawErr */
1839 QM_RW uint32_t status_tfr_low; /**< StatusTfr */
1840 QM_RW uint32_t status_tfr_high; /**< StatusTfr */
1841 QM_RW uint32_t status_block_low; /**< StatusBlock */
1842 QM_RW uint32_t status_block_high; /**< StatusBlock */
1843 QM_RW uint32_t status_src_trans_low; /**< StatusSrcTran */
1844 QM_RW uint32_t status_src_trans_high; /**< StatusSrcTran */
1845 QM_RW uint32_t status_dst_trans_low; /**< StatusDstTran */
1846 QM_RW uint32_t status_dst_trans_high; /**< StatusDstTran */
1847 QM_RW uint32_t status_err_low; /**< StatusErr */
1848 QM_RW uint32_t status_err_high; /**< StatusErr */
1849 QM_RW uint32_t mask_tfr_low; /**< MaskTfr */
1850 QM_RW uint32_t mask_tfr_high; /**< MaskTfr */
1851 QM_RW uint32_t mask_block_low; /**< MaskBlock */
1852 QM_RW uint32_t mask_block_high; /**< MaskBlock */
1853 QM_RW uint32_t mask_src_trans_low; /**< MaskSrcTran */
1854 QM_RW uint32_t mask_src_trans_high; /**< MaskSrcTran */
1855 QM_RW uint32_t mask_dst_trans_low; /**< MaskDstTran */
1856 QM_RW uint32_t mask_dst_trans_high; /**< MaskDstTran */
1857 QM_RW uint32_t mask_err_low; /**< MaskErr */
1858 QM_RW uint32_t mask_err_high; /**< MaskErr */
1859 QM_RW uint32_t clear_tfr_low; /**< ClearTfr */
1860 QM_RW uint32_t clear_tfr_high; /**< ClearTfr */
1861 QM_RW uint32_t clear_block_low; /**< ClearBlock */
1862 QM_RW uint32_t clear_block_high; /**< ClearBlock */
1863 QM_RW uint32_t clear_src_trans_low; /**< ClearSrcTran */
1864 QM_RW uint32_t clear_src_trans_high; /**< ClearSrcTran */
1865 QM_RW uint32_t clear_dst_trans_low; /**< ClearDstTran */
1866 QM_RW uint32_t clear_dst_trans_high; /**< ClearDstTran */
1867 QM_RW uint32_t clear_err_low; /**< ClearErr */
1868 QM_RW uint32_t clear_err_high; /**< ClearErr */
1869 QM_RW uint32_t status_int_low; /**< StatusInt */
1870 QM_RW uint32_t status_int_high; /**< StatusInt */
1871 } qm_dma_int_reg_t;
1872
1873 /* DMA interrupt status register bits. */
1874 #define QM_DMA_INT_STATUS_TFR BIT(0)
1875 #define QM_DMA_INT_STATUS_BLOCK BIT(1)
1876 #define QM_DMA_INT_STATUS_ERR BIT(4)
1877
1878 /** DMA miscellaneous register map. */
1879 typedef struct {
1880 QM_RW uint32_t cfg_low; /**< DmaCfgReg */
1881 QM_RW uint32_t cfg_high; /**< DmaCfgReg */
1882 QM_RW uint32_t chan_en_low; /**< ChEnReg */
1883 QM_RW uint32_t chan_en_high; /**< ChEnReg */
1884 QM_RW uint32_t id_low; /**< DmaIdReg */
1885 QM_RW uint32_t id_high; /**< DmaIdReg */
1886 QM_RW uint32_t test_low; /**< DmaTestReg */
1887 QM_RW uint32_t test_high; /**< DmaTestReg */
1888 QM_RW uint32_t reserved[4]; /**< Reserved */
1889 } qm_dma_misc_reg_t;
1890
1891 /* Channel write enable in the misc channel enable register. */
1892 #define QM_DMA_MISC_CHAN_EN_WE_OFFSET (8)
1893
1894 /* Controller enable bit in the misc config register. */
1895 #define QM_DMA_MISC_CFG_DMA_EN BIT(0)
1896
1897 typedef struct {
1898 QM_RW qm_dma_chan_reg_t chan_reg[8]; /**< Channel Register */
1899 QM_RW qm_dma_int_reg_t int_reg; /**< Interrupt Register */
1900 QM_RW uint32_t reserved[12]; /**< Reserved (SW HS) */
1901 QM_RW qm_dma_misc_reg_t misc_reg; /**< Miscellaneous Register */
1902 } qm_dma_reg_t;
1903
1904 /**
1905 * DMA context type.
1906 *
1907 * Applications should not modify the content.
1908 * This structure is only intended to be used by
1909 * the qm_dma_save_context and qm_dma_restore_context functions.
1910 */
1911 typedef struct {
1912 struct {
1913 uint32_t ctrl_low; /**< Channel Control Lower. */
1914 uint32_t cfg_low; /**< Channel Configuration Lower. */
1915 uint32_t cfg_high; /**< Channel Configuration Upper. */
1916 uint32_t llp_low; /**< Channel Linked List Pointer. */
1917 } channel[QM_DMA_CHANNEL_NUM];
1918 uint32_t misc_cfg_low; /**< DMA Configuration. */
1919 } qm_dma_context_t;
1920
1921 #if (UNIT_TEST)
1922 qm_dma_reg_t test_dma_instance[QM_DMA_NUM];
1923 qm_dma_reg_t *test_dma[QM_DMA_NUM];
1924 #define QM_DMA test_dma
1925 #else
1926 #define QM_DMA_BASE (0xB0700000)
1927 extern qm_dma_reg_t *qm_dma[QM_DMA_NUM];
1928 #define QM_DMA qm_dma
1929 #endif
1930
1931 /** @} */
1932
1933 /**
1934 * @name USB
1935 * @{
1936 */
1937
1938 #define QM_USB_EP_DIR_IN_MASK (0x80)
1939 #define QM_USB_IN_EP_NUM (6)
1940 #define QM_USB_OUT_EP_NUM (4)
1941 #define QM_USB_MAX_PACKET_SIZE (64)
1942
1943 /** Number of USB controllers. */
1944 typedef enum { QM_USB_0 = 0, QM_USB_NUM } qm_usb_t;
1945
1946 typedef enum {
1947 QM_USB_IN_EP_0 = 0,
1948 QM_USB_IN_EP_1 = 1,
1949 QM_USB_IN_EP_2 = 2,
1950 QM_USB_IN_EP_3 = 3,
1951 QM_USB_IN_EP_4 = 4,
1952 QM_USB_IN_EP_5 = 5,
1953 QM_USB_OUT_EP_0 = 6,
1954 QM_USB_OUT_EP_1 = 7,
1955 QM_USB_OUT_EP_2 = 8,
1956 QM_USB_OUT_EP_3 = 9
1957 } qm_usb_ep_idx_t;
1958
1959 /** USB register map. */
1960
1961 /** IN Endpoint Registers. */
1962 typedef struct {
1963 QM_RW uint32_t diepctl;
1964 QM_R uint32_t reserved;
1965 QM_RW uint32_t diepint;
1966 QM_R uint32_t reserved1;
1967 QM_RW uint32_t dieptsiz;
1968 QM_RW uint32_t diepdma;
1969 QM_RW uint32_t dtxfsts;
1970 QM_R uint32_t reserved2;
1971 } qm_usb_in_ep_reg_t;
1972
1973 /** OUT Endpoint Registers. */
1974 typedef struct {
1975 QM_RW uint32_t doepctl;
1976 QM_R uint32_t reserved;
1977 QM_RW uint32_t doepint;
1978 QM_R uint32_t reserved1;
1979 QM_RW uint32_t doeptsiz;
1980 QM_RW uint32_t doepdma;
1981 QM_R uint32_t reserved2[2];
1982 } qm_usb_out_ep_reg_t;
1983
1984 /**
1985 * USB Register block type.
1986 */
1987 typedef struct {
1988 QM_RW uint32_t gotgctl; /**< OTG Control. */
1989 QM_RW uint32_t gotgint; /**< OTG Interrupt. */
1990 QM_RW uint32_t gahbcfg; /**< AHB Configuration. */
1991 QM_RW uint32_t gusbcfg; /**< USB Configuration. */
1992 QM_RW uint32_t grstctl; /**< Reset Register. */
1993 QM_RW uint32_t gintsts; /**< Interrupt Status. */
1994 QM_RW uint32_t gintmsk; /**< Interrupt Mask. */
1995 QM_R uint32_t grxstsr; /**< Receive Status Read/Pop. */
1996 QM_R uint32_t grxstsp; /**< Receive Status Read/Pop. */
1997 QM_R uint32_t grxfsiz; /**< Receive FIFO Size. */
1998 QM_R uint32_t gnptxfsiz; /**< Non-periodic Transmit FIFO Size. */
1999 QM_R uint32_t reserved[5];
2000 QM_R uint32_t gsnpsid; /**< Synopsys ID. */
2001 QM_R uint32_t ghwcfg1; /**< HW config - Endpoint direction. */
2002 QM_R uint32_t ghwcfg2; /**< HW config 2. */
2003 QM_R uint32_t ghwcfg3; /**< HW config 3. */
2004 QM_R uint32_t ghwcfg4; /**< HW config 4. */
2005 QM_RW uint32_t gdfifocfg; /**< Global DFIFO Configuration. */
2006 QM_R uint32_t reserved1[43];
2007 QM_RW uint32_t dieptxf1;
2008 QM_RW uint32_t dieptxf2;
2009 QM_RW uint32_t dieptxf3;
2010 QM_RW uint32_t dieptxf4;
2011 QM_RW uint32_t dieptxf5;
2012 QM_R uint32_t reserved2[442];
2013 QM_RW uint32_t dcfg; /**< Device config. */
2014 QM_RW uint32_t dctl; /**< Device control. */
2015 QM_RW uint32_t dsts; /**< Device Status. */
2016 QM_R uint32_t reserved3;
2017 QM_RW uint32_t diepmsk; /**< IN EP Common Interrupt Mask. */
2018 QM_RW uint32_t doepmsk; /**< OUT EP Common Interrupt Mask. */
2019 QM_R uint32_t daint; /**< Device Interrupt Register. */
2020 QM_RW uint32_t daintmsk; /**< Device Interrupt Mask Register. */
2021 QM_R uint32_t reserved4[2];
2022 QM_RW uint32_t dvbusdis; /**< VBUS discharge time register. */
2023 QM_RW uint32_t dvbuspulse; /**< Device VBUS discharge time. */
2024 QM_RW uint32_t dthrctl; /**< Device Threshold Ctrl. */
2025 QM_RW uint32_t diepempmsk; /**< IN EP FIFO Empty Intr Mask. */
2026 QM_R uint32_t reserved5[50];
2027 qm_usb_in_ep_reg_t in_ep_reg[QM_USB_IN_EP_NUM];
2028 QM_R uint32_t reserved6[80];
2029 qm_usb_out_ep_reg_t out_ep_reg[QM_USB_OUT_EP_NUM];
2030 } qm_usb_reg_t;
2031
2032 #if (UNIT_TEST)
2033 qm_usb_reg_t test_usb;
2034 #define QM_USB ((qm_usb_reg_t *)(&test_usb))
2035 #else
2036 #define QM_USB_0_BASE (0xB0500000)
2037 /* USB controller base address */
2038 #define QM_USB ((qm_usb_reg_t *)QM_USB_0_BASE)
2039 #endif
2040
2041 /* USB PLL enable bit */
2042 #define QM_USB_PLL_PDLD BIT(0)
2043 /* USB PLL has locked when this bit is 1 */
2044 #define QM_USB_PLL_LOCK BIT(14)
2045 /* Default values to setup the USB PLL */
2046 #define QM_USB_PLL_CFG0_DEFAULT (0x00001904)
2047
2048 /* USB PLL register */
2049 #if (UNIT_TEST)
2050 uint32_t test_usb_pll;
2051 #define QM_USB_PLL_CFG0 (test_usb_pll)
2052 #else
2053 #define QM_USB_PLL_CFG0 (REG_VAL(0xB0800014))
2054 #endif
2055
2056 /* USB clock enable bit */
2057 #define QM_CCU_USB_CLK_EN BIT(1)
2058
2059 /** @} */
2060
2061 /**
2062 * @name Hardware Fixes
2063 * @{
2064 */
2065
2066 /* Refer to "HARDWARE_ISSUES.rst" for fix description. */
2067 #define FIX_1 (1)
2068 #define FIX_2 (1)
2069 #define FIX_3 (1)
2070
2071 /** @} */
2072
2073 /**
2074 * @name Versioning
2075 * @{
2076 */
2077
2078 #if (UNIT_TEST)
2079 uint32_t test_rom_version;
2080 #define ROM_VERSION_ADDRESS &test_rom_version;
2081 #else
2082 #define ROM_VERSION_ADDRESS \
2083 (BL_DATA_FLASH_REGION_BASE + \
2084 (BL_DATA_SECTION_BASE_PAGE * QM_FLASH_PAGE_SIZE_BYTES) + \
2085 sizeof(qm_flash_data_trim_t))
2086 #endif
2087
2088 /** @} */
2089
2090 /** @} */
2091
2092 #endif /* __REGISTERS_H__ */
qm_uart_context_t::dlh
uint32_t dlh
Divisor Latch High.
Definition: qm_soc_regs.h:995
QM_FPR_0
FPR 0.
Definition: qm_soc_regs.h:1266
CLK_PERIPH_I2C_M1_REGISTER
I2C Master 1 Clock Gate Enable.
Definition: qm_soc_regs.h:1694
CLK_PERIPH_UARTA_REGISTER
UARTA Clock Gate Enable.
Definition: qm_soc_regs.h:1384
qm_spi_context_t::baudr
uint32_t baudr
Baud Rate Select.
Definition: qm_soc_regs.h:1074
QM_DMA_CHANNEL_5
DMA channel id for channel 5.
Definition: qm_soc_regs.h:1727
qm_dma_context_t::cfg_high
uint32_t cfg_high
Channel Configuration Upper.
Definition: qm_soc_regs.h:1915
qm_lapic_reg_t::lvtpmcr
QM_RW apic_reg_pad_t lvtpmcr
Perfmon counter vector.
Definition: qm_soc_regs.h:246
qm_dma_int_reg_t
DMA interrupt register map.
Definition: qm_soc_regs.h:1583
qm_mpr_id_t
qm_mpr_id_t
Definition: qm_soc_regs.h:1286
qm_scss_pmux_reg_t
Pin MUX register map.
Definition: qm_soc_regs.h:324
qm_lapic_reg_t::esr
QM_RW apic_reg_pad_t esr
Error status.
Definition: qm_soc_regs.h:240
qm_gpio_context_t::gpio_swporta_ddr
uint32_t gpio_swporta_ddr
Port A Data Direction.
Definition: qm_soc_regs.h:1401
QM_FPR_2
FPR 2.
Definition: qm_soc_regs.h:1268
qm_gpio_context_t::gpio_inttype_level
uint32_t gpio_inttype_level
Interrupt Type.
Definition: qm_soc_regs.h:1405
qm_lapic_reg_t::ppr
QM_RW apic_reg_pad_t ppr
Processor priority.
Definition: qm_soc_regs.h:231
qm_flash_context_t::ctrl
uint32_t ctrl
Control Register.
Definition: qm_soc_regs.h:1470
qm_usb_reg_t::daint
QM_R uint32_t daint
Device Interrupt Register.
Definition: qm_soc_regs.h:2019
qm_uart_context_t::mcr
uint32_t mcr
Modem Control.
Definition: qm_soc_regs.h:998
qm_i2c_reg_t
I2C register map.
Definition: qm_soc_regs.h:864
DMA_HW_IF_SPI_MASTER_0_RX
SPI_Master_0_RX.
Definition: qm_soc_regs.h:1499
DMA_HW_IF_SPI_SLAVE_TX
SPI_Slave_TX.
Definition: qm_soc_regs.h:1500
qm_scss_pmu_reg_t::pm1c
QM_RW uint32_t pm1c
Power management 1 control.
Definition: qm_soc_regs.h:347
qm_scss_pmu_reg_t::plat3p3_vr
QM_RW uint32_t plat3p3_vr
Platform 3p3 voltage regulator.
Definition: qm_soc_regs.h:350
qm_pic_timer_context_t::timer_icr
uint32_t timer_icr
Initial Count Register.
Definition: qm_soc_regs.h:284
CLK_PERIPH_GPIO_DB
GPIO Debounce Clock Enable.
Definition: qm_soc_regs.h:1375
qm_dma_context_t::llp_low
uint32_t llp_low
Channel Linked List Pointer.
Definition: qm_soc_regs.h:1916
qm_pic_timer_context_t
PIC TIMER context type.
Definition: qm_soc_regs.h:283
qm_lapic_reg_t::lvtlint0
QM_RW apic_reg_pad_t lvtlint0
Local interrupt 0 vector.
Definition: qm_soc_regs.h:247
qm_lapic_reg_t::apr
QM_RW apic_reg_pad_t apr
Arbitration priority.
Definition: qm_soc_regs.h:230
DMA_HW_IF_UART_B_RX
UART_B_RX.
Definition: qm_soc_regs.h:1497
QM_DMA_CHANNEL_2
DMA channel id for channel 2.
Definition: qm_soc_regs.h:1724
qm_dma_t
qm_dma_t
DMA instances.
Definition: qm_soc_regs.h:1480
DMA_HW_IF_UART_B_TX
UART_B_TX.
Definition: qm_soc_regs.h:1496
qm_gpio_context_t::gpio_ls_sync
uint32_t gpio_ls_sync
Synchronization Level.
Definition: qm_soc_regs.h:1408
qm_i2c_context_t::tx_tl
uint32_t tx_tl
Receive FIFO threshold register.
Definition: qm_soc_regs.h:1271
qm_usb_in_ep_reg_t
USB register map.
Definition: qm_soc_regs.h:1962
qm_i2c_context_t::fs_scl_hcnt
uint32_t fs_scl_hcnt
Fast Speed Clock SCL High Count.
Definition: qm_soc_regs.h:1265
qm_uart_context_t
UART context to be saved between sleep/resume.
Definition: qm_soc_regs.h:993
DMA_HW_IF_I2S_PLAYBACK
I2S_Playback channel.
Definition: qm_soc_regs.h:1745
qm_flash_context_t::tmg_ctrl
uint32_t tmg_ctrl
Flash Timing Control Register.
Definition: qm_soc_regs.h:1468
qm_gpio_context_t::gpio_intmask
uint32_t gpio_intmask
Interrupt Mask.
Definition: qm_soc_regs.h:1404
qm_usb_reg_t::gotgint
QM_RW uint32_t gotgint
OTG Interrupt.
Definition: qm_soc_regs.h:1989
CLK_PERIPH_I2C_M1
I2C Master 1 Clock Enable.
Definition: qm_soc_regs.h:1673
qm_flash_t
qm_flash_t
Number of Flash controllers.
Definition: qm_soc_regs.h:1141
qm_i2c_context_t::con
uint32_t con
Control Register.
Definition: qm_soc_regs.h:1261
CLK_PERIPH_PWM_REGISTER
PWM Clock Gate Enable.
Definition: qm_soc_regs.h:1378
qm_mpr_context_t
MPR context type.
Definition: qm_soc_regs.h:1629
QM_DMA_CHANNEL_NUM
Number of DMA channels.
Definition: qm_soc_regs.h:1489
CLK_PERIPH_I2S
I2S Clock Enable.
Definition: qm_soc_regs.h:1679
qm_mailbox_t::ch_ctrl
QM_RW uint32_t ch_ctrl
Channel Control Word.
Definition: qm_soc_regs.h:635
qm_spi_context_t::ser
uint32_t ser
Slave Enable Register.
Definition: qm_soc_regs.h:1073
QM_FPR_1
FPR 1.
Definition: qm_soc_regs.h:1267
qm_usb_reg_t::gdfifocfg
QM_RW uint32_t gdfifocfg
Global DFIFO Configuration.
Definition: qm_soc_regs.h:2005
QM_MPR_NUM
Number of Memory Protection Regions.
Definition: qm_soc_regs.h:1291
qm_lapic_reg_t::timer_icr
QM_RW apic_reg_pad_t timer_icr
Timer initial count.
Definition: qm_soc_regs.h:250
qm_scss_pmu_reg_t::p_lvl2
QM_RW uint32_t p_lvl2
Processor level 2.
Definition: qm_soc_regs.h:345
qm_mailbox_reg_t::mbox_chall_sts
QM_RW uint32_t mbox_chall_sts
All channel status.
Definition: qm_soc_regs.h:643
qm_lapic_reg_t::timer_dcr
QM_RW apic_reg_pad_t timer_dcr
Timer divide configuration.
Definition: qm_soc_regs.h:253
qm_usb_reg_t::doepmsk
QM_RW uint32_t doepmsk
OUT EP Common Interrupt Mask.
Definition: qm_soc_regs.h:2018
qm_dma_context_t
DMA context type.
Definition: qm_soc_regs.h:1911
CLK_PERIPH_ALL
Quark D2000 peripherals Enable.
Definition: qm_soc_regs.h:1390
CLK_PERIPH_RTC_REGISTER
RTC Clock Gate Enable.
Definition: qm_soc_regs.h:1377
QM_DMA_CHANNEL_1
DMA channel id for channel 1.
Definition: qm_soc_regs.h:1488
qm_uart_reg_t
UART register map.
Definition: qm_soc_regs.h:658
qm_scss_ccu_reg_t::usb_pll_cfg0
QM_RW uint32_t usb_pll_cfg0
USB Phase lock look configuration.
Definition: qm_soc_regs.h:42
qm_lapic_reg_t::lvtlint1
QM_RW apic_reg_pad_t lvtlint1
Local interrupt 1 vector.
Definition: qm_soc_regs.h:248
qm_scss_pmu_reg_t::host_vr
QM_RW uint32_t host_vr
Host Voltage Regulator.
Definition: qm_soc_regs.h:352
qm_fpr_context_t
FPR context type.
Definition: qm_soc_regs.h:1591
qm_uart_t
qm_uart_t
Number of UART controllers.
Definition: qm_soc_regs.h:655
QM_MPR_0
Memory Protection Region 0.
Definition: qm_soc_regs.h:1287
QM_MPR_3
Memory Protection Region 3.
Definition: qm_soc_regs.h:1290
qm_usb_reg_t::gintmsk
QM_RW uint32_t gintmsk
Interrupt Mask.
Definition: qm_soc_regs.h:1994
qm_uart_context_t::htx
uint32_t htx
Halt Transmission.
Definition: qm_soc_regs.h:1000
qm_spi_context_t
SPI context type.
Definition: qm_soc_regs.h:1071
qm_i2c_context_t::fs_scl_lcnt
uint32_t fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
Definition: qm_soc_regs.h:1266
CLK_PERIPH_CLK
Peripheral Clock Enable.
Definition: qm_soc_regs.h:1370
DMA_HW_IF_SPI_MASTER_1_RX
SPI_Master_1_RX.
Definition: qm_soc_regs.h:1742
qm_lapic_reg_t::lvtts
QM_RW apic_reg_pad_t lvtts
Thermal sensor vector.
Definition: qm_soc_regs.h:245
qm_gpio_context_t::gpio_int_polarity
uint32_t gpio_int_polarity
Interrupt Polarity.
Definition: qm_soc_regs.h:1406
CLK_PERIPH_REGISTER
Peripheral Clock Gate Enable.
Definition: qm_soc_regs.h:1369
qm_dma_context_t::cfg_low
uint32_t cfg_low
Channel Configuration Lower.
Definition: qm_soc_regs.h:1914
QM_FPR_3
FPR 3.
Definition: qm_soc_regs.h:1269
qm_pwm_context_t
PWM context type.
Definition: qm_soc_regs.h:702
qm_lapic_reg_t::lvtcmci
QM_RW apic_reg_pad_t lvtcmci
Corrected Machine Check vector.
Definition: qm_soc_regs.h:242
qm_dma_context_t::ctrl_low
uint32_t ctrl_low
Channel Control Lower.
Definition: qm_soc_regs.h:1913
qm_usb_out_ep_reg_t
OUT Endpoint Registers.
Definition: qm_soc_regs.h:1974
qm_scss_ccu_reg_t::ccu_ss_periph_clk_gate_ctl
QM_RW uint32_t ccu_ss_periph_clk_gate_ctl
Sensor Subsystem peripheral clock gate control.
Definition: qm_soc_regs.h:52
qm_spi_controllers
qm_spi_reg_t * qm_spi_controllers[QM_SPI_NUM]
Extern qm_spi_reg_t* array declared at qm_soc_regs.h .
Definition: qm_spi.c:66
qm_pwm_reg_t
PWM / Timer register map.
Definition: qm_soc_regs.h:398
CLK_PERIPH_SPI_M0
SPI Master 0 Clock Enable.
Definition: qm_soc_regs.h:1373
CLK_PERIPH_SPI_M1_REGISTER
SPI Master 1 Clock Gate Enable.
Definition: qm_soc_regs.h:1686
qm_usb_reg_t
USB Register block type.
Definition: qm_soc_regs.h:1987
CLK_PERIPH_WDT_REGISTER
Watchdog Clock Enable.
Definition: qm_soc_regs.h:1376
qm_dma_misc_reg_t
DMA miscellaneous register map.
Definition: qm_soc_regs.h:1634
qm_scss_info_reg_t
Information register map.
Definition: qm_soc_regs.h:357
qm_lapic_reg_t::version
QM_RW apic_reg_pad_t version
LAPIC version.
Definition: qm_soc_regs.h:227
CLK_PERIPH_GPIO_REGISTER
GPIO Clock Gate Enable.
Definition: qm_soc_regs.h:1379
qm_usb_reg_t::ghwcfg4
QM_R uint32_t ghwcfg4
HW config 4.
Definition: qm_soc_regs.h:2004
qm_scss_ccu_reg_t
System Core register map.
Definition: qm_soc_regs.h:30
qm_pwm_context_t::loadcount
uint32_t loadcount
Load Count 1.
Definition: qm_soc_regs.h:704
qm_usb_reg_t::dthrctl
QM_RW uint32_t dthrctl
Device Threshold Ctrl.
Definition: qm_soc_regs.h:2024
qm_usb_reg_t::dvbusdis
QM_RW uint32_t dvbusdis
VBUS discharge time register.
Definition: qm_soc_regs.h:2022
CLK_PERIPH_I2S_REGISTER
I2S Clock Gate Enable.
Definition: qm_soc_regs.h:1696
qm_scss_ss_reg_t::ss_sts
QM_RW uint32_t ss_sts
Sensor Subsystem status.
Definition: qm_soc_regs.h:410
qm_flash_context_t
Flash context type.
Definition: qm_soc_regs.h:1466
DMA_HW_IF_UART_A_RX
UART_A_RX.
Definition: qm_soc_regs.h:1495
qm_usb_reg_t::gnptxfsiz
QM_R uint32_t gnptxfsiz
Non-periodic Transmit FIFO Size.
Definition: qm_soc_regs.h:1998
qm_rtc_reg_t
RTC register map.
Definition: qm_soc_regs.h:821
qm_aonc_reg_t
Always-on Counter Controller register map.
Definition: qm_soc_regs.h:258
qm_usb_reg_t::gahbcfg
QM_RW uint32_t gahbcfg
AHB Configuration.
Definition: qm_soc_regs.h:1990
qm_pic_timer_context_t::timer_dcr
uint32_t timer_dcr
Divide Configuration Register.
Definition: qm_soc_regs.h:285
qm_gpio_context_t::gpio_int_bothedge
uint32_t gpio_int_bothedge
Interrupt both edge type.
Definition: qm_soc_regs.h:1409
qm_scss_gp_reg_t
General Purpose register map.
Definition: qm_soc_regs.h:144
qm_usb_reg_t::dctl
QM_RW uint32_t dctl
Device control.
Definition: qm_soc_regs.h:2014
qm_spi_reg_t
SPI register map.
Definition: qm_soc_regs.h:712
qm_usb_reg_t::gintsts
QM_RW uint32_t gintsts
Interrupt Status.
Definition: qm_soc_regs.h:1993
qm_spi_t
qm_spi_t
Number of SPI controllers.
Definition: qm_soc_regs.h:709
QM_DMA_CHANNEL_6
DMA channel id for channel 6.
Definition: qm_soc_regs.h:1728
qm_flash_reg_t
Flash register map.
Definition: qm_soc_regs.h:1144
qm_scss_pmu_reg_t::pmnetcs
QM_RW uint32_t pmnetcs
Power Management Network (PMNet) Control and Status.
Definition: qm_soc_regs.h:355
qm_rtc_t
qm_rtc_t
Number of RTC controllers.
Definition: qm_soc_regs.h:818
qm_gpio_reg_t::gpio_swporta_ctl
QM_RW uint32_t gpio_swporta_ctl
Port A Data Source.
Definition: qm_soc_regs.h:1372
qm_lapic_reg_t::tpr
QM_RW apic_reg_pad_t tpr
Task priority.
Definition: qm_soc_regs.h:229
DMA_HW_IF_SPI_MASTER_1_TX
SPI_Master_1_TX.
Definition: qm_soc_regs.h:1741
qm_gpio_reg_t
GPIO register map.
Definition: qm_soc_regs.h:1017
qm_usb_reg_t::ghwcfg1
QM_R uint32_t ghwcfg1
HW config - Endpoint direction.
Definition: qm_soc_regs.h:2001
qm_lapic_reg_t::id
QM_RW apic_reg_pad_t id
LAPIC ID.
Definition: qm_soc_regs.h:226
qm_usb_reg_t::ghwcfg2
QM_R uint32_t ghwcfg2
HW config 2.
Definition: qm_soc_regs.h:2002
QM_DMA_0
DMA controller id.
Definition: qm_soc_regs.h:1481
qm_usb_reg_t::dsts
QM_RW uint32_t dsts
Device Status.
Definition: qm_soc_regs.h:2015
qm_uart_context_t::scr
uint32_t scr
Scratchpad.
Definition: qm_soc_regs.h:999
qm_scss_mem_reg_t::mem_ctrl
QM_RW uint32_t mem_ctrl
Memory control.
Definition: qm_soc_regs.h:170
qm_mailbox_reg_t
Mailbox register map.
Definition: qm_soc_regs.h:641
qm_mailbox_t::ch_sts
QM_RW uint32_t ch_sts
Channel status.
Definition: qm_soc_regs.h:637
qm_gpio
qm_gpio_reg_t * qm_gpio[QM_GPIO_NUM]
GPIO register block.
Definition: qm_gpio.c:14
CLK_PERIPH_UARTB_REGISTER
UARTB Clock Gate Enable.
Definition: qm_soc_regs.h:1385
qm_usb_reg_t::grxstsr
QM_R uint32_t grxstsr
Receive Status Read/Pop.
Definition: qm_soc_regs.h:1995
qm_gpio_context_t::gpio_inten
uint32_t gpio_inten
Interrupt Enable.
Definition: qm_soc_regs.h:1403
qm_pwm_id_t
qm_pwm_id_t
PWM ID type.
Definition: qm_soc_regs.h:386
qm_i2c_context_t::ss_scl_lcnt
uint32_t ss_scl_lcnt
Standard Speed Clock SCL Low Count.
Definition: qm_soc_regs.h:1264
qm_i2c_context_t::ss_scl_hcnt
uint32_t ss_scl_hcnt
Standard Speed Clock SCL High Count.
Definition: qm_soc_regs.h:1263
qm_lapic_reg_t::lvterr
QM_RW apic_reg_pad_t lvterr
Error vector.
Definition: qm_soc_regs.h:249
DMA_HW_IF_UART_A_TX
UART_A_TX.
Definition: qm_soc_regs.h:1494
DMA_HW_IF_I2C_MASTER_0_RX
I2C_Master_0_RX.
Definition: qm_soc_regs.h:1503
qm_scss_cmp_reg_t
Comparator register map.
Definition: qm_soc_regs.h:181
qm_lapic_reg_t
APIC register block type.
Definition: qm_soc_regs.h:224
QM_DMA_NUM
Number of DMA controllers.
Definition: qm_soc_regs.h:1482
QM_DMA_CHANNEL_0
DMA channel id for channel 0.
Definition: qm_soc_regs.h:1487
DMA_HW_IF_I2C_MASTER_0_TX
I2C_Master_0_TX.
Definition: qm_soc_regs.h:1502
CLK_PERIPH_I2C_M0_REGISTER
I2C Master 0 Clock Gate Enable.
Definition: qm_soc_regs.h:1386
QM_DMA_CHANNEL_3
DMA channel id for channel 3.
Definition: qm_soc_regs.h:1725
qm_mailbox_t
Mailbox register structure.
Definition: qm_soc_regs.h:634
qm_uart_context_t::dll
uint32_t dll
Divisor Latch Low.
Definition: qm_soc_regs.h:996
CLK_PERIPH_SPI_S_REGISTER
SPI Slave Clock Gate Enable.
Definition: qm_soc_regs.h:1382
qm_i2c_context_t::ic_intr_mask
uint32_t ic_intr_mask
I2C Interrupt Mask.
Definition: qm_soc_regs.h:1269
CLK_PERIPH_I2C_M0
I2C Master 0 Clock Enable.
Definition: qm_soc_regs.h:1371
QM_DMA_CHANNEL_7
DMA channel id for channel 7.
Definition: qm_soc_regs.h:1729
qm_i2c_context_t::enable
uint32_t enable
Enable.
Definition: qm_soc_regs.h:1267
qm_lapic_reg_t::timer_ccr
QM_RW apic_reg_pad_t timer_ccr
Timer current count.
Definition: qm_soc_regs.h:251
QM_MPR_2
Memory Protection Region 2.
Definition: qm_soc_regs.h:1289
qm_gpio_context_t::gpio_swporta_dr
uint32_t gpio_swporta_dr
Port A Data.
Definition: qm_soc_regs.h:1400
qm_scss_mem_reg_t
Memory Control register map.
Definition: qm_soc_regs.h:169
qm_gpio_context_t
GPIO context type.
Definition: qm_soc_regs.h:1399
qm_pwm_context_t::loadcount2
uint32_t loadcount2
Load Count 2.
Definition: qm_soc_regs.h:705
CLK_PERIPH_SPI_M0_REGISTER
SPI Master 0 Clock Gate Enable.
Definition: qm_soc_regs.h:1380
qm_gpio_t
qm_gpio_t
Number of GPIO controllers.
Definition: qm_soc_regs.h:1014
qm_fpr_id_t
qm_fpr_id_t
FPR register map.
Definition: qm_soc_regs.h:1265
qm_dma_chan_reg_t
DMA channel register map.
Definition: qm_soc_regs.h:1507
qm_i2c_t
qm_i2c_t
Number of I2C controllers.
Definition: qm_soc_regs.h:861
DMA_HW_IF_I2C_MASTER_1_RX
I2C_Master_1_RX.
Definition: qm_soc_regs.h:1750
qm_gpio_context_t::gpio_debounce
uint32_t gpio_debounce
Debounce Enable.
Definition: qm_soc_regs.h:1407
qm_usb_reg_t::dcfg
QM_RW uint32_t dcfg
Device config.
Definition: qm_soc_regs.h:2013
qm_usb_reg_t::grxfsiz
QM_R uint32_t grxfsiz
Receive FIFO Size.
Definition: qm_soc_regs.h:1997
qm_i2c
qm_i2c_reg_t * qm_i2c[QM_I2C_NUM]
I2C register block.
Definition: qm_i2c.c:20
qm_scss_gp_reg_t::rev
QM_RW uint32_t rev
Revision Register.
Definition: qm_soc_regs.h:141
DMA_HW_IF_SPI_MASTER_0_TX
SPI_Master_0_TX.
Definition: qm_soc_regs.h:1498
qm_i2c_context_t
I2C context to be saved between sleep/resume.
Definition: qm_soc_regs.h:1260
qm_mpr_reg_t
Memory Protection Region register map.
Definition: qm_soc_regs.h:1295
DMA_HW_IF_SPI_SLAVE_RX
SPI_Slave_RX.
Definition: qm_soc_regs.h:1501
DMA_HW_IF_I2C_MASTER_1_TX
I2C_Master_1_TX.
Definition: qm_soc_regs.h:1749
qm_usb_reg_t::diepempmsk
QM_RW uint32_t diepempmsk
IN EP FIFO Empty Intr Mask.
Definition: qm_soc_regs.h:2025
QM_DMA_CHANNEL_4
DMA channel id for channel 4.
Definition: qm_soc_regs.h:1726
qm_usb_reg_t::gsnpsid
QM_R uint32_t gsnpsid
Synopsys ID.
Definition: qm_soc_regs.h:2000
qm_pwm_t
qm_pwm_t
Number of PWM / Timer controllers.
Definition: qm_soc_regs.h:383
qm_spi_context_t::ctrlr0
uint32_t ctrlr0
Control Register 0.
Definition: qm_soc_regs.h:1072
qm_scss_ss_reg_t
Sensor Subsystem register map.
Definition: qm_soc_regs.h:408
DMA_HW_IF_I2S_CAPTURE
I2S_Capture channel.
Definition: qm_soc_regs.h:1746
qm_usb_t
qm_usb_t
Number of USB controllers.
Definition: qm_soc_regs.h:1944
qm_scss_peripheral_reg_t::usb_phy_cfg0
QM_RW uint32_t usb_phy_cfg0
USB Configuration.
Definition: qm_soc_regs.h:481
qm_dma_context_t::misc_cfg_low
uint32_t misc_cfg_low
DMA Configuration.
Definition: qm_soc_regs.h:1918
qm_usb_reg_t::gotgctl
QM_RW uint32_t gotgctl
OTG Control.
Definition: qm_soc_regs.h:1988
qm_usb_reg_t::diepmsk
QM_RW uint32_t diepmsk
IN EP Common Interrupt Mask.
Definition: qm_soc_regs.h:2017
qm_usb_reg_t::gusbcfg
QM_RW uint32_t gusbcfg
USB Configuration.
Definition: qm_soc_regs.h:1991
qm_usb_reg_t::dvbuspulse
QM_RW uint32_t dvbuspulse
Device VBUS discharge time.
Definition: qm_soc_regs.h:2023
qm_i2c_context_t::fs_spklen
uint32_t fs_spklen
SS and FS Spike Suppression Limit.
Definition: qm_soc_regs.h:1268
QM_MPR_1
Memory Protection Region 1.
Definition: qm_soc_regs.h:1288
qm_dma_channel_id_t
qm_dma_channel_id_t
DMA channel IDs.
Definition: qm_soc_regs.h:1486
qm_scss_pmu_reg_t::plat1p8_vr
QM_RW uint32_t plat1p8_vr
Platform 1p8 voltage regulator.
Definition: qm_soc_regs.h:351
clk_periph_t
clk_periph_t
Peripheral clock register map.
Definition: qm_soc_regs.h:1368
qm_gpio_context_t::gpio_swporta_ctl
uint32_t gpio_swporta_ctl
Port A Data Source.
Definition: qm_soc_regs.h:1402
qm_pic_timer_context_t::lvttimer
uint32_t lvttimer
Timer Entry in Local Vector Table.
Definition: qm_soc_regs.h:286
qm_scss_pmu_reg_t
Power Management register map.
Definition: qm_soc_regs.h:210
qm_lapic_reg_t::ldr
QM_RW apic_reg_pad_t ldr
Logical destination.
Definition: qm_soc_regs.h:234
qm_dma_handshake_interface_t
qm_dma_handshake_interface_t
DMA hardware handshake interfaces.
Definition: qm_soc_regs.h:1493
qm_usb_reg_t::daintmsk
QM_RW uint32_t daintmsk
Device Interrupt Mask Register.
Definition: qm_soc_regs.h:2020
qm_lapic_reg_t::dfr
QM_RW apic_reg_pad_t dfr
Destination format.
Definition: qm_soc_regs.h:235
qm_scss_ss_reg_t::ss_cfg
QM_RW uint32_t ss_cfg
Sensor Subsystem Configuration.
Definition: qm_soc_regs.h:409
qm_pwm_channel_t
PWM / Timer channel register map.
Definition: qm_soc_regs.h:389
qm_uart_context_t::lcr
uint32_t lcr
Line Control.
Definition: qm_soc_regs.h:997
CLK_PERIPH_SPI_S
SPI Slave Clock Enable.
Definition: qm_soc_regs.h:1372
qm_wdt_t
qm_wdt_t
Number of WDT controllers.
Definition: qm_soc_regs.h:467
qm_lapic_reg_t::rrd
QM_RW apic_reg_pad_t rrd
Remote read.
Definition: qm_soc_regs.h:233
qm_wdt_reg_t
Watchdog timer register map.
Definition: qm_soc_regs.h:470
qm_i2c_context_t::sar
uint32_t sar
Slave Address.
Definition: qm_soc_regs.h:1262
qm_uart_context_t::dlf
uint32_t dlf
Divisor Latch Fraction.
Definition: qm_soc_regs.h:1001
qm_scss_pmu_reg_t::vr_lock
QM_RW uint32_t vr_lock
Voltage regulator lock.
Definition: qm_soc_regs.h:363
qm_scss_peripheral_reg_t
Peripheral Registers register map.
Definition: qm_soc_regs.h:301
qm_lapic_reg_t::svr
QM_RW apic_reg_pad_t svr
Spurious vector.
Definition: qm_soc_regs.h:236
qm_scss_pmu_reg_t::slp_cfg
QM_RW uint32_t slp_cfg
Sleeping Configuration.
Definition: qm_soc_regs.h:353
CLK_PERIPH_SPI_M1
SPI Master 1 Clock Enable.
Definition: qm_soc_regs.h:1676
qm_irq_context_t
SS IRQ context type.
Definition: qm_sensor_regs.h:96
qm_usb_reg_t::grxstsp
QM_R uint32_t grxstsp
Receive Status Read/Pop.
Definition: qm_soc_regs.h:1996
qm_uart_context_t::ier
uint32_t ier
Interrupt Enable Register.
Definition: qm_soc_regs.h:994
qm_scss_gp_reg_t::id
QM_RW uint32_t id
Identification Register.
Definition: qm_soc_regs.h:140
qm_usb_reg_t::ghwcfg3
QM_R uint32_t ghwcfg3
HW config 3.
Definition: qm_soc_regs.h:2003
qm_usb_reg_t::grstctl
QM_RW uint32_t grstctl
Reset Register.
Definition: qm_soc_regs.h:1992
qm_aonc_t
qm_aonc_t
Number of Always-on counter controllers.
Definition: qm_soc_regs.h:255
qm_lapic_reg_t::lvttimer
QM_RW apic_reg_pad_t lvttimer
Timer vector.
Definition: qm_soc_regs.h:244
qm_lapic_reg_t::eoi
QM_RW apic_reg_pad_t eoi
End of interrupt.
Definition: qm_soc_regs.h:232
CLK_PERIPH_GPIO_INTERRUPT
GPIO Interrupt Clock Enable.
Definition: qm_soc_regs.h:1374
qm_pwm_context_t::controlreg
uint32_t controlreg
Control Register.
Definition: qm_soc_regs.h:706