Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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power_states.c
1 /*
2 * {% copyright %}
3 */
4
5 #include "power_states.h"
6 #include "clk.h"
7 #include "qm_comparator.h"
8 #include "qm_isr.h"
9 #include "qm_adc.h"
10 #include "qm_flash.h"
11 #include "soc_watch.h"
12
13 typedef struct {
14 uint32_t ac_power_save;
15 uint32_t clk_gate_save;
16 uint32_t sys_clk_ctl_save;
17 uint32_t osc0_cfg_save;
18 uint32_t osc1_cfg_save;
19 uint32_t adc_mode_save;
20 uint32_t aon_vr_save;
21 uint32_t flash_tmg_save;
22 uint32_t ext_clock_save;
23 uint32_t lp_clk_save;
24 uint32_t pmux_slew_save;
25 } power_context_t;
26
27 static power_context_t power_context;
28
29 void qm_power_cpu_halt(void)
30 {
31 SOC_WATCH_LOG_EVENT(SOCW_EVENT_HALT, 0);
32 /*
33 * STI sets the IF flag. After the IF flag is set,
34 * the core begins responding to external,
35 * maskable interrupts after the next instruction is executed.
36 * When this function is called with interrupts disabled,
37 * this guarantees that an interrupt is caught only
38 * after the processor has transitioned into HLT.
39 */
40 __asm__ __volatile__("sti\n\t"
41 "hlt\n\t");
42 }
43
44 static void clear_all_pending_interrupts(void)
45 {
46 /* Clear comparator interrupts. */
47 QM_SCSS_CMP->cmp_stat_clr = -1;
48
49 /* Clear RTC interrupts. */
50 QM_RTC[QM_RTC_0]->rtc_eoi;
51
52 /* Clear timers interrupt flag. */
53 QM_PWM[QM_PWM_0]->timerseoi;
54
55 /* Clear GPIO interrupts. */
56 QM_GPIO[QM_GPIO_0]->gpio_porta_eoi = -1;
57 }
58
59 void qm_power_soc_sleep(void)
60 {
61 /* Save register values. */
62 power_context.ac_power_save = QM_SCSS_CMP->cmp_pwr;
63 power_context.clk_gate_save = QM_SCSS_CCU->ccu_periph_clk_gate_ctl;
64 power_context.sys_clk_ctl_save = QM_SCSS_CCU->ccu_sys_clk_ctl;
65 power_context.osc0_cfg_save = QM_SCSS_CCU->osc0_cfg1;
66 power_context.adc_mode_save = QM_ADC->adc_op_mode;
67 power_context.flash_tmg_save = QM_FLASH[QM_FLASH_0]->tmg_ctrl;
68 power_context.lp_clk_save = QM_SCSS_CCU->ccu_lp_clk_ctl;
69
70 QM_SCSS_GP->gps0 |= QM_GPS0_POWER_STATE_SLEEP;
71
72 /* Clear any pending interrupts. */
73 clear_all_pending_interrupts();
74
75 qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_PWR_DOWN);
76
77 /* Turn off high power comparators. */
78 QM_SCSS_CMP->cmp_pwr &= QM_AC_HP_COMPARATORS_MASK;
79
80 /*
81 * Program WAKE_MASK.WAKE_MASK[31:0],
82 * CCU_LP_CLK_CTL.WAKE_PROBE_MODE_MASK registers identical to Interrupt
83 * Mask registers.
84 */
85 QM_SCSS_CCU->ccu_lp_clk_ctl &= ~QM_WAKE_PROBE_MODE_MASK;
86 /* Enable all wake sources as interrupts. */
87 QM_SCSS_CCU->wake_mask = 0;
88
89 /*
90 * Ensure that powering down of oscillators is delayed by hardware until
91 * core executes HALT instruction.
92 */
93 /* HYB_OSC_PD_LATCH_EN = 0, RTC_OSC_PD_LATCH_EN=0 */
94 QM_SCSS_CCU->ccu_lp_clk_ctl &=
95 ~(QM_HYB_OSC_PD_LATCH_EN | QM_RTC_OSC_PD_LATCH_EN);
96
97 /* Ensure that at exit, hardware will switch system clock to Hybrid
98 * oscillator clock so as to minimize exit latency by running at higher
99 * frequency than RTC clock.
100 */
101 /* CCU_LP_CLK_CTL.CCU_EXIT_TO_HYBOSC */
102 QM_SCSS_CCU->ccu_lp_clk_ctl |=
103 QM_CCU_EXIT_TO_HYBOSC | QM_CCU_MEM_HALT_EN | QM_CCU_CPU_HALT_EN;
104 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_LP_CLK_CTL);
105
106 /*
107 * Only the following peripherals can be used as a wakeup source:
108 * - GPIO Interrupts
109 * - AON timers
110 * - RTC
111 * - low power comparators
112 */
113 clk_periph_disable(
114 CLK_PERIPH_I2C_M0 | CLK_PERIPH_SPI_S | CLK_PERIPH_SPI_M0 |
115 CLK_PERIPH_GPIO_DB | CLK_PERIPH_WDT_REGISTER |
116 CLK_PERIPH_PWM_REGISTER | CLK_PERIPH_GPIO_REGISTER |
117 CLK_PERIPH_SPI_M0_REGISTER | CLK_PERIPH_SPI_S_REGISTER |
118 CLK_PERIPH_UARTA_REGISTER | CLK_PERIPH_UARTB_REGISTER |
119 CLK_PERIPH_I2C_M0_REGISTER);
120
121 /* Set system clock source to hyb osc, 4 MHz, scaled to 512 kHz. */
122 clk_sys_set_mode(CLK_SYS_HYB_OSC_4MHZ, CLK_SYS_DIV_8);
123
124 /* Set the RAR to retention mode. */
125 qm_rar_set_mode(QM_RAR_RETENTION);
126
127 /*
128 * If wake source is any of AON Timer, RTC, GPIO interrupt, program
129 * CCU_SYS_CLK_CTL.CCU_SYS_CLK_SEL to RTC Oscillator.
130 */
131 /* Enter SoC sleep mode. */
132 qm_power_cpu_halt();
133 }
134
135 void qm_power_soc_sleep_restore(void)
136 {
137 /* From here on, restore the SoC to an active state. */
138 /* Set the RAR to normal mode. */
139 qm_rar_set_mode(QM_RAR_NORMAL);
140
141 /*
142 * Since we are running below 4MHz, 0 wait states are configured.
143 * If the previous frequency was > 4MHz, 0 wait states will
144 * violate the flash timings.
145 * In the worst case scenario, when switching back to 32MHz,
146 * 2 wait states will be restored.
147 * This setting will be too conservative until the frequency has been
148 * restored.
149 */
150 QM_FLASH[QM_FLASH_0]->tmg_ctrl = power_context.flash_tmg_save;
151
152 /* Restore all previous values. */
153 QM_SCSS_CCU->ccu_sys_clk_ctl = power_context.sys_clk_ctl_save;
154 /* Re-apply clock divider values. DIV_EN must go 0 -> 1. */
155 QM_SCSS_CCU->ccu_sys_clk_ctl &=
156 ~(QM_CCU_SYS_CLK_DIV_EN | QM_CCU_RTC_CLK_DIV_EN);
157 QM_SCSS_CCU->ccu_sys_clk_ctl |=
158 QM_CCU_SYS_CLK_DIV_EN | QM_CCU_RTC_CLK_DIV_EN;
159
160 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_SYS_CLK_CTL);
161
162 /* Wait for the XTAL or SI oscillator to stabilise. */
163 while (!(QM_SCSS_CCU->osc0_stat1 &
164 (QM_OSC0_LOCK_SI | QM_OSC0_LOCK_XTAL))) {
165 };
166
167 /* Restore original clocking, ADC, analog comparator states. */
168 QM_SCSS_CCU->osc0_cfg1 = power_context.osc0_cfg_save;
169 QM_SCSS_CCU->ccu_periph_clk_gate_ctl = power_context.clk_gate_save;
170 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_OSC0_CFG1);
171 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER,
172 SOCW_REG_CCU_PERIPH_CLK_GATE_CTL);
173 QM_SCSS_CMP->cmp_pwr = power_context.ac_power_save;
174 QM_ADC->adc_op_mode = power_context.adc_mode_save;
175 QM_SCSS_CCU->ccu_lp_clk_ctl = power_context.lp_clk_save;
176
177 QM_SCSS_GP->gps0 &= ~QM_GPS0_POWER_STATE_SLEEP;
178 }
179
180 void qm_power_soc_deep_sleep(const qm_power_wake_event_t wake_event)
181 {
182 /* Save register values. */
183 power_context.ac_power_save = QM_SCSS_CMP->cmp_pwr;
184 power_context.clk_gate_save = QM_SCSS_CCU->ccu_periph_clk_gate_ctl;
185 power_context.sys_clk_ctl_save = QM_SCSS_CCU->ccu_sys_clk_ctl;
186 power_context.osc0_cfg_save = QM_SCSS_CCU->osc0_cfg1;
187 power_context.osc1_cfg_save = QM_SCSS_CCU->osc1_cfg0;
188 power_context.adc_mode_save = QM_ADC->adc_op_mode;
189 power_context.aon_vr_save = QM_SCSS_PMU->aon_vr;
190 power_context.flash_tmg_save = QM_FLASH[QM_FLASH_0]->tmg_ctrl;
191 power_context.pmux_slew_save = QM_SCSS_PMUX->pmux_slew[0];
192 power_context.ext_clock_save = QM_SCSS_CCU->ccu_ext_clock_ctl;
193 power_context.lp_clk_save = QM_SCSS_CCU->ccu_lp_clk_ctl;
194
195 QM_SCSS_GP->gps0 |= QM_GPS0_POWER_STATE_DEEP_SLEEP;
196
197 /* Clear any pending interrupts. */
198 clear_all_pending_interrupts();
199
200 /*
201 * Clear the wake mask bits. Default behaviour is to wake from GPIO /
202 * comparator.
203 */
204 switch (wake_event) {
205 case QM_POWER_WAKE_FROM_RTC:
206 QM_SCSS_CCU->wake_mask =
207 SET_ALL_BITS & ~QM_CCU_WAKE_MASK_RTC_BIT;
208 break;
209 case QM_POWER_WAKE_FROM_GPIO_COMP:
210 default:
211 QM_SCSS_CCU->wake_mask = SET_ALL_BITS &
212 ~(QM_CCU_WAKE_MASK_COMPARATOR_BIT |
213 QM_CCU_WAKE_MASK_GPIO_BIT);
214 break;
215 }
216
217 qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_DEEP_PWR_DOWN);
218
219 /* Turn off high power comparators. */
220 QM_SCSS_CMP->cmp_pwr &= QM_AC_HP_COMPARATORS_MASK;
221
222 /* Disable all peripheral clocks. */
223 clk_periph_disable(CLK_PERIPH_REGISTER);
224
225 /* Disable external clocks. */
226 QM_SCSS_CCU->ccu_ext_clock_ctl = 0;
227 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_EXT_CLK_CTL);
228
229 /* Set slew rate of all pins to 12mA. */
230 QM_SCSS_PMUX->pmux_slew[0] = 0;
231 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_PMUX_SLEW);
232
233 if (wake_event != QM_POWER_WAKE_FROM_RTC) {
234 /* Disable RTC. */
235 QM_SCSS_CCU->osc1_cfg0 &= ~QM_OSC1_PD;
236
237 /* Set system clock source to
238 * Silicon Oscillator 4 MHz, scaled down to 32 kHz. */
239 clk_sys_set_mode(CLK_SYS_HYB_OSC_4MHZ, CLK_SYS_DIV_128);
240 }
241
242 /* Power down the oscillator after the halt instruction is executed. */
243 QM_SCSS_CCU->ccu_lp_clk_ctl &= ~QM_HYB_OSC_PD_LATCH_EN;
244 /*
245 * Enable memory halt and CPU halt. When exiting sleep mode, use hybrid
246 * oscillator.
247 */
248 QM_SCSS_CCU->ccu_lp_clk_ctl |=
249 QM_CCU_EXIT_TO_HYBOSC | QM_CCU_MEM_HALT_EN | QM_CCU_CPU_HALT_EN;
250 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_LP_CLK_CTL);
251
252 /* Power down hybrid oscillator. */
253 QM_SCSS_CCU->osc0_cfg1 |= QM_OSC0_PD;
254
255 /* Disable gpio debounce clocking. */
256 QM_SCSS_CCU->ccu_gpio_db_clk_ctl &= ~QM_CCU_GPIO_DB_CLK_EN;
257 /* Set retention voltage to 1.35V. */
258 /* SCSS.OSC0_CFG0.OSC0_HYB_SET_REG1.OSC0_CFG0[0] = 1; */
259 QM_SCSS_CCU->osc0_cfg0 |= QM_SI_OSC_1V2_MODE;
260
261 /* Enable low voltage mode for flash controller. */
262 /* FlashCtrl.CTRL.LVE_MODE = 1; */
263 QM_FLASH[QM_FLASH_0]->ctrl |= QM_FLASH_LVE_MODE;
264
265 /* Select 1.35V for voltage regulator. */
266 /* SCSS.AON_VR.VSEL = 0xB; */
267 QM_SCSS_PMU->aon_vr =
268 (QM_AON_VR_PASS_CODE |
269 (power_context.aon_vr_save & QM_AON_VR_VSEL_MASK) |
270 QM_AON_VR_VSEL_1V35);
271 /* SCSS.AON_VR.ROK_BUF_VREG_MASK = 1; */
272 QM_SCSS_PMU->aon_vr = (QM_AON_VR_PASS_CODE | QM_SCSS_PMU->aon_vr |
273 QM_AON_VR_ROK_BUF_VREG_MASK);
274
275 /* SCSS.AON_VR.VSEL_STROBE = 1; */
276 QM_SCSS_PMU->aon_vr =
277 (QM_AON_VR_PASS_CODE | QM_SCSS_PMU->aon_vr | QM_AON_VR_VSTRB);
278
279 /* Wait >= 1 usec, at 256 kHz this is 1 cycle. */
280 __asm__ __volatile__("nop");
281
282 /* SCSS.AON_VR.VSEL_STROBE = 0; */
283 QM_SCSS_PMU->aon_vr =
284 (QM_AON_VR_PASS_CODE | (QM_SCSS_PMU->aon_vr & ~QM_AON_VR_VSTRB));
285
286 /* Wait >= 2 usec, at 256 kHz this is 1 cycle. */
287 __asm__ __volatile__("nop");
288
289 /* Set the RAR to retention mode. */
290 qm_rar_set_mode(QM_RAR_RETENTION);
291
292 if (wake_event == QM_POWER_WAKE_FROM_RTC) {
293 /* Start running on the rtc clock */
294 clk_sys_set_mode(CLK_SYS_RTC_OSC, CLK_SYS_DIV_1);
295 }
296
297 /* Disable all peripheral clocks. */
298 clk_periph_disable(CLK_PERIPH_REGISTER | CLK_PERIPH_CLK);
299
300 /* Enter SoC deep sleep mode. */
301 qm_power_cpu_halt();
302 }
303
304 void qm_power_soc_deep_sleep_restore(void)
305 {
306 /* We are now exiting from deep sleep mode. */
307 /* Set the RAR to normal mode. */
308 qm_rar_set_mode(QM_RAR_NORMAL);
309
310 /*
311 * Since we are running below 4MHz, 0 wait states are configured.
312 * If the previous frequency was > 4MHz, 0 wait states will
313 * violate the flash timings.
314 * In the worst case scenario, when switching back to 32MHz,
315 * 2 wait states will be restored.
316 * This setting will be too conservative until the frequency has been
317 * restored.
318 */
319 QM_FLASH[QM_FLASH_0]->tmg_ctrl = power_context.flash_tmg_save;
320
321 /* Restore operating voltage to 1.8V. */
322 /* SCSS.AON_VR.VSEL = 0x10; */
323 QM_SCSS_PMU->aon_vr =
324 (QM_AON_VR_PASS_CODE | (QM_SCSS_PMU->aon_vr & QM_AON_VR_VSEL_MASK) |
325 QM_AON_VR_VSEL_1V8 | QM_AON_VR_ROK_BUF_VREG_MASK);
326
327 /* SCSS.AON_VR.VSEL_STROBE = 1; */
328 QM_SCSS_PMU->aon_vr =
329 (QM_AON_VR_PASS_CODE | QM_SCSS_PMU->aon_vr | QM_AON_VR_VSTRB);
330
331 /* Wait >= 1 usec, at 256 kHz this is 1 cycle. */
332 __asm__ __volatile__("nop");
333
334 /* SCSS.AON_VR.VSEL_STROBE = 0; */
335 QM_SCSS_PMU->aon_vr =
336 (QM_AON_VR_PASS_CODE | (QM_SCSS_PMU->aon_vr & ~QM_AON_VR_VSTRB));
337
338 /* Wait >= 2 usec, at 256 kHz this is 1 cycle. */
339 __asm__ __volatile__("nop");
340
341 /* SCSS.AON_VR.ROK_BUF_VREG_MASK = 0; */
342 QM_SCSS_PMU->aon_vr =
343 (QM_AON_VR_PASS_CODE |
344 (QM_SCSS_PMU->aon_vr & ~QM_AON_VR_ROK_BUF_VREG_MASK));
345
346 /* Wait >= 1 usec, at 256 kHz this is 1 cycle. */
347 __asm__ __volatile__("nop");
348
349 /* Wait for voltage regulator to attain 1.8V regulation. */
350 while (!(QM_SCSS_PMU->aon_vr & QM_AON_VR_ROK_BUF_VREG_STATUS)) {
351 }
352
353 /* SCSS.OSC0_CFG0.OSC0_HYB_SET_REG1.OSC0_CFG0[0] = 0; */
354 QM_SCSS_CCU->osc0_cfg0 &= ~QM_SI_OSC_1V2_MODE;
355
356 /* FlashCtrl.CTRL.LVE_MODE = 0; */
357 QM_FLASH[QM_FLASH_0]->ctrl &= ~QM_FLASH_LVE_MODE;
358
359 /* Restore all previous values. */
360 QM_SCSS_CCU->ccu_sys_clk_ctl = power_context.sys_clk_ctl_save;
361 /* Re-apply clock divider values. DIV_EN must go 0 -> 1. */
362 QM_SCSS_CCU->ccu_sys_clk_ctl &=
363 ~(QM_CCU_SYS_CLK_DIV_EN | QM_CCU_RTC_CLK_DIV_EN);
364 QM_SCSS_CCU->ccu_sys_clk_ctl |=
365 QM_CCU_SYS_CLK_DIV_EN | QM_CCU_RTC_CLK_DIV_EN;
366
367 /* Wait for the XTAL or SI oscillator to stabilise. */
368 while (!(QM_SCSS_CCU->osc0_stat1 &
369 (QM_OSC0_LOCK_SI | QM_OSC0_LOCK_XTAL))) {
370 };
371 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_SYS_CLK_CTL);
372
373 /* Re-enable clocks. */
374 clk_periph_enable(CLK_PERIPH_REGISTER);
375
376 /* Re-enable gpio debounce clocking. */
377 QM_SCSS_CCU->ccu_gpio_db_clk_ctl |= QM_CCU_GPIO_DB_CLK_EN;
378
379 /* Restore original clocking, ADC, analog comparator states. */
380 QM_SCSS_CCU->osc0_cfg1 = power_context.osc0_cfg_save;
381 QM_SCSS_CCU->ccu_periph_clk_gate_ctl = power_context.clk_gate_save;
382 QM_SCSS_CCU->osc1_cfg0 = power_context.osc1_cfg_save;
383
384 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_OSC0_CFG1);
385 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER,
386 SOCW_REG_CCU_PERIPH_CLK_GATE_CTL);
387 QM_SCSS_CMP->cmp_pwr = power_context.ac_power_save;
388 QM_ADC->adc_op_mode = power_context.adc_mode_save;
389
390 QM_SCSS_PMUX->pmux_slew[0] = power_context.pmux_slew_save;
391 QM_SCSS_CCU->ccu_ext_clock_ctl = power_context.ext_clock_save;
392 QM_SCSS_CCU->ccu_lp_clk_ctl = power_context.lp_clk_save;
393
394 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_PMUX_SLEW);
395 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_LP_CLK_CTL);
396 SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_EXT_CLK_CTL);
397
398 QM_SCSS_CCU->wake_mask = SET_ALL_BITS;
399 QM_SCSS_GP->gps0 &= ~QM_GPS0_POWER_STATE_DEEP_SLEEP;
400 }
401
402 void qm_power_soc_restore(void)
403 {
404 /*
405 * If the SoC is waking from sleep or deep sleep mode then the full
406 * system state must be restored.
407 */
408 if (QM_SCSS_GP->gps0 & QM_GPS0_POWER_STATE_SLEEP) {
409 qm_power_soc_sleep_restore();
410 } else if (QM_SCSS_GP->gps0 & QM_GPS0_POWER_STATE_DEEP_SLEEP) {
411 qm_power_soc_deep_sleep_restore();
412 }
413 }
414
415 int qm_rar_set_mode(const qm_rar_state_t mode)
416 {
417 QM_CHECK(mode <= QM_RAR_RETENTION, -EINVAL);
418 volatile uint32_t i = 32;
419 volatile uint32_t reg;
420
421 switch (mode) {
422 case QM_RAR_RETENTION:
423 QM_SCSS_PMU->aon_vr |=
424 (QM_AON_VR_PASS_CODE | QM_AON_VR_ROK_BUF_VREG_MASK);
425 QM_SCSS_PMU->aon_vr |=
426 (QM_AON_VR_PASS_CODE | QM_AON_VR_VREG_SEL);
427 break;
428
429 case QM_RAR_NORMAL:
430 reg = QM_SCSS_PMU->aon_vr & ~QM_AON_VR_VREG_SEL;
431 QM_SCSS_PMU->aon_vr = QM_AON_VR_PASS_CODE | reg;
432 /* Wait for >= 2usec, at most 64 clock cycles. */
433 while (i--) {
434 __asm__ __volatile__("nop");
435 }
436 reg = QM_SCSS_PMU->aon_vr & ~QM_AON_VR_ROK_BUF_VREG_MASK;
437 QM_SCSS_PMU->aon_vr = QM_AON_VR_PASS_CODE | reg;
438 break;
439 }
440 return 0;
441 }
clk_sys_set_mode
int clk_sys_set_mode(const clk_sys_mode_t mode, const clk_sys_div_t div)
Set clock mode and divisor.
Definition: clk.c:100
qm_power_soc_restore
void qm_power_soc_restore(void)
Restore system state after sleep or deep sleep.
Definition: power_states.c:402
CLK_PERIPH_UARTA_REGISTER
UARTA Clock Gate Enable.
Definition: qm_soc_regs.h:1384
CLK_SYS_DIV_8
Clock Divider = 8.
Definition: clk.h:40
CLK_PERIPH_GPIO_DB
GPIO Debounce Clock Enable.
Definition: qm_soc_regs.h:1375
qm_rar_set_mode
int qm_rar_set_mode(const qm_rar_state_t mode)
Change operating mode of RAR.
Definition: power_states.c:415
SOCW_EVENT_REGISTER
SOC register altered.
Definition: soc_watch.h:40
clk_periph_enable
int clk_periph_enable(const clk_periph_t clocks)
Enable clocks for peripherals / registers.
Definition: clk.c:319
QM_RAR_NORMAL
Normal mode = 50 mA.
Definition: power_states.h:91
CLK_PERIPH_PWM_REGISTER
PWM Clock Gate Enable.
Definition: qm_soc_regs.h:1378
QM_RAR_RETENTION
Retention mode = 300 uA.
Definition: power_states.h:92
SOCW_REG_CCU_EXT_CLK_CTL
0x024 CCU Ext Clock Gate Ctl.
Definition: soc_watch.h:78
SOCW_REG_CCU_PERIPH_CLK_GATE_CTL
0x018 Perip Clock Gate Ctl.
Definition: soc_watch.h:77
CLK_PERIPH_CLK
Peripheral Clock Enable.
Definition: qm_soc_regs.h:1370
SOCW_REG_CCU_LP_CLK_CTL
0x02C Clock Control register.
Definition: soc_watch.h:74
CLK_PERIPH_REGISTER
Peripheral Clock Gate Enable.
Definition: qm_soc_regs.h:1369
CLK_PERIPH_SPI_M0
SPI Master 0 Clock Enable.
Definition: qm_soc_regs.h:1373
qm_power_soc_deep_sleep
void qm_power_soc_deep_sleep(const qm_power_wake_event_t wake_event)
Put SoC to deep sleep.
Definition: power_states.c:180
CLK_PERIPH_WDT_REGISTER
Watchdog Clock Enable.
Definition: qm_soc_regs.h:1376
SOCW_EVENT_HALT
CPU Halt.
Definition: soc_watch.h:37
CLK_PERIPH_GPIO_REGISTER
GPIO Clock Gate Enable.
Definition: qm_soc_regs.h:1379
QM_ADC_MODE_DEEP_PWR_DOWN
Deep power down mode.
Definition: qm_adc.h:50
QM_POWER_WAKE_FROM_RTC
Use RTC as wake source.
Definition: power_states.h:24
qm_power_soc_deep_sleep_restore
void qm_power_soc_deep_sleep_restore(void)
Enter SoC deep sleep state and restore after wake up.
Definition: power_states.c:304
QM_POWER_WAKE_FROM_GPIO_COMP
Use GPIO/Comparator as wake source.
Definition: power_states.h:23
SOCW_REG_OSC0_CFG1
0x000 OSC0_CFG1 register.
Definition: soc_watch.h:73
CLK_PERIPH_UARTB_REGISTER
UARTB Clock Gate Enable.
Definition: qm_soc_regs.h:1385
clk_periph_disable
int clk_periph_disable(const clk_periph_t clocks)
Disable clocks for peripherals / registers.
Definition: clk.c:333
qm_rar_state_t
qm_rar_state_t
RAR modes type.
Definition: power_states.h:90
qm_power_soc_sleep
void qm_power_soc_sleep(void)
Put SoC to sleep.
Definition: power_states.c:59
qm_power_wake_event_t
qm_power_wake_event_t
Wake source for deep sleep mode type.
Definition: power_states.h:21
CLK_PERIPH_I2C_M0_REGISTER
I2C Master 0 Clock Gate Enable.
Definition: qm_soc_regs.h:1386
CLK_PERIPH_SPI_S_REGISTER
SPI Slave Clock Gate Enable.
Definition: qm_soc_regs.h:1382
CLK_PERIPH_I2C_M0
I2C Master 0 Clock Enable.
Definition: qm_soc_regs.h:1371
qm_power_soc_sleep_restore
void qm_power_soc_sleep_restore(void)
Enter SoC sleep state and restore after wake up.
Definition: power_states.c:135
qm_adc_set_mode
int qm_adc_set_mode(const qm_adc_t adc, const qm_adc_mode_t mode)
Switch operating mode of ADC.
Definition: qm_adc.c:271
CLK_PERIPH_SPI_M0_REGISTER
SPI Master 0 Clock Gate Enable.
Definition: qm_soc_regs.h:1380
CLK_SYS_DIV_128
Clock Divider = 128.
Definition: clk.h:44
qm_power_cpu_halt
void qm_power_cpu_halt(void)
Put CPU in halt state.
Definition: power_states.c:29
SOCW_REG_CCU_SYS_CLK_CTL
0x038 System Clock Control.
Definition: soc_watch.h:75
CLK_SYS_RTC_OSC
Real Time Clock.
Definition: clk.h:56
CLK_SYS_HYB_OSC_4MHZ
4MHz Hybrid Oscillator Clock.
Definition: clk.h:55
CLK_PERIPH_SPI_S
SPI Slave Clock Enable.
Definition: qm_soc_regs.h:1372
SOCW_REG_PMUX_SLEW
0x910 Pin Mux Slew.
Definition: soc_watch.h:82
QM_ADC_MODE_PWR_DOWN
Power down mode.
Definition: qm_adc.h:51
CLK_SYS_DIV_1
Clock Divider = 1.
Definition: clk.h:37