Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_sensor_regs.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __SENSOR_REGISTERS_H__
6 #define __SENSOR_REGISTERS_H__
7
8 #include "qm_common.h"
9 #include "qm_soc_interrupts.h"
10
11 /**
12 * Quark SE SoC Sensor Subsystem Registers.
13 *
14 * For detailed description please read the SOC datasheet.
15 *
16 * @defgroup groupSSSEREG SoC Registers (Sensor Subsystem)
17 * @{
18 */
19
20 #if (UNIT_TEST)
21
22 #define QM_SS_BASE_AUX_REGS_NUM (0x701)
23 /* Peripherals auxiliary registers start at
24 * 0x80010000 and ends at 0x80018180 */
25 #define QM_SS_PERIPH_AUX_REGS_BASE (0x80010000)
26 #define QM_SS_PERIPH_AUX_REGS_SIZE (0x8181)
27 #define QM_SS_AUX_REGS_SIZE \
28 (QM_SS_BASE_AUX_REGS_NUM + QM_SS_PERIPH_AUX_REGS_SIZE)
29
30 uint32_t test_sensor_aux[QM_SS_AUX_REGS_SIZE];
31
32 #define __builtin_arc_lr(addr) \
33 ({ \
34 uint32_t temp = addr; \
35 if (temp >= QM_SS_PERIPH_AUX_REGS_BASE) { \
36 temp -= QM_SS_PERIPH_AUX_REGS_BASE; \
37 temp += QM_SS_BASE_AUX_REGS_NUM; \
38 } \
39 (test_sensor_aux[temp]); \
40 })
41
42 #define __builtin_arc_sr(val, addr) \
43 ({ \
44 uint32_t temp = addr; \
45 if (temp >= QM_SS_PERIPH_AUX_REGS_BASE) { \
46 temp -= QM_SS_PERIPH_AUX_REGS_BASE; \
47 temp += QM_SS_BASE_AUX_REGS_NUM; \
48 } \
49 (test_sensor_aux[temp] = val); \
50 })
51
52 #define __builtin_arc_kflag(sreg)
53 #define __builtin_arc_brk()
54 #define __builtin_arc_clri()
55 #define __builtin_arc_seti(val)
56 #define __builtin_arc_nop()
57 #endif
58
59 /* Bitwise OR operation macro for registers in the auxiliary memory space. */
60 #define QM_SS_REG_AUX_OR(reg, mask) \
61 (__builtin_arc_sr(__builtin_arc_lr(reg) | (mask), reg))
62 /* Bitwise NAND operation macro for registers in the auxiliary memory space. */
63 #define QM_SS_REG_AUX_NAND(reg, mask) \
64 (__builtin_arc_sr(__builtin_arc_lr(reg) & (~(mask)), reg))
65 /* Bitwise MASK and OR operation macro for registers in the auxiliary memory
66 * space.
67 */
68 #define QM_SS_REG_AUX_MASK_OR(reg, mask, value) \
69 (__builtin_arc_sr(((__builtin_arc_lr(reg) & (~(mask))) | value), reg))
70
71 /* Sensor Subsystem status32 register. */
72 #define QM_SS_AUX_STATUS32 (0xA)
73 /** Interrupt priority threshold. */
74 #define QM_SS_STATUS32_E_MASK (0x1E)
75 /** Interrupt enable. */
76 #define QM_SS_STATUS32_IE_MASK BIT(31)
77 /* Sensor Subsystem control register. */
78 #define QM_SS_AUX_IC_CTRL (0x11)
79 /* Sensor Subsystem cache invalidate register. */
80 #define QM_SS_AUX_IC_IVIL (0x19)
81 /* Sensor Subsystem vector base register. */
82 #define QM_SS_AUX_INT_VECTOR_BASE (0x25)
83
84 /**
85 * @name SS Interrupt
86 * @{
87 */
88
89 /**
90 * SS IRQ context type.
91 *
92 * Applications should not modify the content.
93 * This structure is only intended to be used by
94 * qm_irq_save_context and qm_irq_restore_context functions.
95 */
96 typedef struct {
97 uint32_t status32_irq_threshold; /**< STATUS32 Interrupt Threshold. */
98 uint32_t status32_irq_enable; /**< STATUS32 Interrupt Enable. */
99 uint32_t irq_ctrl; /**< Interrupt Context Saving Control Register. */
100
101 /**
102 * IRQ configuration:
103 * - IRQ Priority:BIT(6):BIT(2)
104 * - IRQ Trigger:BIT(1)
105 * - IRQ Enable:BIT(0)
106 */
107 uint8_t irq_config[QM_SS_INT_VECTOR_NUM - QM_SS_EXCEPTION_NUM];
108 } qm_irq_context_t;
109
110 /** @} */
111
112 /**
113 * @name SS Timer
114 * @{
115 */
116
117 typedef enum {
118 QM_SS_TIMER_COUNT = 0,
119 QM_SS_TIMER_CONTROL,
120 QM_SS_TIMER_LIMIT
121 } qm_ss_timer_reg_t;
122
123 /**
124 * Sensor Subsystem Timers.
125 */
126 typedef enum { QM_SS_TIMER_0 = 0, QM_SS_TIMER_NUM } qm_ss_timer_t;
127
128 /*
129 * SS TIMER context type.
130 *
131 * Application should not modify the content.
132 * This structure is only intended to be used by the qm_ss_timer_save_context
133 * and qm_ss_timer_restore_context functions.
134 */
135 typedef struct {
136 uint32_t timer_count; /**< Timer count. */
137 uint32_t timer_control; /**< Timer control. */
138 uint32_t timer_limit; /**< Timer limit. */
139 } qm_ss_timer_context_t;
140
141 #define QM_SS_TIMER_0_BASE (0x21)
142 #define QM_SS_TIMER_1_BASE (0x100)
143 #define QM_SS_TSC_BASE QM_SS_TIMER_1_BASE
144
145 #define QM_SS_TIMER_CONTROL_INT_EN_OFFSET (0)
146 #define QM_SS_TIMER_CONTROL_NON_HALTED_OFFSET (1)
147 #define QM_SS_TIMER_CONTROL_WATCHDOG_OFFSET (2)
148 #define QM_SS_TIMER_CONTROL_INT_PENDING_OFFSET (3)
149 /** @} */
150
151 /**
152 * GPIO registers and definitions.
153 *
154 * @name SS GPIO
155 * @{
156 */
157
158 /** Sensor Subsystem GPIO register block type. */
159 typedef enum {
160 QM_SS_GPIO_SWPORTA_DR = 0,
161 QM_SS_GPIO_SWPORTA_DDR,
162 QM_SS_GPIO_INTEN = 3,
163 QM_SS_GPIO_INTMASK,
164 QM_SS_GPIO_INTTYPE_LEVEL,
165 QM_SS_GPIO_INT_POLARITY,
166 QM_SS_GPIO_INTSTATUS,
167 QM_SS_GPIO_DEBOUNCE,
168 QM_SS_GPIO_PORTA_EOI,
169 QM_SS_GPIO_EXT_PORTA,
170 QM_SS_GPIO_LS_SYNC
171 } qm_ss_gpio_reg_t;
172
173 /**
174 * SS GPIO context type.
175 *
176 * Application should not modify the content.
177 * This structure is only intended to be used by the qm_ss_gpio_save_context and
178 * qm_ss_gpio_restore_context functions.
179 */
180 typedef struct {
181 uint32_t gpio_swporta_dr; /**< Port A Data. */
182 uint32_t gpio_swporta_ddr; /**< Port A Data Direction. */
183 uint32_t gpio_inten; /**< Interrupt Enable. */
184 uint32_t gpio_intmask; /**< Interrupt Mask. */
185 uint32_t gpio_inttype_level; /**< Interrupt Type. */
186 uint32_t gpio_int_polarity; /**< Interrupt Polarity. */
187 uint32_t gpio_debounce; /**< Debounce Enable. */
188 uint32_t gpio_ls_sync; /**< Synchronization Level. */
189 } qm_ss_gpio_context_t;
190
191 #define QM_SS_GPIO_NUM_PINS (16)
192 #define QM_SS_GPIO_LS_SYNC_CLK_EN BIT(31)
193 #define QM_SS_GPIO_LS_SYNC_SYNC_LVL BIT(0)
194
195 /** Sensor Subsystem GPIO. */
196 typedef enum { QM_SS_GPIO_0 = 0, QM_SS_GPIO_1, QM_SS_GPIO_NUM } qm_ss_gpio_t;
197
198 #define QM_SS_GPIO_0_BASE (0x80017800)
199 #define QM_SS_GPIO_1_BASE (0x80017900)
200
201 /** @} */
202
203 /**
204 * I2C registers and definitions.
205 *
206 * @name SS I2C
207 * @{
208 */
209
210 /** Sensor Subsystem I2C register block type. */
211 typedef enum {
212 QM_SS_I2C_CON = 0,
213 QM_SS_I2C_DATA_CMD,
214 QM_SS_I2C_SS_SCL_CNT,
215 QM_SS_I2C_FS_SCL_CNT = 0x04,
216 QM_SS_I2C_INTR_STAT = 0x06,
217 QM_SS_I2C_INTR_MASK,
218 QM_SS_I2C_TL,
219 QM_SS_I2C_INTR_CLR = 0x0A,
220 QM_SS_I2C_STATUS,
221 QM_SS_I2C_TXFLR,
222 QM_SS_I2C_RXFLR,
223 QM_SS_I2C_SDA_CONFIG,
224 QM_SS_I2C_TX_ABRT_SOURCE,
225 QM_SS_I2C_ENABLE_STATUS = 0x11
226 } qm_ss_i2c_reg_t;
227
228 /**
229 * SS I2C context type.
230 *
231 * Application should not modify the content.
232 * This structure is only intended to be used by the qm_ss_gpio_save_context and
233 * qm_ss_gpio_restore_context functions.
234 */
235 typedef struct {
236 uint32_t i2c_con;
237 uint32_t i2c_ss_scl_cnt;
238 uint32_t i2c_fs_scl_cnt;
239 } qm_ss_i2c_context_t;
240
241 #define QM_SS_I2C_CON_ENABLE BIT(0)
242 #define QM_SS_I2C_CON_ABORT BIT(1)
243 #define QM_SS_I2C_CON_ABORT_OFFSET (1)
244 #define QM_SS_I2C_CON_SPEED_SS BIT(3)
245 #define QM_SS_I2C_CON_SPEED_FS BIT(4)
246 #define QM_SS_I2C_CON_SPEED_FSP BIT(4)
247 #define QM_SS_I2C_CON_SPEED_MASK (0x18)
248 #define QM_SS_I2C_CON_SPEED_OFFSET (3)
249 #define QM_SS_I2C_CON_IC_10BITADDR BIT(5)
250 #define QM_SS_I2C_CON_IC_10BITADDR_OFFSET (5)
251 #define QM_SS_I2C_CON_IC_10BITADDR_MASK BIT(5)
252 #define QM_SS_I2C_CON_RESTART_EN BIT(7)
253 #define QM_SS_I2C_CON_RESTART_EN_OFFSET (7)
254 #define QM_SS_I2C_CON_TAR_SAR_OFFSET (9)
255 #define QM_SS_I2C_CON_TAR_SAR_MASK (0x7FE00)
256 #define QM_SS_I2C_CON_TAR_SAR_10_BIT_MASK (0x3FF)
257 #define QM_SS_I2C_CON_SPKLEN_OFFSET (22)
258 #define QM_SS_I2C_CON_SPKLEN_MASK (0x3FC00000)
259 #define QM_SS_I2C_CON_CLK_ENA BIT(31)
260 #define QM_SS_I2C_CON_ENABLE_ABORT_MASK (0x3)
261
262 #define QM_SS_I2C_DATA_CMD_CMD BIT(8)
263 #define QM_SS_I2C_DATA_CMD_STOP BIT(9)
264 #define QM_SS_I2C_DATA_CMD_PUSH (0xC0000000)
265 #define QM_SS_I2C_DATA_CMD_POP (0x80000000)
266
267 #define QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET (16)
268 #define QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK (0xFFFF)
269
270 #define QM_SS_I2C_INTR_STAT_RX_UNDER BIT(0)
271 #define QM_SS_I2C_INTR_STAT_RX_OVER BIT(1)
272 #define QM_SS_I2C_INTR_STAT_RX_FULL BIT(2)
273 #define QM_SS_I2C_INTR_STAT_TX_OVER BIT(3)
274 #define QM_SS_I2C_INTR_STAT_TX_EMPTY BIT(4)
275 #define QM_SS_I2C_INTR_STAT_TX_ABRT BIT(6)
276 #define QM_SS_I2C_INTR_STAT_STOP BIT(9)
277 #define QM_SS_I2C_INTR_STAT_START BIT(10)
278
279 #define QM_SS_I2C_INTR_MASK_ALL (0x0)
280 #define QM_SS_I2C_INTR_MASK_RX_UNDER BIT(0)
281 #define QM_SS_I2C_INTR_MASK_RX_OVER BIT(1)
282 #define QM_SS_I2C_INTR_MASK_RX_FULL BIT(2)
283 #define QM_SS_I2C_INTR_MASK_TX_OVER BIT(3)
284 #define QM_SS_I2C_INTR_MASK_TX_EMPTY BIT(4)
285 #define QM_SS_I2C_INTR_MASK_TX_ABRT BIT(6)
286 #define QM_SS_I2C_INTR_MASK_STOP BIT(9)
287 #define QM_SS_I2C_INTR_MASK_START BIT(10)
288
289 #define QM_SS_I2C_TL_TX_TL_OFFSET (16)
290 #define QM_SS_I2C_TL_MASK (0xFF)
291 #define QM_SS_I2C_TL_RX_TL_MASK (0xFF)
292 #define QM_SS_I2C_TL_TX_TL_MASK (0xFF0000)
293
294 #define QM_SS_I2C_INTR_CLR_ALL (0xFF)
295 #define QM_SS_I2C_INTR_CLR_RX_UNDER BIT(0)
296 #define QM_SS_I2C_INTR_CLR_RX_OVER BIT(1)
297 #define QM_SS_I2C_INTR_CLR_TX_OVER BIT(3)
298 #define QM_SS_I2C_INTR_CLR_TX_ABRT BIT(6)
299 #define QM_SS_I2C_INTR_CLR_STOP_DET BIT(9)
300
301 #define QM_SS_I2C_TX_ABRT_SOURCE_NAK_MASK (0x09)
302 #define QM_SS_I2C_TX_ABRT_SOURCE_ALL_MASK (0x1FFFF)
303 #define QM_SS_I2C_TX_ABRT_SBYTE_NORSTRT BIT(9)
304 #define QM_SS_I2C_TX_ABRT_SOURCE_ART_LOST BIT(12)
305
306 #define QM_SS_I2C_ENABLE_CONTROLLER_EN BIT(0)
307 #define QM_SS_I2C_ENABLE_STATUS_IC_EN BIT(0)
308
309 #define QM_SS_I2C_STATUS_BUSY_MASK (0x21)
310 #define QM_SS_I2C_STATUS_RFNE BIT(3)
311 #define QM_SS_I2C_STATUS_TFE BIT(2)
312 #define QM_SS_I2C_STATUS_TFNF BIT(1)
313
314 #define QM_SS_I2C_IC_LCNT_MAX (65525)
315 #define QM_SS_I2C_IC_LCNT_MIN (8)
316 #define QM_SS_I2C_IC_HCNT_MAX (65525)
317 #define QM_SS_I2C_IC_HCNT_MIN (6)
318
319 #define QM_SS_I2C_FIFO_SIZE (8)
320
321 #define QM_SS_I2C_SPK_LEN_SS (1)
322 #define QM_SS_I2C_SPK_LEN_FS (2)
323 #define QM_SS_I2C_SPK_LEN_FSP (2)
324
325 #define QM_SS_I2C_WRITE_CLKEN(controller) \
326 __builtin_arc_sr((__builtin_arc_lr(controller + QM_SS_I2C_CON) & \
327 QM_SS_I2C_CON_CLK_ENA), \
328 controller + QM_SS_I2C_CON)
329 #define QM_SS_I2C_WRITE_SPKLEN(controller, value) \
330 QM_SS_REG_AUX_OR((controller + QM_SS_I2C_CON), \
331 value << QM_SS_I2C_CON_SPKLEN_OFFSET)
332 #define QM_SS_I2C_WRITE_TAR(controller, value) \
333 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_CON, \
334 (value & QM_SS_I2C_CON_TAR_SAR_10_BIT_MASK) \
335 << QM_SS_I2C_CON_TAR_SAR_OFFSET)
336 #define QM_SS_I2C_WRITE_RESTART_EN(controller) \
337 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_CON, QM_SS_I2C_CON_RESTART_EN)
338 #define QM_SS_I2C_WRITE_ADDRESS_MODE(contoller, value) \
339 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_CON, \
340 value << QM_SS_I2C_CON_IC_10BITADDR_OFFSET)
341 #define QM_SS_I2C_WRITE_SPEED(controller, value) \
342 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_CON, value)
343 #define QM_SS_I2C_WRITE_DATA_CMD(controller, value) \
344 __builtin_arc_sr(value, controller + QM_SS_I2C_DATA_CMD)
345 #define QM_SS_I2C_WRITE_SS_SCL_HCNT(controller, value) \
346 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_SS_SCL_CNT, \
347 (value & QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK) \
348 << QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET)
349 #define QM_SS_I2C_WRITE_SS_SCL_LCNT(controller, value) \
350 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_SS_SCL_CNT, \
351 value & QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK)
352 #define QM_SS_I2C_WRITE_FS_SCL_HCNT(controller, value) \
353 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_FS_SCL_CNT, \
354 (value & QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK) \
355 << QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET)
356 #define QM_SS_I2C_WRITE_FS_SCL_LCNT(controller, value) \
357 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_FS_SCL_CNT, \
358 value & QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK)
359 #define QM_SS_I2C_WRITE_RAW_INTR_STAT(controller, value) \
360 __builtin_arc_sr(value, controller + QM_SS_I2C_INTR_STAT)
361 #define QM_SS_I2C_WRITE_TX_TL(controller, value) \
362 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_TL, \
363 (value & QM_SS_I2C_TL_MASK) \
364 << QM_SS_I2C_TL_TX_TL_OFFSET)
365 #define QM_SS_I2C_WRITE_RX_TL(controller, value) \
366 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_TL, \
367 value & QM_SS_I2C_TL_RX_TL_MASK)
368 #define QM_SS_I2C_WRITE_STATUS(controller, value) \
369 __builtin_arc_sr(value, controller + QM_SS_I2C_STATUS)
370 #define QM_SS_I2C_WRITE_TXFLR(controller, value) \
371 __builtin_arc_sr(value, controller + QM_SS_I2C_TXFLR)
372 #define QM_SS_I2C_WRITE_RXFLR(controller, value) \
373 __builtin_arc_sr(value, controller + QM_SS_I2C_RXFLR)
374 #define QM_SS_I2C_WRITE_TX_ABRT_SOURCE(controller, value) \
375 __builtin_arc_sr(value, controller + QM_SS_I2C_TX_ABRT_SOURCE)
376
377 #define QM_SS_I2C_CLEAR_ENABLE(controller) \
378 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_CON, \
379 QM_SS_I2C_CON_ENABLE_ABORT_MASK)
380 #define QM_SS_I2C_CLEAR_CON(controller) \
381 __builtin_arc_sr(0, controller + QM_SS_I2C_CON)
382 #define QM_SS_I2C_CLEAR_SPKLEN(controller) \
383 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_CON, \
384 QM_SS_I2C_CON_SPKLEN_MASK)
385 #define QM_SS_I2C_CLEAR_TAR(controller) \
386 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_CON, \
387 QM_SS_I2C_CON_TAR_SAR_MASK)
388 #define QM_SS_I2C_CLEAR_SPEED(controller) \
389 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_CON, QM_SS_I2C_CON_SPEED_MASK)
390 #define QM_SS_I2C_CLEAR_DATA_CMD(controller) \
391 __builtin_arc_sr(0, controller + QM_SS_I2C_DATA_CMD)
392 #define QM_SS_I2C_CLEAR_SS_SCL_HCNT(controller) \
393 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_SS_SCL_CNT, \
394 QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK \
395 << QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET)
396 #define QM_SS_I2C_CLEAR_SS_SCL_LCNT(controller) \
397 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_SS_SCL_CNT, \
398 QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK)
399 #define QM_SS_I2C_CLEAR_FS_SCL_HCNT(controller) \
400 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_FS_SCL_CNT, \
401 QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK \
402 << QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET)
403 #define QM_SS_I2C_CLEAR_FS_SCL_LCNT(controller) \
404 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_FS_SCL_CNT, \
405 QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK)
406 #define QM_SS_I2C_CLEAR_INTR_STAT(controller) \
407 __builtin_arc_sr(0, controller + QM_SS_I2C_INTR_STAT)
408 #define QM_SS_I2C_CLEAR_INTR_MASK(controller) \
409 __builtin_arc_sr(0, controller + QM_SS_I2C_INTR_MASK)
410 #define QM_SS_I2C_CLEAR_TX_TL(controller) \
411 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_TL, QM_SS_I2C_TL_TX_TL_MASK)
412 #define QM_SS_I2C_CLEAR_RX_TL(controller) \
413 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_TL, QM_SS_I2C_TL_RX_TL_MASK)
414 #define QM_SS_I2C_CLEAR_STATUS(controller) \
415 __builtin_arc_sr(0, controller + QM_SS_I2C_STATUS)
416 #define QM_SS_I2C_CLEAR_TXFLR(controller) \
417 __builtin_arc_sr(0, controller + QM_SS_I2C_TXFLR)
418 #define QM_SS_I2C_CLEAR_RXFLR(controller) \
419 __builtin_arc_sr(0, controller + QM_SS_I2C_RXFLR)
420 #define QM_SS_I2C_CLEAR_SDA_CONFIG(controller) \
421 __builtin_arc_sr(0, controller + QM_SS_I2C_SDA_CONFIG)
422 #define QM_SS_I2C_CLEAR_TX_ABRT_SOURCE(controller) \
423 __builtin_arc_sr(0, controller + QM_SS_I2C_TX_ABRT_SOURCE)
424 #define QM_SS_I2C_CLEAR_ENABLE_STATUS(controller) \
425 __builtin_arc_sr(0, controller + QM_SS_I2C_ENABLE_STATUS)
426
427 #define QM_SS_I2C_READ_CON(controller) \
428 __builtin_arc_lr(controller + QM_SS_I2C_CON)
429 #define QM_SS_I2C_READ_ENABLE(controller) \
430 __builtin_arc_lr(controller + QM_SS_I2C_CON) & QM_SS_I2C_CON_ENABLE
431 #define QM_SS_I2C_READ_ABORT(controller) \
432 (__builtin_arc_lr(controller + QM_SS_I2C_CON) & \
433 QM_SS_I2C_CON_ABORT) >> \
434 QM_SS_I2C_CON_ABORT_OFFSET
435 #define QM_SS_I2C_READ_SPEED(controller) \
436 (__builtin_arc_lr(controller + QM_SS_I2C_CON) & \
437 QM_SS_I2C_CON_SPEED_MASK) >> \
438 QM_SS_I2C_CON_SPEED_OFFSET
439 #define QM_SS_I2C_READ_ADDR_MODE(controller) \
440 (__builtin_arc_lr(controller + QM_SS_I2C_CON) & \
441 QM_SS_I2C_CON_IC_10BITADDR_MASK) >> \
442 QM_SS_I2C_CON_IC_10BITADDR_OFFSET
443 #define QM_SS_I2C_READ_RESTART_EN(controller) \
444 (__builtin_arc_lr(controller + QM_SS_I2C_CON) & \
445 QM_SS_I2C_CON_RESTART_EN) >> \
446 QM_SS_I2C_CON_RESTART_EN_OFFSET
447 #define QM_SS_I2C_READ_TAR(controller) \
448 (__builtin_arc_lr(controller + QM_SS_I2C_CON) & \
449 QM_SS_I2C_CON_TAR_SAR_MASK) >> \
450 QM_SS_I2C_CON_TAR_SAR_OFFSET
451 #define QM_SS_I2C_READ_SPKLEN(controller) \
452 (__builtin_arc_lr(controller + QM_SS_I2C_CON) & \
453 QM_SS_I2C_CON_SPKLEN_MASK) >> \
454 QM_SS_I2C_CON_SPKLEN_OFFSET
455 #define QM_SS_I2C_READ_DATA_CMD(controller) \
456 __builtin_arc_lr(controller + QM_SS_I2C_DATA_CMD)
457 #define QM_SS_I2C_READ_RX_FIFO(controller) \
458 __builtin_arc_sr(QM_SS_I2C_DATA_CMD_POP, \
459 controller + QM_SS_I2C_DATA_CMD)
460 #define QM_SS_I2C_READ_SS_SCL_HCNT(controller) \
461 __builtin_arc_lr(controller + QM_SS_I2C_SS_SCL_CNT) >> \
462 QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET
463 #define QM_SS_I2C_READ_SS_SCL_LCNT(controller) \
464 __builtin_arc_lr(controller + QM_SS_I2C_SS_SCL_CNT) & \
465 QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK
466 #define QM_SS_I2C_READ_FS_SCL_HCNT(controller) \
467 __builtin_arc_lr(controller + QM_SS_I2C_FS_SCL_CNT) >> \
468 QM_SS_I2C_SS_FS_SCL_CNT_HCNT_OFFSET
469 #define QM_SS_I2C_READ_FS_SCL_LCNT(controller) \
470 __builtin_arc_lr(controller + QM_SS_I2C_FS_SCL_CNT) & \
471 QM_SS_I2C_SS_FS_SCL_CNT_16BIT_MASK
472 #define QM_SS_I2C_READ_INTR_STAT(controller) \
473 __builtin_arc_lr(controller + QM_SS_I2C_INTR_STAT)
474 #define QM_SS_I2C_READ_INTR_MASK(controller) \
475 __builtin_arc_lr(controller + QM_SS_I2C_INTR_MASK)
476 #define QM_SS_I2C_READ_RX_TL(controller) \
477 __builtin_arc_lr(controller + QM_SS_I2C_TL) & QM_SS_I2C_TL_RX_TL_MASK
478 #define QM_SS_I2C_READ_TX_TL(controller) \
479 (__builtin_arc_lr(controller + QM_SS_I2C_TL) & \
480 QM_SS_I2C_TL_TX_TL_MASK) >> \
481 QM_SS_I2C_TL_TX_TL_OFFSET
482 #define QM_SS_I2C_READ_STATUS(controller) \
483 __builtin_arc_lr(controller + QM_SS_I2C_STATUS)
484 #define QM_SS_I2C_READ_TXFLR(controller) \
485 __builtin_arc_lr(controller + QM_SS_I2C_TXFLR)
486 #define QM_SS_I2C_READ_RXFLR(controller) \
487 __builtin_arc_lr(controller + QM_SS_I2C_RXFLR)
488 #define QM_SS_I2C_READ_TX_ABRT_SOURCE(controller) \
489 __builtin_arc_lr(controller + QM_SS_I2C_TX_ABRT_SOURCE)
490 #define QM_SS_I2C_READ_ENABLE_STATUS(controller) \
491 __builtin_arc_lr(controller + QM_SS_I2C_ENABLE_STATUS)
492
493 #define QM_SS_I2C_ABORT(controller) \
494 QM_SS_REG_AUX_OR((controller + QM_SS_I2C_CON), QM_SS_I2C_CON_ABORT)
495 #define QM_SS_I2C_ENABLE(controller) \
496 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_CON, QM_SS_I2C_CON_ENABLE)
497 #define QM_SS_I2C_DISABLE(controller) \
498 QM_SS_REG_AUX_NAND((controller + QM_SS_I2C_CON), QM_SS_I2C_CON_ENABLE)
499
500 #define QM_SS_I2C_MASK_ALL_INTERRUPTS(controller) \
501 __builtin_arc_sr(QM_SS_I2C_INTR_MASK_ALL, \
502 controller + QM_SS_I2C_INTR_MASK)
503 #define QM_SS_I2C_UNMASK_INTERRUPTS(controller) \
504 __builtin_arc_sr( \
505 (QM_SS_I2C_INTR_MASK_TX_ABRT | QM_SS_I2C_INTR_MASK_TX_EMPTY | \
506 QM_SS_I2C_INTR_MASK_TX_OVER | QM_SS_I2C_INTR_MASK_RX_FULL | \
507 QM_SS_I2C_INTR_MASK_RX_OVER | QM_SS_I2C_INTR_MASK_RX_UNDER), \
508 controller + QM_SS_I2C_INTR_MASK)
509 #define QM_SS_I2C_MASK_INTERRUPT(controller, value) \
510 QM_SS_REG_AUX_NAND(controller + QM_SS_I2C_INTR_MASK, value)
511
512 #define QM_SS_I2C_CLEAR_RX_UNDER_INTR(controller) \
513 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_INTR_CLR, \
514 QM_SS_I2C_INTR_CLR_RX_UNDER)
515 #define QM_SS_I2C_CLEAR_RX_OVER_INTR(controller) \
516 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_INTR_CLR, \
517 QM_SS_I2C_INTR_CLR_RX_OVER)
518 #define QM_SS_I2C_CLEAR_TX_OVER_INTR(controller) \
519 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_INTR_CLR, \
520 QM_SS_I2C_INTR_CLR_TX_OVER)
521 #define QM_SS_I2C_CLEAR_TX_ABRT_INTR(controller) \
522 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_INTR_CLR, \
523 QM_SS_I2C_INTR_CLR_TX_ABRT)
524 #define QM_SS_I2C_CLEAR_STOP_DET_INTR(controller) \
525 QM_SS_REG_AUX_OR(controller + QM_SS_I2C_INTR_CLR, \
526 QM_SS_I2C_INTR_CLR_STOP_DET)
527 #define QM_SS_I2C_CLEAR_ALL_INTR(controller) \
528 __builtin_arc_sr(QM_SS_I2C_INTR_CLR_ALL, \
529 controller + QM_SS_I2C_INTR_CLR)
530
531 /** Sensor Subsystem I2C */
532 typedef enum { QM_SS_I2C_0 = 0, QM_SS_I2C_1, QM_SS_I2C_NUM } qm_ss_i2c_t;
533
534 #define QM_SS_I2C_0_BASE (0x80012000)
535 #define QM_SS_I2C_1_BASE (0x80012100)
536
537 /** @} */
538 /** Sensor Subsystem ADC @{*/
539
540 /** Sensor Subsystem ADC registers */
541 typedef enum {
542 QM_SS_ADC_SET = 0, /**< ADC and sequencer settings register. */
543 QM_SS_ADC_DIVSEQSTAT, /**< ADC clock and sequencer status register. */
544 QM_SS_ADC_SEQ, /**< ADC sequence entry register. */
545 QM_SS_ADC_CTRL, /**< ADC control register. */
546 QM_SS_ADC_INTSTAT, /**< ADC interrupt status register. */
547 QM_SS_ADC_SAMPLE /**< ADC sample register. */
548 } qm_ss_adc_reg_t;
549
550 /** Sensor Subsystem ADC */
551 typedef enum {
552 QM_SS_ADC_0 = 0, /**< ADC first module. */
553 QM_SS_ADC_NUM
554 } qm_ss_adc_t;
555
556 /**
557 * SS ADC context type.
558 *
559 * The application should not modify the content of this structure.
560 *
561 * This structure is intented to be used by qm_ss_adc_save_context and
562 * qm_ss_adc_restore_context functions only.
563 */
564 typedef struct {
565 uint32_t adc_set; /**< ADC settings. */
566 uint32_t adc_divseqstat; /**< ADC clock divider and sequencer status. */
567 uint32_t adc_seq; /**< ADC sequencer entry. */
568 uint32_t adc_ctrl; /**< ADC control. */
569 } qm_ss_adc_context_t;
570
571 /* SS ADC register base. */
572 #define QM_SS_ADC_BASE (0x80015000)
573
574 /* For 1MHz, the max divisor is 7. */
575 #define QM_SS_ADC_DIV_MAX (7)
576
577 #define QM_SS_ADC_FIFO_LEN (32)
578
579 #define QM_SS_ADC_SET_POP_RX BIT(31)
580 #define QM_SS_ADC_SET_FLUSH_RX BIT(30)
581 #define QM_SS_ADC_SET_THRESHOLD_MASK (0x3F000000)
582 #define QM_SS_ADC_SET_THRESHOLD_OFFSET (24)
583 #define QM_SS_ADC_SET_SEQ_ENTRIES_MASK (0x3F0000)
584 #define QM_SS_ADC_SET_SEQ_ENTRIES_OFFSET (16)
585 #define QM_SS_ADC_SET_SEQ_MODE BIT(13)
586 #define QM_SS_ADC_SET_SAMPLE_WIDTH_MASK (0x1F)
587
588 #define QM_SS_ADC_DIVSEQSTAT_CLK_RATIO_MASK (0x1FFFFF)
589
590 #define QM_SS_ADC_CTRL_CLR_SEQERROR BIT(19)
591 #define QM_SS_ADC_CTRL_CLR_UNDERFLOW BIT(18)
592 #define QM_SS_ADC_CTRL_CLR_OVERFLOW BIT(17)
593 #define QM_SS_ADC_CTRL_CLR_DATA_A BIT(16)
594 #define QM_SS_ADC_CTRL_MSK_SEQERROR BIT(11)
595 #define QM_SS_ADC_CTRL_MSK_UNDERFLOW BIT(10)
596 #define QM_SS_ADC_CTRL_MSK_OVERFLOW BIT(9)
597 #define QM_SS_ADC_CTRL_MSK_DATA_A BIT(8)
598 #define QM_SS_ADC_CTRL_SEQ_TABLE_RST BIT(6)
599 #define QM_SS_ADC_CTRL_SEQ_PTR_RST BIT(5)
600 #define QM_SS_ADC_CTRL_SEQ_START BIT(4)
601 #define QM_SS_ADC_CTRL_CLK_ENA BIT(2)
602 #define QM_SS_ADC_CTRL_ADC_ENA BIT(1)
603
604 #define QM_SS_ADC_CTRL_MSK_ALL_INT (0xF00)
605 #define QM_SS_ADC_CTRL_CLR_ALL_INT (0xF0000)
606
607 #define QM_SS_ADC_SEQ_DELAYODD_OFFSET (21)
608 #define QM_SS_ADC_SEQ_MUXODD_OFFSET (16)
609 #define QM_SS_ADC_SEQ_DELAYEVEN_OFFSET (5)
610
611 #define QM_SS_ADC_SEQ_DUMMY (0x480)
612
613 #define QM_SS_ADC_INTSTAT_SEQERROR BIT(3)
614 #define QM_SS_ADC_INTSTAT_UNDERFLOW BIT(2)
615 #define QM_SS_ADC_INTSTAT_OVERFLOW BIT(1)
616 #define QM_SS_ADC_INTSTAT_DATA_A BIT(0)
617
618 /** End of Sensor Subsystem ADC @}*/
619
620 /**
621 * CREG Registers.
622 *
623 * @name SS CREG
624 * @{
625 */
626
627 /* Sensor Subsystem CREG */
628 typedef enum {
629 QM_SS_IO_CREG_MST0_CTRL = 0x0, /**< Master control register. */
630 QM_SS_IO_CREG_SLV0_OBSR = 0x80, /**< Slave control register. */
631 QM_SS_IO_CREG_SLV1_OBSR = 0x180 /**< Slave control register. */
632 } qm_ss_creg_reg_t;
633
634 /* MST0_CTRL fields */
635 #define QM_SS_IO_CREG_MST0_CTRL_ADC_PWR_MODE_OFFSET (1)
636 #define QM_SS_IO_CREG_MST0_CTRL_ADC_PWR_MODE_MASK (0x7)
637 #define QM_SS_IO_CREG_MST0_CTRL_ADC_DELAY_OFFSET (3)
638 #define QM_SS_IO_CREG_MST0_CTRL_ADC_DELAY_MASK (0xFFF8)
639 #define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_REQ BIT(16)
640 #define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_CMD_OFFSET (17)
641 #define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_CMD_MASK (0xE0000)
642 #define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_VAL_OFFSET (20)
643 #define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_VAL_MASK (0x7F00000)
644 #define QM_SS_IO_CREG_MST0_CTRL_ADC_CAL_VAL_MAX (0x7F)
645 #define QM_SS_IO_CREG_MST0_CTRL_SPI1_CLK_GATE BIT(27)
646 #define QM_SS_IO_CREG_MST0_CTRL_SPI0_CLK_GATE BIT(28)
647 #define QM_SS_IO_CREG_MST0_CTRL_I2C0_CLK_GATE BIT(29)
648 #define QM_SS_IO_CREG_MST0_CTRL_I2C1_CLK_GATE BIT(30)
649 #define QM_SS_IO_CREG_MST0_CTRL_ADC_CLK_GATE BIT(31)
650 /* SLV0_OBSR fields */
651 #define QM_SS_IO_CREG_SLV0_OBSR_ADC_CAL_VAL_OFFSET (5)
652 #define QM_SS_IO_CREG_SLV0_OBSR_ADC_CAL_VAL_MASK (0xFE0)
653 #define QM_SS_IO_CREG_SLV0_OBSR_ADC_CAL_ACK BIT(4)
654 #define QM_SS_IO_CREG_SLV0_OBSR_ADC_PWR_MODE_STS BIT(3)
655
656 #define SS_CLK_PERIPH_ALL_IN_CREG \
657 (SS_CLK_PERIPH_ADC | SS_CLK_PERIPH_I2C_1 | SS_CLK_PERIPH_I2C_0 | \
658 SS_CLK_PERIPH_SPI_1 | SS_CLK_PERIPH_SPI_0)
659
660 /* SS CREG base. */
661 #define QM_SS_CREG_BASE (0x80018000)
662
663 /** @} */
664
665 /**
666 * SPI registers and definitions.
667 *
668 * @name SS SPI
669 * @{
670 */
671
672 /* SS SPI FIFO depth */
673 #define QM_SS_SPI_FIFO_DEPTH (8)
674
675 /** Sensor Subsystem SPI register map. */
676 typedef enum {
677 QM_SS_SPI_CTRL = 0, /**< SPI control register. */
678 QM_SS_SPI_SPIEN = 2, /**< SPI enable register. */
679 QM_SS_SPI_TIMING = 4, /**< SPI serial clock divider value. */
680 QM_SS_SPI_FTLR, /**< Threshold value for TX/RX FIFO. */
681 QM_SS_SPI_TXFLR = 7, /**< Number of valid data entries in TX FIFO. */
682 QM_SS_SPI_RXFLR, /**< Number of valid data entries in RX FIFO. */
683 QM_SS_SPI_SR, /**< SPI status register. */
684 QM_SS_SPI_INTR_STAT, /**< Interrupt status register. */
685 QM_SS_SPI_INTR_MASK, /**< Interrupt mask register. */
686 QM_SS_SPI_CLR_INTR, /**< Interrupt clear register. */
687 QM_SS_SPI_DR, /**< RW buffer for FIFOs. */
688 } qm_ss_spi_reg_t;
689
690 /**
691 * Sensor Subsystem SPI context type.
692 *
693 * Applications should not modify the content.
694 * This structure is only intended to be used by
695 * the qm_ss_spi_save_context and qm_ss_spi_restore_context functions.
696 */
697 typedef struct {
698 uint32_t spi_ctrl; /**< Control Register. */
699 uint32_t spi_spien; /**< SPI Enable Register. */
700 uint32_t spi_timing; /**< Timing Register. */
701 } qm_ss_spi_context_t;
702
703 /** Sensor Subsystem SPI modules. */
704 typedef enum {
705 QM_SS_SPI_0 = 0, /**< SPI module 0 */
706 QM_SS_SPI_1, /**< SPI module 1 */
707 QM_SS_SPI_NUM
708 } qm_ss_spi_t;
709
710 #define QM_SS_SPI_0_BASE (0x80010000)
711 #define QM_SS_SPI_1_BASE (0x80010100)
712
713 #define QM_SS_SPI_CTRL_DFS_OFFS (0)
714 #define QM_SS_SPI_CTRL_DFS_MASK (0x0000000F)
715 #define QM_SS_SPI_CTRL_BMOD_OFFS (6)
716 #define QM_SS_SPI_CTRL_BMOD_MASK (0x000000C0)
717 #define QM_SS_SPI_CTRL_SCPH BIT(6)
718 #define QM_SS_SPI_CTRL_SCPOL BIT(7)
719 #define QM_SS_SPI_CTRL_TMOD_OFFS (8)
720 #define QM_SS_SPI_CTRL_TMOD_MASK (0x00000300)
721 #define QM_SS_SPI_CTRL_SRL BIT(11)
722 #define QM_SS_SPI_CTRL_CLK_ENA BIT(15)
723 #define QM_SS_SPI_CTRL_NDF_OFFS (16)
724 #define QM_SS_SPI_CTRL_NDF_MASK (0xFFFF0000)
725
726 #define QM_SS_SPI_SPIEN_EN BIT(0)
727 #define QM_SS_SPI_SPIEN_SER_OFFS (4)
728 #define QM_SS_SPI_SPIEN_SER_MASK (0x000000F0)
729
730 #define QM_SS_SPI_TIMING_SCKDV_OFFS (0)
731 #define QM_SS_SPI_TIMING_SCKDV_MASK (0x0000FFFF)
732 #define QM_SS_SPI_TIMING_RSD_OFFS (16)
733 #define QM_SS_SPI_TIMING_RSD_MASK (0x00FF0000)
734
735 #define QM_SS_SPI_FTLR_RFT_OFFS (0)
736 #define QM_SS_SPI_FTLR_RFT_MASK (0x0000FFFF)
737 #define QM_SS_SPI_FTLR_TFT_OFFS (16)
738 #define QM_SS_SPI_FTLR_TFT_MASK (0xFFFF0000)
739
740 #define QM_SS_SPI_SR_BUSY BIT(0)
741 #define QM_SS_SPI_SR_TFNF BIT(1)
742 #define QM_SS_SPI_SR_TFE BIT(2)
743 #define QM_SS_SPI_SR_RFNE BIT(3)
744 #define QM_SS_SPI_SR_RFF BIT(4)
745
746 #define QM_SS_SPI_INTR_TXEI BIT(0)
747 #define QM_SS_SPI_INTR_TXOI BIT(1)
748 #define QM_SS_SPI_INTR_RXUI BIT(2)
749 #define QM_SS_SPI_INTR_RXOI BIT(3)
750 #define QM_SS_SPI_INTR_RXFI BIT(4)
751 #define QM_SS_SPI_INTR_ALL (0x0000001F)
752
753 #define QM_SS_SPI_INTR_STAT_TXEI QM_SS_SPI_INTR_TXEI
754 #define QM_SS_SPI_INTR_STAT_TXOI QM_SS_SPI_INTR_TXOI
755 #define QM_SS_SPI_INTR_STAT_RXUI QM_SS_SPI_INTR_RXUI
756 #define QM_SS_SPI_INTR_STAT_RXOI QM_SS_SPI_INTR_RXOI
757 #define QM_SS_SPI_INTR_STAT_RXFI QM_SS_SPI_INTR_RXFI
758
759 #define QM_SS_SPI_INTR_MASK_TXEI QM_SS_SPI_INTR_TXEI
760 #define QM_SS_SPI_INTR_MASK_TXOI QM_SS_SPI_INTR_TXOI
761 #define QM_SS_SPI_INTR_MASK_RXUI QM_SS_SPI_INTR_RXUI
762 #define QM_SS_SPI_INTR_MASK_RXOI QM_SS_SPI_INTR_RXOI
763 #define QM_SS_SPI_INTR_MASK_RXFI QM_SS_SPI_INTR_RXFI
764
765 #define QM_SS_SPI_CLR_INTR_TXEI QM_SS_SPI_INTR_TXEI
766 #define QM_SS_SPI_CLR_INTR_TXOI QM_SS_SPI_INTR_TXOI
767 #define QM_SS_SPI_CLR_INTR_RXUI QM_SS_SPI_INTR_RXUI
768 #define QM_SS_SPI_CLR_INTR_RXOI QM_SS_SPI_INTR_RXOI
769 #define QM_SS_SPI_CLR_INTR_RXFI QM_SS_SPI_INTR_RXFI
770
771 #define QM_SS_SPI_DR_DR_OFFS (0)
772 #define QM_SS_SPI_DR_DR_MASK (0x0000FFFF)
773 #define QM_SS_SPI_DR_WR BIT(30)
774 #define QM_SS_SPI_DR_STROBE BIT(31)
775 #define QM_SS_SPI_DR_W_MASK (0xc0000000)
776 #define QM_SS_SPI_DR_R_MASK (0x80000000)
777
778 #define QM_SS_SPI_ENABLE_REG_WRITES(spi) \
779 QM_SS_REG_AUX_OR(spi + QM_SS_SPI_CTRL, QM_SS_SPI_CTRL_CLK_ENA)
780
781 #define QM_SS_SPI_CTRL_READ(spi) __builtin_arc_lr(spi + QM_SS_SPI_CTRL)
782
783 #define QM_SS_SPI_CTRL_WRITE(value, spi) \
784 __builtin_arc_sr(value, spi + QM_SS_SPI_CTRL)
785
786 #define QM_SS_SPI_BAUD_RATE_WRITE(value, spi) \
787 __builtin_arc_sr(value, spi + QM_SS_SPI_TIMING)
788
789 #define QM_SS_SPI_SER_WRITE(value, spi) \
790 QM_SS_REG_AUX_MASK_OR(spi + QM_SS_SPI_SPIEN, QM_SS_SPI_SPIEN_SER_MASK, \
791 value << QM_SS_SPI_SPIEN_SER_OFFS)
792
793 #define QM_SS_SPI_INTERRUPT_MASK_WRITE(value, spi) \
794 __builtin_arc_sr(value, spi + QM_SS_SPI_INTR_MASK)
795
796 #define QM_SS_SPI_INTERRUPT_MASK_NAND(value, spi) \
797 QM_SS_REG_AUX_NAND(spi + QM_SS_SPI_INTR_MASK, value)
798
799 #define QM_SS_SPI_NDF_WRITE(value, spi) \
800 QM_SS_REG_AUX_MASK_OR(spi + QM_SS_SPI_CTRL, QM_SS_SPI_CTRL_NDF_MASK, \
801 value << QM_SS_SPI_CTRL_NDF_OFFS)
802
803 #define QM_SS_SPI_INTERRUPT_STATUS_READ(spi) \
804 __builtin_arc_lr(spi + QM_SS_SPI_INTR_STAT)
805
806 #define QM_SS_SPI_INTERRUPT_CLEAR_WRITE(value, spi) \
807 __builtin_arc_sr(value, spi + QM_SS_SPI_CLR_INTR)
808
809 #define QM_SS_SPI_RFTLR_WRITE(value, spi) \
810 __builtin_arc_sr((value << QM_SS_SPI_FTLR_RFT_OFFS) & \
811 QM_SS_SPI_FTLR_RFT_MASK, \
812 spi + QM_SS_SPI_FTLR)
813
814 #define QM_SS_SPI_TFTLR_WRITE(value, spi) \
815 __builtin_arc_sr((value << QM_SS_SPI_FTLR_TFT_OFFS) & \
816 QM_SS_SPI_FTLR_TFT_MASK, \
817 spi + QM_SS_SPI_FTLR)
818
819 #define QM_SS_SPI_RFTLR_READ(spi) __builtin_arc_lr(spi + QM_SS_SPI_FTLR)
820
821 #define QM_SS_SPI_TFTLR_READ(spi) __builtin_arc_lr(spi + QM_SS_SPI_FTLR)
822
823 #define QM_SS_SPI_DUMMY_WRITE(spi) \
824 __builtin_arc_sr(QM_SS_SPI_DR_R_MASK, spi + QM_SS_SPI_DR)
825
826 /** @} */
827 /** @} */
828
829 #endif /* __SENSOR_REGISTERS_H__ */
QM_SS_ADC_SEQ
ADC sequence entry register.
Definition: qm_sensor_regs.h:544
qm_irq_context_t::status32_irq_threshold
uint32_t status32_irq_threshold
STATUS32 Interrupt Threshold.
Definition: qm_sensor_regs.h:97
QM_SS_SPI_SR
SPI status register.
Definition: qm_sensor_regs.h:683
qm_ss_spi_reg_t
qm_ss_spi_reg_t
Sensor Subsystem SPI register map.
Definition: qm_sensor_regs.h:676
qm_ss_gpio_context_t::gpio_swporta_ddr
uint32_t gpio_swporta_ddr
Port A Data Direction.
Definition: qm_sensor_regs.h:182
qm_ss_spi_context_t::spi_timing
uint32_t spi_timing
Timing Register.
Definition: qm_sensor_regs.h:700
qm_ss_adc_context_t::adc_ctrl
uint32_t adc_ctrl
ADC control.
Definition: qm_sensor_regs.h:568
QM_SS_ADC_DIVSEQSTAT
ADC clock and sequencer status register.
Definition: qm_sensor_regs.h:543
QM_SS_SPI_0
SPI module 0.
Definition: qm_sensor_regs.h:705
qm_ss_gpio_context_t::gpio_debounce
uint32_t gpio_debounce
Debounce Enable.
Definition: qm_sensor_regs.h:187
qm_ss_creg_reg_t
qm_ss_creg_reg_t
Definition: qm_sensor_regs.h:628
qm_ss_gpio_t
qm_ss_gpio_t
Sensor Subsystem GPIO.
Definition: qm_sensor_regs.h:196
qm_ss_spi_context_t
Sensor Subsystem SPI context type.
Definition: qm_sensor_regs.h:697
qm_ss_timer_t
qm_ss_timer_t
Sensor Subsystem Timers.
Definition: qm_sensor_regs.h:126
qm_ss_gpio_context_t::gpio_int_polarity
uint32_t gpio_int_polarity
Interrupt Polarity.
Definition: qm_sensor_regs.h:186
qm_irq_context_t::irq_ctrl
uint32_t irq_ctrl
Interrupt Context Saving Control Register.
Definition: qm_sensor_regs.h:99
qm_ss_i2c_t
qm_ss_i2c_t
Sensor Subsystem I2C.
Definition: qm_sensor_regs.h:532
qm_irq_context_t::status32_irq_enable
uint32_t status32_irq_enable
STATUS32 Interrupt Enable.
Definition: qm_sensor_regs.h:98
QM_SS_SPI_INTR_MASK
Interrupt mask register.
Definition: qm_sensor_regs.h:685
qm_ss_adc_t
qm_ss_adc_t
Sensor Subsystem ADC.
Definition: qm_sensor_regs.h:551
qm_ss_gpio_reg_t
qm_ss_gpio_reg_t
Sensor Subsystem GPIO register block type.
Definition: qm_sensor_regs.h:159
QM_SS_ADC_CTRL
ADC control register.
Definition: qm_sensor_regs.h:545
QM_SS_IO_CREG_SLV0_OBSR
Slave control register.
Definition: qm_sensor_regs.h:630
QM_SS_ADC_SET
ADC and sequencer settings register.
Definition: qm_sensor_regs.h:542
qm_ss_gpio_context_t::gpio_intmask
uint32_t gpio_intmask
Interrupt Mask.
Definition: qm_sensor_regs.h:184
QM_SS_ADC_INTSTAT
ADC interrupt status register.
Definition: qm_sensor_regs.h:546
QM_SS_ADC_0
ADC first module.
Definition: qm_sensor_regs.h:552
QM_SS_SPI_DR
RW buffer for FIFOs.
Definition: qm_sensor_regs.h:687
QM_SS_SPI_CLR_INTR
Interrupt clear register.
Definition: qm_sensor_regs.h:686
QM_SS_SPI_TIMING
SPI serial clock divider value.
Definition: qm_sensor_regs.h:679
QM_SS_SPI_INTR_STAT
Interrupt status register.
Definition: qm_sensor_regs.h:684
qm_ss_gpio_context_t::gpio_inttype_level
uint32_t gpio_inttype_level
Interrupt Type.
Definition: qm_sensor_regs.h:185
QM_SS_SPI_TXFLR
Number of valid data entries in TX FIFO.
Definition: qm_sensor_regs.h:681
QM_SS_SPI_1
SPI module 1.
Definition: qm_sensor_regs.h:706
QM_SS_ADC_SAMPLE
ADC sample register.
Definition: qm_sensor_regs.h:547
QM_SS_SPI_SPIEN
SPI enable register.
Definition: qm_sensor_regs.h:678
QM_SS_IO_CREG_MST0_CTRL
Master control register.
Definition: qm_sensor_regs.h:629
qm_ss_adc_context_t
SS ADC context type.
Definition: qm_sensor_regs.h:564
qm_ss_gpio_context_t::gpio_inten
uint32_t gpio_inten
Interrupt Enable.
Definition: qm_sensor_regs.h:183
qm_ss_adc_context_t::adc_set
uint32_t adc_set
ADC settings.
Definition: qm_sensor_regs.h:565
QM_SS_SPI_CTRL
SPI control register.
Definition: qm_sensor_regs.h:677
QM_SS_IO_CREG_SLV1_OBSR
Slave control register.
Definition: qm_sensor_regs.h:631
qm_ss_adc_context_t::adc_seq
uint32_t adc_seq
ADC sequencer entry.
Definition: qm_sensor_regs.h:567
qm_ss_i2c_context_t
SS I2C context type.
Definition: qm_sensor_regs.h:235
qm_ss_gpio_context_t
SS GPIO context type.
Definition: qm_sensor_regs.h:180
qm_ss_spi_context_t::spi_ctrl
uint32_t spi_ctrl
Control Register.
Definition: qm_sensor_regs.h:698
qm_ss_gpio_context_t::gpio_swporta_dr
uint32_t gpio_swporta_dr
Port A Data.
Definition: qm_sensor_regs.h:181
qm_ss_spi_context_t::spi_spien
uint32_t spi_spien
SPI Enable Register.
Definition: qm_sensor_regs.h:699
qm_ss_spi_t
qm_ss_spi_t
Sensor Subsystem SPI modules.
Definition: qm_sensor_regs.h:704
qm_ss_adc_reg_t
qm_ss_adc_reg_t
Sensor Subsystem ADC.
Definition: qm_sensor_regs.h:541
QM_SS_SPI_RXFLR
Number of valid data entries in RX FIFO.
Definition: qm_sensor_regs.h:682
QM_SS_SPI_FTLR
Threshold value for TX/RX FIFO.
Definition: qm_sensor_regs.h:680
qm_ss_adc_context_t::adc_divseqstat
uint32_t adc_divseqstat
ADC clock divider and sequencer status.
Definition: qm_sensor_regs.h:566
qm_irq_context_t
SS IRQ context type.
Definition: qm_sensor_regs.h:96
qm_ss_i2c_reg_t
qm_ss_i2c_reg_t
Sensor Subsystem I2C register block type.
Definition: qm_sensor_regs.h:211
qm_ss_gpio_context_t::gpio_ls_sync
uint32_t gpio_ls_sync
Synchronization Level.
Definition: qm_sensor_regs.h:188