Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_interrupt_router_regs.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __QM_INTERRUPT_ROUTER_REGS_H__
6 #define __QM_INTERRUPT_ROUTER_REGS_H__
7
8 /**
9 * Quark D2000 SoC Interrupt Router registers.
10 *
11 * @defgroup groupQUARKD2000INTERRUPTROUTER SoC Interrupt Router (D2000)
12 * @{
13 */
14
15 /**
16 * Masks for single source interrupts in the Interrupt Router.
17 * To enable: reg &= ~(MASK)
18 * To disable: reg |= MASK;
19 */
20 #define QM_IR_INT_LMT_MASK BIT(0)
21
22 /* Masks for single source halts in the Interrupt Router. */
23 #define QM_IR_INT_LMT_HALT_MASK BIT(16)
24
25 /**
26 * Interrupt Router macros to determine if the specified peripheral interrupt
27 * mask has been locked.
28 */
29 #define QM_IR_LMT_INT_LOCK_HALT_MASK(_peripheral_) \
30 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(2))
31 #define QM_IR_LMT_INT_LOCK_MASK(_peripheral_) \
32 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(0))
33
34 /* Interrupt Router Unmask interrupts for a peripheral. */
35 #define QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_) \
36 (_peripheral_ &= ~(QM_IR_INT_LMT_MASK))
37
38 /* Mask interrupts for a peripheral. */
39 #define QM_IR_MASK_LMT_INTERRUPTS(_peripheral_) \
40 (_peripheral_ |= QM_IR_INT_LMT_MASK)
41
42 /* Unmask halt for a peripheral. */
43 #define QM_IR_UNMASK_LMT_HALTS(_peripheral_) \
44 (_peripheral_ &= ~(QM_IR_INT_LMT_HALT_MASK))
45
46 /* Mask halt for a peripheral. */
47 #define QM_IR_MASK_LMT_HALTS(_peripheral_) \
48 (_peripheral_ |= QM_IR_INT_LMT_HALT_MASK)
49
50 #define QM_IR_GET_LMT_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_LMT_MASK)
51 #define QM_IR_GET_LMT_HALT_MASK(_peripheral_) \
52 (_peripheral_ & QM_IR_INT_LMT_HALT_MASK)
53
54 /* Define macros for use by the active core. */
55 #if (QM_LAKEMONT)
56 #define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
57 QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_)
58 #define QM_IR_MASK_INTERRUPTS(_peripheral_) \
59 QM_IR_MASK_LMT_INTERRUPTS(_peripheral_)
60 #define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_LMT_HALTS(_peripheral_)
61 #define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_LMT_HALTS(_peripheral_)
62
63 #define QM_IR_INT_LOCK_MASK(_peripheral_) QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
64 #define QM_IR_INT_LOCK_HALT_MASK(_peripheral_) \
65 QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
66
67 #define QM_IR_INT_MASK QM_IR_INT_LMT_MASK
68 #define QM_IR_INT_HALT_MASK QM_IR_INT_LMT_HALT_MASK
69 #define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_LMT_MASK(_peripheral_)
70 #define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_LMT_HALT_MASK(_peripheral_)
71
72 #else
73 #error "No active core selected."
74 #endif
75
76 /** Interrupt register map. */
77 typedef struct {
78 QM_RW uint32_t i2c_master_0_int_mask; /**< I2C Master 0, Mask 0. */
79 QM_R uint32_t reserved[2];
80 QM_RW uint32_t spi_master_0_int_mask; /**< SPI Master 0, Mask 3. */
81 QM_R uint32_t reserved1;
82 QM_RW uint32_t spi_slave_0_int_mask; /**< SPI Slave 0, Mask 5. */
83 QM_RW uint32_t uart_0_int_mask; /**< UART 0, Mask 6. */
84 QM_RW uint32_t uart_1_int_mask; /**< UART 1, Mask 7. */
85 QM_RW uint32_t reserved2;
86 QM_RW uint32_t gpio_0_int_mask; /**< GPIO 0, Mask 9. */
87 QM_RW uint32_t timer_0_int_mask; /**< Timer 0, Mask 10. */
88 QM_R uint32_t reserved3;
89 QM_RW uint32_t rtc_0_int_mask; /**< RTC 0, Mask 12. */
90 QM_RW uint32_t wdt_0_int_mask; /**< WDT 0, Mask 13. */
91 QM_RW uint32_t dma_0_int_0_mask; /**< DMA 0 int 0, Mask 14. */
92 QM_RW uint32_t dma_0_int_1_mask; /**< DMA 0 int 1, Mask 15. */
93 QM_RW uint32_t reserved4[8];
94 /** Comparator 0 Host halt, Mask 24. */
95 QM_RW uint32_t comparator_0_host_halt_int_mask;
96 QM_R uint32_t reserved5;
97 /** Comparator 0 Host, Mask 26. */
98 QM_RW uint32_t comparator_0_host_int_mask;
99 QM_RW uint32_t host_bus_error_int_mask; /**< Host bus error, Mask 27. */
100 QM_RW uint32_t dma_0_error_int_mask; /**< DMA 0 Error, Mask 28. */
101 QM_RW uint32_t sram_mpr_0_int_mask; /**< SRAM MPR 0, Mask 29. */
102 QM_RW uint32_t flash_mpr_0_int_mask; /**< Flash MPR 0, Mask 30. */
103 QM_R uint32_t reserved6;
104 QM_RW uint32_t aonpt_0_int_mask; /**< AONPT 0, Mask 32. */
105 QM_RW uint32_t adc_0_pwr_int_mask; /**< ADC 0 PWR, Mask 33. */
106 QM_RW uint32_t adc_0_cal_int_mask; /**< ADC 0 CAL, Mask 34. */
107 QM_R uint32_t reserved7;
108 QM_RW uint32_t lock_int_mask_reg; /**< Interrupt Mask Lock Register. */
109 } qm_interrupt_router_reg_t;
110
111 /* Number of interrupt mask registers (excluding mask lock register). */
112 #define QM_INTERRUPT_ROUTER_MASK_NUMREG \
113 ((sizeof(qm_interrupt_router_reg_t) / sizeof(uint32_t)) - 1)
114
115 /* Default POR interrupt mask (all interrupts masked). */
116 #define QM_INTERRUPT_ROUTER_MASK_DEFAULT (0xFFFFFFFF)
117
118 #if (UNIT_TEST)
119 qm_interrupt_router_reg_t test_interrupt_router;
120 #define QM_INTERRUPT_ROUTER \
121 ((qm_interrupt_router_reg_t *)(&test_interrupt_router))
122
123 #else
124 #define QM_INTERRUPT_ROUTER_BASE (0xB0800448)
125 #define QM_INTERRUPT_ROUTER \
126 ((qm_interrupt_router_reg_t *)QM_INTERRUPT_ROUTER_BASE)
127 #endif
128
129 #define QM_IR_DMA_ERROR_HOST_MASK (0x00000003)
130
131 /** @} */
132
133 #endif /* __QM_INTERRUPT_ROUTER_REGS_H__ */
qm_interrupt_router_reg_t::dma_0_error_int_mask
QM_RW uint32_t dma_0_error_int_mask
DMA 0 Error, Mask 28.
Definition: qm_interrupt_router_regs.h:100
qm_interrupt_router_reg_t::i2c_master_0_int_mask
QM_RW uint32_t i2c_master_0_int_mask
I2C Master 0, Mask 0.
Definition: qm_interrupt_router_regs.h:78
qm_interrupt_router_reg_t::sram_mpr_0_int_mask
QM_RW uint32_t sram_mpr_0_int_mask
SRAM MPR 0, Mask 29.
Definition: qm_interrupt_router_regs.h:101
qm_interrupt_router_reg_t::dma_0_int_0_mask
QM_RW uint32_t dma_0_int_0_mask
DMA 0 int 0, Mask 14.
Definition: qm_interrupt_router_regs.h:91
qm_interrupt_router_reg_t::uart_0_int_mask
QM_RW uint32_t uart_0_int_mask
UART 0, Mask 6.
Definition: qm_interrupt_router_regs.h:83
qm_interrupt_router_reg_t::aonpt_0_int_mask
QM_RW uint32_t aonpt_0_int_mask
AONPT 0, Mask 32.
Definition: qm_interrupt_router_regs.h:104
qm_interrupt_router_reg_t::adc_0_pwr_int_mask
QM_RW uint32_t adc_0_pwr_int_mask
ADC 0 PWR, Mask 33.
Definition: qm_interrupt_router_regs.h:105
qm_interrupt_router_reg_t::dma_0_int_1_mask
QM_RW uint32_t dma_0_int_1_mask
DMA 0 int 1, Mask 15.
Definition: qm_interrupt_router_regs.h:92
qm_interrupt_router_reg_t::gpio_0_int_mask
QM_RW uint32_t gpio_0_int_mask
GPIO 0, Mask 9.
Definition: qm_interrupt_router_regs.h:86
qm_interrupt_router_reg_t::wdt_0_int_mask
QM_RW uint32_t wdt_0_int_mask
WDT 0, Mask 13.
Definition: qm_interrupt_router_regs.h:90
qm_interrupt_router_reg_t
Interrupt register map.
Definition: qm_interrupt_router_regs.h:77
qm_interrupt_router_reg_t::rtc_0_int_mask
QM_RW uint32_t rtc_0_int_mask
RTC 0, Mask 12.
Definition: qm_interrupt_router_regs.h:89
qm_interrupt_router_reg_t::comparator_0_host_halt_int_mask
QM_RW uint32_t comparator_0_host_halt_int_mask
Comparator 0 Host halt, Mask 24.
Definition: qm_interrupt_router_regs.h:95
qm_interrupt_router_reg_t::timer_0_int_mask
QM_RW uint32_t timer_0_int_mask
Timer 0, Mask 10.
Definition: qm_interrupt_router_regs.h:87
qm_interrupt_router_reg_t::spi_master_0_int_mask
QM_RW uint32_t spi_master_0_int_mask
SPI Master 0, Mask 3.
Definition: qm_interrupt_router_regs.h:80
qm_interrupt_router_reg_t::spi_slave_0_int_mask
QM_RW uint32_t spi_slave_0_int_mask
SPI Slave 0, Mask 5.
Definition: qm_interrupt_router_regs.h:82
qm_interrupt_router_reg_t::lock_int_mask_reg
QM_RW uint32_t lock_int_mask_reg
Interrupt Mask Lock Register.
Definition: qm_interrupt_router_regs.h:108
qm_interrupt_router_reg_t::adc_0_cal_int_mask
QM_RW uint32_t adc_0_cal_int_mask
ADC 0 CAL, Mask 34.
Definition: qm_interrupt_router_regs.h:106
qm_interrupt_router_reg_t::host_bus_error_int_mask
QM_RW uint32_t host_bus_error_int_mask
Host bus error, Mask 27.
Definition: qm_interrupt_router_regs.h:99
qm_interrupt_router_reg_t::uart_1_int_mask
QM_RW uint32_t uart_1_int_mask
UART 1, Mask 7.
Definition: qm_interrupt_router_regs.h:84
qm_interrupt_router_reg_t::comparator_0_host_int_mask
QM_RW uint32_t comparator_0_host_int_mask
Comparator 0 Host, Mask 26.
Definition: qm_interrupt_router_regs.h:98
qm_interrupt_router_reg_t::flash_mpr_0_int_mask
QM_RW uint32_t flash_mpr_0_int_mask
Flash MPR 0, Mask 30.
Definition: qm_interrupt_router_regs.h:102