Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_soc_interrupts.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __QM_SOC_INTERRUPTS_H__
6 #define __QM_SOC_INTERRUPTS_H__
7
8 /**
9 * Quark SE SoC Interrupts.
10 *
11 * @defgroup groupQUARKSESEINT SoC Interrupts (SE)
12 * @{
13 */
14
15 #if (QM_LAKEMONT)
16
17 /* x86 internal interrupt vectors. */
18 #define QM_X86_DIVIDE_ERROR_INT (0)
19 #define QM_X86_DEBUG_EXCEPTION_INT (1)
20 #define QM_X86_NMI_INTERRUPT_INT (2)
21 #define QM_X86_BREAKPOINT_INT (3)
22 #define QM_X86_OVERFLOW_INT (4)
23 #define QM_X86_BOUND_RANGE_EXCEEDED_INT (5)
24 #define QM_X86_INVALID_OPCODE_INT (6)
25 #define QM_X86_DEVICE_NOT_AVAILABLE_INT (7)
26 #define QM_X86_DOUBLE_FAULT_INT (8)
27 #define QM_X86_INTEL_RESERVED_09_INT (9)
28 #define QM_X86_INVALID_TSS_INT (10)
29 #define QM_X86_SEGMENT_NOT_PRESENT_INT (11)
30 #define QM_X86_STACK_SEGMENT_FAULT_INT (12)
31 #define QM_X86_GENERAL_PROTECT_FAULT_INT (13)
32 #define QM_X86_PAGE_FAULT_INT (14)
33 #define QM_X86_INTEL_RESERVED_15_INT (15)
34 #define QM_X86_FLOATING_POINT_ERROR_INT (16)
35 #define QM_X86_ALIGNMENT_CHECK_INT (17)
36 #define QM_X86_INTEL_RESERVED_18_INT (18)
37 #define QM_X86_INTEL_RESERVED_19_INT (19)
38 #define QM_X86_INTEL_RESERVED_20_INT (20)
39 #define QM_X86_INTEL_RESERVED_21_INT (21)
40 #define QM_X86_INTEL_RESERVED_22_INT (22)
41 #define QM_X86_INTEL_RESERVED_23_INT (23)
42 #define QM_X86_INTEL_RESERVED_24_INT (24)
43 #define QM_X86_INTEL_RESERVED_25_INT (25)
44 #define QM_X86_INTEL_RESERVED_26_INT (26)
45 #define QM_X86_INTEL_RESERVED_27_INT (27)
46 #define QM_X86_INTEL_RESERVED_28_INT (28)
47 #define QM_X86_INTEL_RESERVED_29_INT (29)
48 #define QM_X86_INTEL_RESERVED_30_INT (30)
49 #define QM_X86_INTEL_RESERVED_31_INT (31)
50
51 #define QM_X86_PIC_TIMER_INT_VECTOR (32)
52
53 #endif /* QM_LAKEMONT */
54
55 #if (QM_SENSOR)
56
57 /* ARC EM processor internal interrupt vector assignments. */
58 #define QM_ARC_RESET_INT (0)
59 #define QM_ARC_MEMORY_ERROR_INT (1)
60 #define QM_ARC_INSTRUCTION_ERROR_INT (2)
61 #define QM_ARC_MACHINE_CHECK_EXCEPTION_INT (3)
62 #define QM_ARC_INSTRUCTION_TLB_MISS_INT (4)
63 #define QM_ARC_DATA_TLB_MISS_INT (5)
64 #define QM_ARC_PROTECTION_VIOLATION_INT (6)
65 #define QM_ARC_PRIVILEGE_VIOLATION_INT (7)
66 #define QM_ARC_SOFTWARE_INTERRUPT_INT (8)
67 #define QM_ARC_TRAP_INT (9)
68 #define QM_ARC_EXTENSION_INSTRUCTION_EXCEPTION_INT (10)
69 #define QM_ARC_DIVIDE_BY_ZERO_INT (11)
70 #define QM_ARC_DATA_CACHE_CONSISTENCY_ERROR_INT (12)
71 #define QM_ARC_MISALIGNED_DATA_ACCESS_INT (13)
72 #define QM_ARC_RESERVED_14_INT (14)
73 #define QM_ARC_RESERVED_15_INT (15)
74 #define QM_ARC_TIMER_0_INT (16)
75 #define QM_ARC_TIMER_1_INT (17)
76
77 #endif /* QM_SENSOR */
78
79 #if (QM_SENSOR)
80 /**
81 * Sensor Sub-System Specific IRQs and interrupt vectors.
82 *
83 * @name SS Interrupt
84 * @{
85 */
86
87 #define QM_SS_EXCEPTION_NUM (16) /* Exceptions and traps in ARC EM core. */
88 #define QM_SS_INT_TIMER_NUM (2) /* Internal interrupts in ARC EM core. */
89 #define QM_SS_IRQ_SENSOR_NUM (18) /* IRQ's from the Sensor Subsystem. */
90 #define QM_SS_IRQ_COMMON_NUM (32) /* IRQ's from the common SoC fabric. */
91 #define QM_SS_INT_VECTOR_NUM \
92 (QM_SS_EXCEPTION_NUM + QM_SS_INT_TIMER_NUM + QM_SS_IRQ_SENSOR_NUM + \
93 QM_SS_IRQ_COMMON_NUM)
94 #define QM_SS_IRQ_NUM (QM_SS_IRQ_SENSOR_NUM + QM_SS_IRQ_COMMON_NUM)
95
96 /*
97 * The following definitions are Sensor Subsystem interrupt irq and vector
98 * numbers:
99 * #define QM_SS_xxx - irq number
100 * #define QM_SS_xxx_VECTOR - vector number
101 */
102
103 /** Sensor Subsystem ADC Rx Fifo Error Interrupt. */
104 #define QM_SS_IRQ_ADC_0_ERROR_INT 0
105 #define QM_SS_IRQ_ADC_0_ERROR_INT_VECTOR 18
106
107 /** Sensor Subsystem ADC Data Available Interrupt. */
108 #define QM_SS_IRQ_ADC_0_INT 1
109 #define QM_SS_IRQ_ADC_0_INT_VECTOR 19
110
111 /** Sensor Subsystem GPIO Single Interrupt 0 */
112 #define QM_SS_IRQ_GPIO_0_INT 2
113 #define QM_SS_IRQ_GPIO_0_INT_VECTOR 20
114
115 /** Sensor Subsystem GPIO Single Interrupt 1. */
116 #define QM_SS_IRQ_GPIO_1_INT 3
117 #define QM_SS_IRQ_GPIO_1_INT_VECTOR 21
118
119 /** Sensor Subsystem I2C 0 Error Interrupt. */
120 #define QM_SS_IRQ_I2C_0_ERROR_INT 4
121 #define QM_SS_IRQ_I2C_0_ERROR_INT_VECTOR 22
122
123 /** Sensor Subsystem I2C 0 Data Available Interrupt. */
124 #define QM_SS_IRQ_I2C_0_RX_AVAIL_INT 5
125 #define QM_SS_IRQ_I2C_0_RX_AVAIL_INT_VECTOR 23
126
127 /** Sensor Subsystem I2C 0 Data Required Interrupt. */
128 #define QM_SS_IRQ_I2C_0_TX_REQ_INT 6
129 #define QM_SS_IRQ_I2C_0_TX_REQ_INT_VECTOR 24
130
131 /** Sensor Subsystem I2C 0 Stop Detect Interrupt. */
132 #define QM_SS_IRQ_I2C_0_STOP_DET_INT 7
133 #define QM_SS_IRQ_I2C_0_STOP_DET_INT_VECTOR 25
134
135 /** Sensor Subsystem I2C 1 Error Interrupt. */
136 #define QM_SS_IRQ_I2C_1_ERROR_INT 8
137 #define QM_SS_IRQ_I2C_1_ERROR_INT_VECTOR 26
138
139 /** Sensor Subsystem I2C 1 Data Available Interrupt. */
140 #define QM_SS_IRQ_I2C_1_RX_AVAIL_INT 9
141 #define QM_SS_IRQ_I2C_1_RX_AVAIL_INT_VECTOR 27
142
143 /** Sensor Subsystem I2C 1 Data Required Interrupt. */
144 #define QM_SS_IRQ_I2C_1_TX_REQ_INT 10
145 #define QM_SS_IRQ_I2C_1_TX_REQ_INT_VECTOR 28
146
147 /** Sensor Subsystem I2C 1 Stop Detect Interrupt. */
148 #define QM_SS_IRQ_I2C_1_STOP_DET_INT 11
149 #define QM_SS_IRQ_I2C_1_STOP_DET_INT_VECTOR 29
150
151 /** Sensor Subsystem SPI 0 Error Interrupt. */
152 #define QM_SS_IRQ_SPI_0_ERROR_INT 12
153 #define QM_SS_IRQ_SPI_0_ERROR_INT_VECTOR 30
154
155 /** Sensor Subsystem SPI 0 Data Available Interrupt. */
156 #define QM_SS_IRQ_SPI_0_RX_AVAIL_INT 13
157 #define QM_SS_IRQ_SPI_0_RX_AVAIL_INT_VECTOR 31
158
159 /** Sensor Subsystem SPI 0 Data Required Interrupt. */
160 #define QM_SS_IRQ_SPI_0_TX_REQ_INT 14
161 #define QM_SS_IRQ_SPI_0_TX_REQ_INT_VECTOR 32
162
163 /** Sensor Subsystem SPI 1 Error Interrupt. */
164 #define QM_SS_IRQ_SPI_1_ERROR_INT 15
165 #define QM_SS_IRQ_SPI_1_ERROR_INT_VECTOR 33
166
167 /** Sensor Subsystem SPI 1 Data Available Interrupt. */
168 #define QM_SS_IRQ_SPI_1_RX_AVAIL_INT 16
169 #define QM_SS_IRQ_SPI_1_RX_AVAIL_INT_VECTOR 34
170
171 /** Sensor Subsystem SPI 1 Data Required Interrupt. */
172 #define QM_SS_IRQ_SPI_1_TX_REQ_INT 17
173 #define QM_SS_IRQ_SPI_1_TX_REQ_INT_VECTOR 35
174
175 typedef enum {
176 QM_SS_INT_PRIORITY_0 = 0,
177 QM_SS_INT_PRIORITY_1 = 1,
178 QM_SS_INT_PRIORITY_15 = 15,
179 QM_SS_INT_PRIORITY_NUM
180 } qm_ss_irq_priority_t;
181
182 typedef enum { QM_SS_INT_DISABLE = 0, QM_SS_INT_ENABLE = 1 } qm_ss_irq_mask_t;
183
184 typedef enum {
185 QM_SS_IRQ_LEVEL_SENSITIVE = 0,
186 QM_SS_IRQ_EDGE_SENSITIVE = 1
187 } qm_ss_irq_trigger_t;
188
189 #define QM_SS_AUX_IRQ_CTRL (0xE)
190 #define QM_SS_AUX_IRQ_HINT (0x201)
191 #define QM_SS_AUX_IRQ_PRIORITY (0x206)
192 #define QM_SS_AUX_IRQ_STATUS (0x406)
193 #define QM_SS_AUX_IRQ_SELECT (0x40B)
194 #define QM_SS_AUX_IRQ_ENABLE (0x40C)
195 #define QM_SS_AUX_IRQ_TRIGGER (0x40D)
196
197 /** @} */
198
199 #endif /* QM_SENSOR */
200
201 /**
202 * @name Common SoC IRQs and Interrupts
203 * @{
204 */
205
206 /* IRQs and interrupt vectors.
207 *
208 * Any IRQ > 1 actually has a event router mask register offset of +1.
209 * The vector numbers must be defined without arithmetic expressions nor
210 * parentheses because they are expanded as token concatenation.
211 */
212
213 /** I2C Master 0 Single Interrupt. */
214 #define QM_IRQ_I2C_0_INT 0
215 #define QM_IRQ_I2C_0_INT_MASK_OFFSET 0
216 #define QM_IRQ_I2C_0_INT_VECTOR 36
217
218 /** I2C Master 1 Single Interrupt. */
219 #define QM_IRQ_I2C_1_INT 1
220 #define QM_IRQ_I2C_1_INT_MASK_OFFSET 1
221 #define QM_IRQ_I2C_1_INT_VECTOR 37
222
223 /** SPI Master 0 Single Interrupt. */
224 #define QM_IRQ_SPI_MASTER_0_INT 2
225 #define QM_IRQ_SPI_MASTER_0_INT_MASK_OFFSET 3
226 #define QM_IRQ_SPI_MASTER_0_INT_VECTOR 38
227
228 /** SPI Master 1 Single Interrupt. */
229 #define QM_IRQ_SPI_MASTER_1_INT 3
230 #define QM_IRQ_SPI_MASTER_1_INT_MASK_OFFSET 4
231 #define QM_IRQ_SPI_MASTER_1_INT_VECTOR 39
232
233 /** SPI Slave Single Interrupt. */
234 #define QM_IRQ_SPI_SLAVE_0_INT 4
235 #define QM_IRQ_SPI_SLAVE_0_INT_MASK_OFFSET 5
236 #define QM_IRQ_SPI_SLAVE_0_INT_VECTOR 40
237
238 /** UART 0 Single Interrupt. */
239 #define QM_IRQ_UART_0_INT 5
240 #define QM_IRQ_UART_0_INT_MASK_OFFSET 6
241 #define QM_IRQ_UART_0_INT_VECTOR 41
242
243 /** UART 1 Single Interrupt. */
244 #define QM_IRQ_UART_1_INT 6
245 #define QM_IRQ_UART_1_INT_MASK_OFFSET 7
246 #define QM_IRQ_UART_1_INT_VECTOR 42
247
248 /** I2S Single Interrupt. */
249 #define QM_IRQ_I2S_0_INT 7
250 #define QM_IRQ_I2S_0_INT_MASK_OFFSET 8
251 #define QM_IRQ_I2S_0_INT_VECTOR 43
252
253 /** GPIO Single Interrupt. */
254 #define QM_IRQ_GPIO_0_INT 8
255 #define QM_IRQ_GPIO_0_INT_MASK_OFFSET 9
256 #define QM_IRQ_GPIO_0_INT_VECTOR 44
257
258 /** PWM/Timer Single Interrupt. */
259 #define QM_IRQ_PWM_0_INT 9
260 #define QM_IRQ_PWM_0_INT_MASK_OFFSET 10
261 #define QM_IRQ_PWM_0_INT_VECTOR 45
262
263 /** USB Single Interrupt. */
264 #define QM_IRQ_USB_0_INT (10)
265 #define QM_IRQ_USB_0_INT_MASK_OFFSET (11)
266 #define QM_IRQ_USB_0_INT_VECTOR 46
267
268 /** RTC Single Interrupt. */
269 #define QM_IRQ_RTC_0_INT 11
270 #define QM_IRQ_RTC_0_INT_MASK_OFFSET 12
271 #define QM_IRQ_RTC_0_INT_VECTOR 47
272
273 /** WDT Single Interrupt. */
274 #define QM_IRQ_WDT_0_INT 12
275 #define QM_IRQ_WDT_0_INT_MASK_OFFSET 13
276 #define QM_IRQ_WDT_0_INT_VECTOR 48
277
278 /** DMA Channel 0 Single Interrupt. */
279 #define QM_IRQ_DMA_0_INT_0 13
280 #define QM_IRQ_DMA_0_INT_0_MASK_OFFSET 14
281 #define QM_IRQ_DMA_0_INT_0_VECTOR 49
282
283 /** DMA Channel 1 Single Interrupt. */
284 #define QM_IRQ_DMA_0_INT_1 14
285 #define QM_IRQ_DMA_0_INT_1_MASK_OFFSET 15
286 #define QM_IRQ_DMA_0_INT_1_VECTOR 50
287
288 /** DMA Channel 2 Single Interrupt. */
289 #define QM_IRQ_DMA_0_INT_2 15
290 #define QM_IRQ_DMA_0_INT_2_MASK_OFFSET 16
291 #define QM_IRQ_DMA_0_INT_2_VECTOR 51
292
293 /** DMA Channel 3 Single Interrupt. */
294 #define QM_IRQ_DMA_0_INT_3 16
295 #define QM_IRQ_DMA_0_INT_3_MASK_OFFSET 17
296 #define QM_IRQ_DMA_0_INT_3_VECTOR 52
297
298 /** DMA Channel 4 Single Interrupt. */
299 #define QM_IRQ_DMA_0_INT_4 17
300 #define QM_IRQ_DMA_0_INT_4_MASK_OFFSET 18
301 #define QM_IRQ_DMA_0_INT_4_VECTOR 53
302
303 /** DMA Channel 5 Single Interrupt. */
304 #define QM_IRQ_DMA_0_INT_5 18
305 #define QM_IRQ_DMA_0_INT_5_MASK_OFFSET 19
306 #define QM_IRQ_DMA_0_INT_5_VECTOR 54
307
308 /** DMA Channel 6 Single Interrupt. */
309 #define QM_IRQ_DMA_0_INT_6 19
310 #define QM_IRQ_DMA_0_INT_6_MASK_OFFSET 20
311 #define QM_IRQ_DMA_0_INT_6_VECTOR 55
312
313 /** DMA Channel 7 Single Interrupt. */
314 #define QM_IRQ_DMA_0_INT_7 20
315 #define QM_IRQ_DMA_0_INT_7_MASK_OFFSET 21
316 #define QM_IRQ_DMA_0_INT_7_VECTOR 56
317
318 /**
319 * 8 Mailbox Channel Interrupts Routed to Single Interrupt
320 * with 8bit Mask per Destination.
321 */
322 #define QM_IRQ_MAILBOX_0_INT 21
323 #define QM_IRQ_MAILBOX_0_INT_MASK_OFFSET 22
324 #define QM_IRQ_MAILBOX_0_INT_VECTOR 57
325
326 /**
327 * 19 Comparators Routed to Single Interrupt with 19bit Mask per Destination.
328 */
329 #define QM_IRQ_COMPARATOR_0_INT 22
330 #define QM_IRQ_COMPARATOR_0_INT_MASK_OFFSET 26
331 #define QM_IRQ_COMPARATOR_0_INT_VECTOR 58
332
333 /** System and Power Management Single Interrupt. */
334 #define QM_IRQ_PMU_0_INT 23
335 #define QM_IRQ_PMU_0_INT_MASK_OFFSET 27
336 #define QM_IRQ_PMU_0_INT_VECTOR 59
337
338 /**
339 * 8 DMA Channel Error Interrupts Routed to Single Interrupt with 8bit Mask
340 * per Destination.
341 */
342 #define QM_IRQ_DMA_0_ERROR_INT 24
343 #define QM_IRQ_DMA_0_ERROR_INT_MASK_OFFSET 28
344 #define QM_IRQ_DMA_0_ERROR_INT_VECTOR 60
345
346 /** Internal SRAM Memory Protection Error Single Interrupt. */
347 #define QM_IRQ_SRAM_MPR_0_INT 25
348 #define QM_IRQ_SRAM_MPR_0_INT_MASK_OFFSET 29
349 #define QM_IRQ_SRAM_MPR_0_INT_VECTOR 61
350
351 /** Internal Flash Controller 0 Memory Protection Error Single Interrupt. */
352 #define QM_IRQ_FLASH_MPR_0_INT 26
353 #define QM_IRQ_FLASH_MPR_0_INT_MASK_OFFSET 30
354 #define QM_IRQ_FLASH_MPR_0_INT_VECTOR 62
355
356 /** Internal Flash Controller 1 Memory Protection Error Single Interrupt. */
357 #define QM_IRQ_FLASH_MPR_1_INT 27
358 #define QM_IRQ_FLASH_MPR_1_INT_MASK_OFFSET 31
359 #define QM_IRQ_FLASH_MPR_1_INT_VECTOR 63
360
361 /** Always-On Timer Interrupt. */
362 #define QM_IRQ_AONPT_0_INT 28
363 #define QM_IRQ_AONPT_0_INT_MASK_OFFSET 32
364 #define QM_IRQ_AONPT_0_INT_VECTOR 64
365
366 /** ADC power sequence done. */
367 #define QM_SS_IRQ_ADC_0_PWR_INT 29
368 #define QM_SS_IRQ_ADC_0_PWR_INT_MASK_OFFSET 33
369 #define QM_SS_IRQ_ADC_0_PWR_INT_VECTOR 65
370
371 /** ADC calibration done. */
372 #define QM_SS_IRQ_ADC_0_CAL_INT 30
373 #define QM_SS_IRQ_ADC_0_CAL_INT_MASK_OFFSET 34
374 #define QM_SS_IRQ_ADC_0_CAL_INT_VECTOR 66
375
376 /** Always-On GPIO Interrupt. */
377 #define QM_IRQ_AON_GPIO_0_INT 31
378 #define QM_IRQ_AON_GPIO_0_INT_MASK_OFFSET 35
379 #define QM_IRQ_AON_GPIO_0_INT_VECTOR 67
380
381 /** @} */
382
383 /** @} */
384
385 #endif /* __QM_SOC_INTERRUPTS_H__ */