Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_ss_gpio.c
1 /*
2 * {% copyright %}
3 */
4
5 #include "qm_ss_gpio.h"
6
7 static void (*callback[QM_SS_GPIO_NUM])(void *data, uint32_t int_status);
8 static void *callback_data[QM_SS_GPIO_NUM];
9
10 static uint32_t gpio_base[QM_SS_GPIO_NUM] = {QM_SS_GPIO_0_BASE,
11 QM_SS_GPIO_1_BASE};
12
13 static void ss_gpio_isr_handler(qm_ss_gpio_t gpio)
14 {
15 uint32_t int_status = 0;
16 uint32_t controller = gpio_base[gpio];
17
18 int_status = __builtin_arc_lr(controller + QM_SS_GPIO_INTSTATUS);
19
20 if (callback[gpio]) {
21 callback[gpio](callback_data[gpio], int_status);
22 }
23
24 __builtin_arc_sr(int_status, controller + QM_SS_GPIO_PORTA_EOI);
25 }
26
27 QM_ISR_DECLARE(qm_ss_gpio_0_isr)
28 {
29 ss_gpio_isr_handler(QM_SS_GPIO_0);
30 }
31
32 QM_ISR_DECLARE(qm_ss_gpio_1_isr)
33 {
34 ss_gpio_isr_handler(QM_SS_GPIO_1);
35 }
36
37 int qm_ss_gpio_set_config(const qm_ss_gpio_t gpio,
38 const qm_ss_gpio_port_config_t *const cfg)
39 {
40 uint32_t controller, reg_ls_sync_;
41
42 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
43 QM_CHECK(cfg != NULL, -EINVAL);
44
45 controller = gpio_base[gpio];
46
47 #if (HAS_SS_GPIO_CLK_ENABLE)
48 /*
49 * SS GPIO Clock gate (CLKEN) is enabled here, because it is local to
50 * the peripheral block and not a part of the SoC power management clock
51 * gating.
52 */
53 __builtin_arc_sr(BIT(0), controller + QM_SS_GPIO_CLKEN);
54 #endif /* HAS_SS_GPIO_CLK_ENABLE */
55
56 __builtin_arc_sr(0xFFFFFFFF, controller + QM_SS_GPIO_INTMASK);
57
58 __builtin_arc_sr(cfg->direction, controller + QM_SS_GPIO_SWPORTA_DDR);
59 __builtin_arc_sr(cfg->int_type, controller + QM_SS_GPIO_INTTYPE_LEVEL);
60 __builtin_arc_sr(cfg->int_polarity,
61 controller + QM_SS_GPIO_INT_POLARITY);
62 __builtin_arc_sr(cfg->int_debounce, controller + QM_SS_GPIO_DEBOUNCE);
63
64 #if (HAS_SS_GPIO_INTERRUPT_BOTHEDGE)
65 __builtin_arc_sr(cfg->int_bothedge,
66 controller + QM_SS_GPIO_INT_BOTHEDGE);
67 #endif /* HAS_SS_GPIO_INTERRUPT_BOTHEDGE */
68
69 callback[gpio] = cfg->callback;
70 callback_data[gpio] = cfg->callback_data;
71
72 /* Synchronize the level-sensitive interrupts to pclk_intr. */
73 reg_ls_sync_ = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_LS_SYNC);
74 __builtin_arc_sr(reg_ls_sync_ | BIT(0),
75 controller + QM_SS_GPIO_LS_SYNC);
76
77 __builtin_arc_sr(cfg->int_en, controller + QM_SS_GPIO_INTEN);
78
79 __builtin_arc_sr(~cfg->int_en, controller + QM_SS_GPIO_INTMASK);
80
81 return 0;
82 }
83
84 int qm_ss_gpio_read_pin(const qm_ss_gpio_t gpio, const uint8_t pin,
85 qm_ss_gpio_state_t *const state)
86 {
87 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
88 QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
89 QM_CHECK(state != NULL, -EINVAL);
90
91 *state =
92 ((__builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_EXT_PORTA) >> pin) &
93 1);
94
95 return 0;
96 }
97
98 int qm_ss_gpio_set_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
99 {
100 uint32_t val;
101 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
102 QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
103
104 val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR) |
105 BIT(pin);
106 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
107
108 return 0;
109 }
110
111 int qm_ss_gpio_clear_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
112 {
113 uint32_t val;
114 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
115 QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
116
117 val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
118 val &= ~BIT(pin);
119 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
120
121 return 0;
122 }
123
124 int qm_ss_gpio_set_pin_state(const qm_ss_gpio_t gpio, const uint8_t pin,
125 const qm_ss_gpio_state_t state)
126 {
127 uint32_t val;
128 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
129 QM_CHECK(state < QM_SS_GPIO_STATE_NUM, -EINVAL);
130
131 val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
132 val ^= (-state ^ val) & (1 << pin);
133 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
134
135 return 0;
136 }
137
138 int qm_ss_gpio_read_port(const qm_ss_gpio_t gpio, uint32_t *const port)
139 {
140 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
141 QM_CHECK(port != NULL, -EINVAL);
142
143 *port = (__builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_EXT_PORTA));
144
145 return 0;
146 }
147
148 int qm_ss_gpio_write_port(const qm_ss_gpio_t gpio, const uint32_t val)
149 {
150 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
151
152 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
153
154 return 0;
155 }
156
157 #if (ENABLE_RESTORE_CONTEXT)
158 int qm_ss_gpio_save_context(const qm_ss_gpio_t gpio,
159 qm_ss_gpio_context_t *const ctx)
160 {
161 uint32_t controller;
162
163 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
164 QM_CHECK(ctx != NULL, -EINVAL);
165
166 controller = gpio_base[gpio];
167
168 ctx->gpio_swporta_dr =
169 __builtin_arc_lr(controller + QM_SS_GPIO_SWPORTA_DR);
170 ctx->gpio_swporta_ddr =
171 __builtin_arc_lr(controller + QM_SS_GPIO_SWPORTA_DDR);
172 ctx->gpio_inten = __builtin_arc_lr(controller + QM_SS_GPIO_INTEN);
173 ctx->gpio_intmask = __builtin_arc_lr(controller + QM_SS_GPIO_INTMASK);
174 ctx->gpio_inttype_level =
175 __builtin_arc_lr(controller + QM_SS_GPIO_INTTYPE_LEVEL);
176 ctx->gpio_int_polarity =
177 __builtin_arc_lr(controller + QM_SS_GPIO_INT_POLARITY);
178 ctx->gpio_debounce = __builtin_arc_lr(controller + QM_SS_GPIO_DEBOUNCE);
179 ctx->gpio_ls_sync = __builtin_arc_lr(controller + QM_SS_GPIO_LS_SYNC);
180
181 return 0;
182 }
183
184 int qm_ss_gpio_restore_context(const qm_ss_gpio_t gpio,
185 const qm_ss_gpio_context_t *const ctx)
186 {
187 uint32_t controller;
188
189 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
190 QM_CHECK(ctx != NULL, -EINVAL);
191
192 controller = gpio_base[gpio];
193
194 __builtin_arc_sr(0xffffffff, controller + QM_SS_GPIO_INTMASK);
195 __builtin_arc_sr(ctx->gpio_swporta_dr,
196 controller + QM_SS_GPIO_SWPORTA_DR);
197 __builtin_arc_sr(ctx->gpio_swporta_ddr,
198 controller + QM_SS_GPIO_SWPORTA_DDR);
199 __builtin_arc_sr(ctx->gpio_inten, controller + QM_SS_GPIO_INTEN);
200 __builtin_arc_sr(ctx->gpio_inttype_level,
201 controller + QM_SS_GPIO_INTTYPE_LEVEL);
202 __builtin_arc_sr(ctx->gpio_int_polarity,
203 controller + QM_SS_GPIO_INT_POLARITY);
204 __builtin_arc_sr(ctx->gpio_debounce, controller + QM_SS_GPIO_DEBOUNCE);
205 __builtin_arc_sr(ctx->gpio_ls_sync, controller + QM_SS_GPIO_LS_SYNC);
206 __builtin_arc_sr(ctx->gpio_intmask, controller + QM_SS_GPIO_INTMASK);
207
208 return 0;
209 }
210 #else
211 int qm_ss_gpio_save_context(const qm_ss_gpio_t gpio,
212 qm_ss_gpio_context_t *const ctx)
213 {
214 (void)gpio;
215 (void)ctx;
216
217 return 0;
218 }
219
220 int qm_ss_gpio_restore_context(const qm_ss_gpio_t gpio,
221 const qm_ss_gpio_context_t *const ctx)
222 {
223 (void)gpio;
224 (void)ctx;
225
226 return 0;
227 }
228 #endif /* ENABLE_RESTORE_CONTEXT */
qm_ss_gpio_state_t
qm_ss_gpio_state_t
GPIO SS pin states.
Definition: qm_ss_gpio.h:21
qm_ss_gpio_context_t::gpio_swporta_ddr
uint32_t gpio_swporta_ddr
Port A Data Direction.
Definition: qm_sensor_regs.h:182
qm_ss_gpio_context_t::gpio_debounce
uint32_t gpio_debounce
Debounce Enable.
Definition: qm_sensor_regs.h:187
qm_ss_gpio_port_config_t::int_type
uint32_t int_type
Interrupt type, 0b: level; 1b: edge.
Definition: qm_ss_gpio.h:35
qm_ss_gpio_t
qm_ss_gpio_t
Sensor Subsystem GPIO.
Definition: qm_sensor_regs.h:196
qm_ss_gpio_port_config_t::int_polarity
uint32_t int_polarity
Interrupt polarity, 0b: low, 1b: high.
Definition: qm_ss_gpio.h:36
qm_ss_gpio_port_config_t::int_en
uint32_t int_en
Interrupt enable.
Definition: qm_ss_gpio.h:34
qm_ss_gpio_context_t::gpio_int_polarity
uint32_t gpio_int_polarity
Interrupt Polarity.
Definition: qm_sensor_regs.h:186
qm_ss_gpio_save_context
int qm_ss_gpio_save_context(const qm_ss_gpio_t gpio, qm_ss_gpio_context_t *const ctx)
Save SS GPIO context.
Definition: qm_ss_gpio.c:158
QM_SS_GPIO_STATE_NUM
Number of states.
Definition: qm_ss_gpio.h:24
qm_ss_gpio_context_t::gpio_intmask
uint32_t gpio_intmask
Interrupt Mask.
Definition: qm_sensor_regs.h:184
qm_ss_gpio_set_pin
int qm_ss_gpio_set_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
Set a single pin on a given SS GPIO port.
Definition: qm_ss_gpio.c:98
qm_ss_gpio_port_config_t::int_bothedge
uint32_t int_bothedge
Interrupt on rising and falling edges.
Definition: qm_ss_gpio.h:40
QM_ISR_DECLARE
QM_ISR_DECLARE(qm_ss_gpio_0_isr)
ISR for GPIO 0 error interrupt.
Definition: qm_ss_gpio.c:27
qm_ss_gpio_clear_pin
int qm_ss_gpio_clear_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
Clear a single pin on a given SS GPIO port.
Definition: qm_ss_gpio.c:111
qm_ss_gpio_port_config_t
SS GPIO port configuration type.
Definition: qm_ss_gpio.h:32
qm_ss_gpio_set_pin_state
int qm_ss_gpio_set_pin_state(const qm_ss_gpio_t gpio, const uint8_t pin, const qm_ss_gpio_state_t state)
Set or clear a single SS GPIO pin using a state variable.
Definition: qm_ss_gpio.c:124
qm_ss_gpio_context_t::gpio_inttype_level
uint32_t gpio_inttype_level
Interrupt Type.
Definition: qm_sensor_regs.h:185
qm_ss_gpio_write_port
int qm_ss_gpio_write_port(const qm_ss_gpio_t gpio, const uint32_t val)
Get SS GPIO port values.
Definition: qm_ss_gpio.c:148
qm_ss_gpio_read_port
int qm_ss_gpio_read_port(const qm_ss_gpio_t gpio, uint32_t *const port)
Get SS GPIO port values.
Definition: qm_ss_gpio.c:138
qm_ss_gpio_set_config
int qm_ss_gpio_set_config(const qm_ss_gpio_t gpio, const qm_ss_gpio_port_config_t *const cfg)
Set SS GPIO port configuration.
Definition: qm_ss_gpio.c:37
qm_ss_gpio_read_pin
int qm_ss_gpio_read_pin(const qm_ss_gpio_t gpio, const uint8_t pin, qm_ss_gpio_state_t *const state)
Read the current value of a single pin on a given SS GPIO port.
Definition: qm_ss_gpio.c:84
qm_ss_gpio_context_t::gpio_inten
uint32_t gpio_inten
Interrupt Enable.
Definition: qm_sensor_regs.h:183
qm_ss_gpio_restore_context
int qm_ss_gpio_restore_context(const qm_ss_gpio_t gpio, const qm_ss_gpio_context_t *const ctx)
Restore SS GPIO context.
Definition: qm_ss_gpio.c:184
qm_ss_gpio_port_config_t::callback
void(* callback)(void *data, uint32_t int_status)
User callback.
Definition: qm_ss_gpio.h:51
qm_ss_gpio_context_t
SS GPIO context type.
Definition: qm_sensor_regs.h:180
qm_ss_gpio_context_t::gpio_swporta_dr
uint32_t gpio_swporta_dr
Port A Data.
Definition: qm_sensor_regs.h:181
qm_ss_gpio_port_config_t::direction
uint32_t direction
SS GPIO direction, 0b: input, 1b: output.
Definition: qm_ss_gpio.h:33
qm_ss_gpio_port_config_t::int_debounce
uint32_t int_debounce
Debounce on/off.
Definition: qm_ss_gpio.h:37
qm_ss_gpio_port_config_t::callback_data
void * callback_data
Callback user data.
Definition: qm_ss_gpio.h:52
qm_ss_gpio_context_t::gpio_ls_sync
uint32_t gpio_ls_sync
Synchronization Level.
Definition: qm_sensor_regs.h:188