Intel® Quark™ Microcontroller Software Interface 1.4.0 Intel® Quark™ Microcontroller BSP

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qm_isr.h
1 /*
2 * {% copyright %}
3 */
4
5 #ifndef __QM_ISR_H__
6 #define __QM_ISR_H__
7
8 #include "qm_common.h"
9 #include "qm_soc_regs.h"
10
11 /**
12 * Interrupt Service Routines.
13 *
14 * @defgroup groupISR ISR
15 * @{
16 */
17
18 #if (QUARK_D2000)
19 /**
20 * ISR for ADC 0 convert and calibration interrupt.
21 *
22 * This function needs to be registered with
23 * @code QM_IRQ_REQUEST(QM_IRQ_ADC_0_CAL_INT, qm_adc_0_cal_isr);
24 * @endcode if IRQ based transfers are used.
25 */
26 QM_ISR_DECLARE(qm_adc_0_cal_isr);
27
28 /**
29 * ISR for ADC 0 change mode interrupt.
30 *
31 * This function needs to be registered with
32 * @code QM_IRQ_REQUEST(QM_IRQ_ADC_0_PWR_INT, qm_adc_0_pwr_isr);
33 * @endcode if IRQ based transfers are used.
34 */
35 QM_ISR_DECLARE(qm_adc_0_pwr_isr);
36 #endif /* QUARK_D2000 */
37
38 /**
39 * ISR for Always-on Periodic Timer 0 interrupt.
40 *
41 * This function needs to be registered with
42 * @code QM_IRQ_REQUEST(QM_IRQ_AONPT_0_INT, qm_aonpt_0_isr);
43 * @endcode if IRQ based transfers are used.
44 */
45 QM_ISR_DECLARE(qm_aonpt_0_isr);
46
47 /**
48 * ISR for Analog Comparator 0 interrupt.
49 *
50 * This function needs to be registered with
51 * @code QM_IRQ_REQUEST(QM_IRQ_COMPARATOR_0_INT, qm_comparator_0_isr);
52 * @endcode if IRQ based transfers are used.
53 */
54 QM_ISR_DECLARE(qm_comparator_0_isr);
55
56 /**
57 * ISR for DMA error interrupt.
58 *
59 * This function needs to be registered with
60 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_ERROR_INT, qm_dma_0_error_isr);
61 * @endcode if IRQ based transfers are used.
62 */
63 QM_ISR_DECLARE(qm_dma_0_error_isr);
64
65 /**
66 * ISR for DMA channel 0 interrupt.
67 *
68 * This function needs to be registered with
69 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_0, qm_dma_0_isr_0);
70 * @endcode if IRQ based transfers are used.
71 */
72 QM_ISR_DECLARE(qm_dma_0_isr_0);
73
74 /**
75 * ISR for DMA channel 1 interrupt.
76 *
77 * This function needs to be registered with
78 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_1, qm_dma_0_isr_1);
79 * @endcode if IRQ based transfers are used.
80 */
81 QM_ISR_DECLARE(qm_dma_0_isr_1);
82
83 #if (QUARK_SE)
84 /**
85 * ISR for DMA channel 2 interrupt.
86 *
87 * This function needs to be registered with
88 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_2, qm_dma_0_isr_2);
89 * @endcode if IRQ based transfers are used.
90 */
91 QM_ISR_DECLARE(qm_dma_0_isr_2);
92
93 /**
94 * ISR for DMA channel 3 interrupt.
95 *
96 * This function needs to be registered with
97 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_3, qm_dma_0_isr_3);
98 * @endcode if IRQ based transfers are used.
99 */
100 QM_ISR_DECLARE(qm_dma_0_isr_3);
101
102 /**
103 * ISR for DMA channel 4 interrupt.
104 *
105 * This function needs to be registered with
106 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_4, qm_dma_0_isr_4);
107 * @endcode if IRQ based transfers are used.
108 */
109 QM_ISR_DECLARE(qm_dma_0_isr_4);
110
111 /**
112 * ISR for DMA channel 5 interrupt.
113 *
114 * This function needs to be registered with
115 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_5, qm_dma_0_isr_5);
116 * @endcode if IRQ based transfers are used.
117 */
118 QM_ISR_DECLARE(qm_dma_0_isr_5);
119
120 /**
121 * ISR for DMA channel 6 interrupt.
122 *
123 * This function needs to be registered with
124 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_6, qm_dma_0_isr_6);
125 * @endcode if IRQ based transfers are used.
126 */
127 QM_ISR_DECLARE(qm_dma_0_isr_6);
128
129 /**
130 * ISR for DMA 0 channel 7 interrupt.
131 *
132 * This function needs to be registered with
133 * @code QM_IRQ_REQUEST(QM_IRQ_DMA_0_INT_7, qm_dma_0_isr_7);
134 * @endcode if IRQ based transfers are used.
135 */
136 QM_ISR_DECLARE(qm_dma_0_isr_7);
137 #endif /* QUARK_SE */
138
139 /**
140 * ISR for FPR 0 interrupt.
141 *
142 * This function needs to be registered with
143 * @code QM_IRQ_REQUEST(QM_IRQ_FLASH_MPR_0_INT, qm_flash_mpr_0_isr);
144 * @endcode if IRQ based transfers are used.
145 */
146 QM_ISR_DECLARE(qm_flash_mpr_0_isr);
147
148 /**
149 * ISR for FPR 1 interrupt.
150 *
151 * This function needs to be registered with
152 * @code QM_IRQ_REQUEST(QM_IRQ_FLASH_MPR_1_INT, qm_flash_mpr_1_isr);
153 * @endcode if IRQ based transfers are used.
154 */
155 QM_ISR_DECLARE(qm_flash_mpr_1_isr);
156
157 /**
158 * ISR for GPIO 0 interrupt.
159 *
160 * This function needs to be registered with
161 * @code QM_IRQ_REQUEST(QM_IRQ_GPIO_0_INT, qm_gpio_0_isr);
162 * @endcode if IRQ based transfers are used.
163 */
164 QM_ISR_DECLARE(qm_gpio_0_isr);
165
166 #if (HAS_AON_GPIO)
167 /**
168 * ISR for AON GPIO 0 interrupt.
169 *
170 * This function needs to be registered with
171 * @code QM_IRQ_REQUEST(QM_IRQ_AON_GPIO_0_INT, qm_aon_gpio_0_isr);
172 * @endcode if IRQ based transfers are used.
173 */
174 QM_ISR_DECLARE(qm_aon_gpio_0_isr);
175 #endif /* HAS_AON_GPIO */
176
177 /**
178 * ISR for I2C 0 irq mode transfer interrupt.
179 *
180 * This function needs to be registered with
181 * @code QM_IRQ_REQUEST(QM_IRQ_I2C_0_INT, qm_i2c_0_irq_isr);
182 * @endcode if IRQ based transfers are used.
183 */
184 QM_ISR_DECLARE(qm_i2c_0_irq_isr);
185
186 /**
187 * ISR for I2C 1 irq mode transfer interrupt.
188 *
189 * This function needs to be registered with
190 * @code QM_IRQ_REQUEST(QM_IRQ_I2C_1_INT, qm_i2c_1_irq_isr);
191 * @endcode if IRQ based transfers are used.
192 */
193 QM_ISR_DECLARE(qm_i2c_1_irq_isr);
194
195 /**
196 * ISR for I2C 0 dma mode transfer interrupt.
197 *
198 * This function needs to be registered with
199 * @code QM_IRQ_REQUEST(QM_IRQ_I2C_0_INT, qm_i2c_0_dma_isr);
200 * @endcode if DMA based transfers are used.
201 */
202 QM_ISR_DECLARE(qm_i2c_0_dma_isr);
203
204 /**
205 * ISR for I2C 1 dma mode transfer interrupt.
206 *
207 * This function needs to be registered with
208 * @code QM_IRQ_REQUEST(QM_IRQ_I2C_1_INT, qm_i2c_1_dma_isr);
209 * @endcode if DMA based transfers are used.
210 */
211 QM_ISR_DECLARE(qm_i2c_1_dma_isr);
212
213 /**
214 * ISR for Mailbox interrupt.
215 *
216 * This function needs to be registered with
217 * @code QM_IRQ_REQUEST(QM_IRQ_MAILBOX_0_INT, qm_mailbox_0_isr);
218 * @endcode if IRQ based transfers are used.
219 */
220 QM_ISR_DECLARE(qm_mailbox_0_isr);
221
222 /**
223 * ISR for Memory Protection Region interrupt.
224 *
225 * This function needs to be registered with
226 * @code QM_IRQ_REQUEST(QM_IRQ_SRAM_MPR_0_INT, qm_sram_mpr_0_isr);
227 * @endcode if IRQ based transfers are used.
228 */
229 QM_ISR_DECLARE(qm_sram_mpr_0_isr);
230
231 /**
232 * ISR for PIC Timer interrupt.
233 *
234 * On Quark Microcontroller D2000 Development Platform,
235 * this function needs to be registered with:
236 * @code qm_int_vector_request(QM_X86_PIC_TIMER_INT_VECTOR,
237 * qm_pic_timer_0_isr);
238 * @endcode if IRQ based transfers are used.
239 *
240 * On Quark SE, this function needs to be registered with:
241 * @code QM_IRQ_REQUEST(QM_IRQ_PIC_TIMER, qm_pic_timer_0_isr);
242 * @endcode if IRQ based transfers are used.
243 */
244 QM_ISR_DECLARE(qm_pic_timer_0_isr);
245
246 /**
247 * ISR for PWM 0 Channel 0 interrupt.
248 * If there is only one interrupt per controller this ISR handles
249 * all channel interrupts.
250 *
251 * This function needs to be registered with
252 * @code QM_IRQ_REQUEST(QM_IRQ_PWM_0_INT, qm_pwm_0_isr);
253 * @endcode if IRQ based transfers are used.
254 */
255 QM_ISR_DECLARE(qm_pwm_0_isr_0);
256
257 #if (NUM_PWM_CONTROLLER_INTERRUPTS > 1)
258 /**
259 * ISR for PWM 0 channel 1 interrupt.
260 *
261 * This function needs to be registered with
262 * @code qm_irq_request(QM_IRQ_PWM_1, qm_pwm_0_isr_1);
263 * @endcode if IRQ based transfers are used.
264 */
265 QM_ISR_DECLARE(qm_pwm_0_isr_1);
266
267 /**
268 * ISR for PWM 0 channel 2 interrupt.
269 *
270 * This function needs to be registered with
271 * @code qm_irq_request(QM_IRQ_PWM_2, qm_pwm_0_isr_2);
272 * @endcode if IRQ based transfers are used.
273 */
274 QM_ISR_DECLARE(qm_pwm_0_isr_2);
275
276 /**
277 * ISR for PWM 0 channel 3 interrupt.
278 *
279 * This function needs to be registered with
280 * @code qm_irq_request(QM_IRQ_PWM_3, qm_pwm_0_isr_3);
281 * @endcode if IRQ based transfers are used.
282 */
283 QM_ISR_DECLARE(qm_pwm_0_isr_3);
284
285 #endif /* NUM_PWM_CONTROLLER_INTERRUPTS > 1 */
286
287 /**
288 * ISR for RTC 0 interrupt.
289 *
290 * This function needs to be registered with
291 * @code QM_IRQ_REQUEST(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);
292 * @endcode if IRQ based transfers are used.
293 */
294 QM_ISR_DECLARE(qm_rtc_0_isr);
295
296 /**
297 * ISR for SPI Master 0 interrupt.
298 *
299 * This function needs to be registered with
300 * @code QM_IRQ_REQUEST(QM_IRQ_SPI_MASTER_0_INT, qm_spi_master_0_isr);
301 * @endcode if IRQ based transfers are used.
302 */
303 QM_ISR_DECLARE(qm_spi_master_0_isr);
304
305 #if (QUARK_SE)
306 /**
307 * ISR for SPI Master 1 interrupt.
308 *
309 * This function needs to be registered with
310 * @code QM_IRQ_REQUEST(QM_IRQ_SPI_MASTER_1_INT, qm_spi_master_1_isr);
311 * @endcode if IRQ based transfers are used.
312 */
313 QM_ISR_DECLARE(qm_spi_master_1_isr);
314 #endif /* (QUARK_SE) */
315
316 /**
317 * ISR for SPI Slave 0 interrupt.
318 *
319 * This function needs to be registered with
320 * @code qm_irq_request(QM_IRQ_SPI_SLAVE_0_INT, qm_spi_slave_0_isr);
321 * @endcode if IRQ based transfers are used.
322 */
323 QM_ISR_DECLARE(qm_spi_slave_0_isr);
324
325 /**
326 * ISR for UART 0 interrupt.
327 *
328 * This function needs to be registered with
329 * @code QM_IRQ_REQUEST(QM_IRQ_UART_0_INT, qm_uart_0_isr);
330 * @endcode if IRQ based transfers are used.
331 */
332 QM_ISR_DECLARE(qm_uart_0_isr);
333
334 /**
335 * ISR for UART 1 interrupt.
336 *
337 * This function needs to be registered with
338 * @code QM_IRQ_REQUEST(QM_IRQ_UART_1_INT, qm_uart_1_isr);
339 * @endcode if IRQ based transfers are used.
340 */
341 QM_ISR_DECLARE(qm_uart_1_isr);
342
343 /**
344 * ISR for WDT 0 interrupt.
345 *
346 * This function needs to be registered with
347 * @code QM_IRQ_REQUEST(QM_IRQ_WDT_0_INT, qm_wdt_0_isr);
348 * @endcode if IRQ based transfers are used.
349 */
350 QM_ISR_DECLARE(qm_wdt_0_isr);
351
352 #if (NUM_WDT_CONTROLLERS > 1)
353 /**
354 * ISR for WDT 1 interrupt.
355 *
356 * This function needs to be registered with
357 * @code QM_IRQ_REQUEST(QM_IRQ_WDT_1_INT, qm_wdt_1_isr);
358 * @endcode if IRQ based transfers are used.
359 */
360 QM_ISR_DECLARE(qm_wdt_1_isr);
361 #endif /* NUM_WDT_CONTROLLERS > 1 */
362
363 /**
364 * ISR for USB 0 interrupt.
365 *
366 * This function needs to be registered with
367 * @code QM_IRQ_REQUEST(QM_IRQ_USB_0_INT, qm_usb_0_isr);
368 * @endcode if IRQ based transfers are used.
369 */
370 QM_ISR_DECLARE(qm_usb_0_isr);
371
372 /**
373 * @}
374 */
375
376 #endif /* __QM_ISR_H__ */
QM_ISR_DECLARE
QM_ISR_DECLARE(qm_adc_0_cal_isr)
ISR for ADC 0 convert and calibration interrupt.
Definition: qm_adc.c:166