This section lets you specify timing delays for
the backlight signals as follows:
• T1-VDD active and sDVO clock/data active.
• T2-DVO active and backlight enable.
• T3-Backlight disable and DVO clock/data
inactive.
• T4-DVO clock/data active and inactive.
• T5-Minimum from VDD inactive and active.
For Internal LVDS, the timing range is as follows:
• T1 to T4: 0-409, increment by 1.
• T5: 1-1600, increment by 50.
For CH7308,CH7036,STM* IOH ConneXt and Lapis Semiconductor*
ML7213, the timing range is as follows:
• T1 to T4: 0-4095, increment by 1.
• T5: 1-<Max 4 byte integer value>,
increment by 50.
Note:
Timers are very specific to the panel you are using. If
they are set incorrectly the display can be damaged or ruined. Please
refer to the datasheet for your display to determine the correct settings.
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