KOH_CreatingaNewCustDTD

Creating a New Customized DTD

CED allows you to create Dynamic Timings Definitions (DTD) for EDID-less displays or displays for which you do not want to use the display's EDID settings. In either of those cases, you can create your own DTD using the steps below. Otherwise you can use one of the standard DTDs included in CED.

You can create a new DTD by clicking the New DTD link at the top of the main CED window, or you can create DTDs for each configured port when you create a new configuration. Any DTDs you create will be available for all configurations.

When you select New DTD from the main CED window, the following Intel® EMGD DTD Page appears.

EMGD DTD Page

 

To create a custom DTD setting:

1. From the CED main screen, select New DTD.

2. Enter a name for the DTD in the text box provided, for example, test_LVDS.

3. Using the data sheet from the panel being used, enter the DTD timings in the appropriate fields. Refer to Table 6, “Intel® EMGD DTD Setting Options” for field descriptions.

The screen will be similar to the example shown in EMGD DTD Page.

4. Click Finish.

The custom DTD is complete.

Table 6. Intel® EMGD DTD Setting Options

DTD Parameter

Description

Enter DTD File Name

Enter a name for this customized DTD. This is a required field and the name must be between 1 and 50 characters and may contain spaces and underscores.

DTD Type

Select the DTD Type that most closely aligns with your display parameters. Options are:

• Intel® EMGD Parameters:
The Intel® EMGD Parameters are the same as the current PCF/CED DTD parameters.

VESA Parameters:
The VESA Parameters allow the user to create a DTD from a VESA monitor timing standard.

Hardware Parameters:
The Hardware Parameters are the parameters that are used by Intel® EMGD.

Simple Parameters:
The Simple Parameters (CVT Standard) is a process for computing standard timing specifications. The method for developing Reduced Blanking timings is not included.

Mode Lines:
The Mode Lines are a video timing spec used by X.Org. The X.Org timing setting for Mode Lines is “name” I A B C D E F G H. For example: “640x480@8bpp” 25.175 640 672 728 816 480 489 501 526.

EDID Block:
The EDID Block is the detailed timing section (18 bytes) of the basic 128-byte EDID data structure. The detailed timing section starts at 36h of the 128-byte EDID data structure. Enter the EDID block 1 byte at a time. Example:
a0 0f 20 00 31 58 1c 20 d2 1a 14 00 f6 b8 00 00 00 18

Pixel Clock

Pixel clock value in KHz. Range 0-0x7fffffff.

DTD Settings Flags

This section allows you to set flags for Interlace, Vertical Sync Polarity, Horizontal Sync Polarity, and Blank Sync Polarity. Each field in this section is described below.

Interlaced Display:

• Check for Interlaced

• Cleared for Non-interlaced

Vertical Sync Polarity:

• Active Low (Default)

• Active High

Horizontal Sync Polarity:

• Active Low (Default)

• Active High

Blank Sync Polarity:

• Active Low (Default)

• Active High

 

Note: These flags are Intel® EMGD-specific and do not correspond to VESA 3.0 flags.

Horizontal Sync Offset (Front Porch) in pixels

Specifies the amount of time after a line of the active video ends and the horizontal sync pulse starts (Horizontal Front Porch). Range 0-1023 [10 bits].

Horizontal Sync Pulse Width (Sync Time) in pixels

Width of the Horizontal Sync Pulse (Sync Time) which synchronizes the display and returns the beam to the left side of the display. Range 0-1023 [10 bits].

Horizontal Blank Width (Blank Time) in pixels

This parameter indicates the amount of time it takes to move the beam from the right side of the display to the left side of the display (Blank Time). During this time, the beam is shut off, or blanked. Range 0-4095 [12 bits].

Horizontal Active (Width) in pixels

Number of pixels displayed on a horizontal line (Width). Range 1-32767 [15 bits].

Horizontal Sync Start in pixels

This parameter specifies the start of the horizontal active time.
Range 0-40957.

Horizontal Sync End in pixels

This parameter specifies the end of the horizontal active time.
Range 0-49148.

Horizontal Blank Start in pixels

This parameter specifies the start of one line of the video and margin period. Range 0-32766.

Horizontal Blank End in pixels

This parameter specifies the end of one line of the video and margin period. Range 0-65533.

Refresh in Hz

Also known as the Vertical Refresh, the rate the full display updates. Standard refresh rates are 50Hz, 60Hz, 75Hz, and 85Hz.

Vertical Sync Offset (Front Porch) in lines

Specifies the amount of time after last active line of video ends and vertical sync pulse starts (Vertical Front Porch). Range 0-4095 [12 bits].

Vertical Sync Pulse Width (Sync Time) in lines

Specifies the Width of the Vertical Sync Pulse which synchronizes the display on the vertical axis and returns the beam to the top, left side of the display. Range 0-63 [6 bits].

Vertical Blank Width (Blank Time) in lines

The amount of time for the complete vertical blanking operation to complete. It indicates the time it takes to move the beam from the bottom right to the top, left side of the display (Blank Time). During this time, the beam is shut off, or blanked. Range 0-4095 [12 bits].

Vertical Active (Height) in lines

The number of active lines displayed (Height). Range 1-4095 [12 bits].

Vertical Sync Start in lines

This parameter specifies the start of the vertical sync. Range 0-4157.

Vertical Sync End in lines

This parameter specifies the end of the vertical sync. Range 0-4220.

Vertical Blank Start in lines

This parameter specifies the start of display vertical blanking including margin period. Range 0-4094.

Vertical Blank End in lines

This parameter specifies the end of vertical blanking. Range 0-8189.

DTD Example Specifications

The following table shows example product specifications that can be used in the timing fields.

Table 7. Timing Specification Example Values

Item

Symbol

Standard value

Unit

Min.

Typ.

Max.

Clock

Frequency

1/ts

29.91

33.231

36.55

MHz

Period

ts

27.36

30.06

33.43

ns

Hi-time

tsh

7

ns

Low-time

tsl

7

ns

DUTY ratio

th/tl

35

50

65

ns

Data

Setup time

tds

7

ns

Hold time

tdh

4

ns

H sync.

Period

tlpl, tlpd

24.51

31.75

32.05

us

880

1056

1088

clk

Pulse width

tlw

3

128

200

clk

H display

Term

thd

800

800

800

clk

Enable

Setup time

tdrs

7

ns

Hold time

tdrh

4

ns

V sync.

Period

tfpf, tfpd

520

525

680

Line

Pulse width

tfw

1

2

3

Line

V display

Term

tvd

480

480

480

Line

Start

tfd

10

33

40

Line

Phase difference

H sync. ~ enable

tdrds

50

216

260

clk

H sync. ~ clock

tls

7

ns

H sync. ~V sync.

tn

7

ns

For information about creating DTDs for Windows Embedded Compact 7, see Configuring and Building Intel® EMGD for Microsoft Windows* Embedded Compact 7




*Other names and brands may be claimed as the property of others.
Revised April 2013